WO2002001345A2 - Method and apparatus for arbitration of concurrent processes in multiprocessor systems - Google Patents

Method and apparatus for arbitration of concurrent processes in multiprocessor systems Download PDF

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Publication number
WO2002001345A2
WO2002001345A2 PCT/EP2001/007193 EP0107193W WO0201345A2 WO 2002001345 A2 WO2002001345 A2 WO 2002001345A2 EP 0107193 W EP0107193 W EP 0107193W WO 0201345 A2 WO0201345 A2 WO 0201345A2
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WO
WIPO (PCT)
Prior art keywords
bus
main processor
processor
secondary processor
access
Prior art date
Application number
PCT/EP2001/007193
Other languages
French (fr)
Other versions
WO2002001345A3 (en
Inventor
Valter Bella
Marco Gandini
Original Assignee
Telecom Italia Lab S.P.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecom Italia Lab S.P.A. filed Critical Telecom Italia Lab S.P.A.
Publication of WO2002001345A2 publication Critical patent/WO2002001345A2/en
Publication of WO2002001345A3 publication Critical patent/WO2002001345A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Definitions

  • This invention relates to systems managed by microprocessors and in particular relates to a method and an apparatus for arbitration of concurrent processes in multiprocessor systems.
  • processors coexist in multiprocessor systems implemented in diverse technologies, for example in second generation - and presumably third generation - mobile telephone apparatuses. Despite performing different tasks, the processors must asynchronously access common resources. These usually include external memory elements on a shared bus, on which the various devices in the system communicate. A method for the arbitration of said concurrent processes is required.
  • the various devices in the system comprise “master” devices and “slave” devices.
  • the master devices include processors, such as RISC (Reduced Instruction Set Computer) and DSP (Digital Signal Processor) devices.
  • Slave devices include various interfaces, such as UART (Universal Asynchronous Receiver/Transmitter) devices, display managers, keyboard managers, coprocessors, buzzers, etc.
  • UART Universal Asynchronous Receiver/Transmitter
  • the external memory elements required by the processors for operation are usually reduced to two: one FLASH memory and one RAM (Random Access Memory). Since both must be either read or written by the processors, in undetermined instants of time, arbitration capable of governing the connections on the basis of a priority management is required to prevent the risk of access conflicts.
  • This function is generally performed by the RISC processor, which manages the RTOS (Real Time Operative System), i.e. for managing tasks and accesses to external memories of all devices on the shared bus.
  • RTOS Real Time Operative System
  • the DSP manages the data processing operations, such as radio communication channel data, audio source samples, which may be compressed in the case of a mobile telephone system.
  • a critical condition occurs when one of the two processors needs to access the memory resources, while connection has been established with the other processor. This is due to the fact that, by working both processors at high priority, the memories must be accessed in an alternating and exclusive way. Consequently, if one of the two is reading or writing data, the other must wait until the end of the operation. These operations may have also very different duration for the two processors, and therefore one of the two could be penalised.
  • the RISC operating method is a succession of fast task assignments, which is priority with respect to other devices, while the DSP, once enabled to work at top priority, takes on a large amount of processing, which can considerably protract in time. During these operations, the DSP negates return of the control to the RISC, which consequently cannot access the external memories to extract instructions for the subsequent tasks. Consequently, the operating system is in fact blocked.
  • the method and the apparatus according to this invention prevent said shortcomings and solve the technical problem described above, permitting the DSP to fully perform the assigned task without precluding the possibility of the RISC to reassume control of the system when required, avoiding the memory resource access redundancy described above.
  • this invention relates to a method and an apparatus for arbitration of concurrent processes in multiprocessor systems as described in the characterising preamble of claim 1.
  • Fig. 1 is a block diagram of a multiprocessor system with shared memories
  • Fig. 2 is a block diagram of the block indicated as IME in Fig. 1.
  • RISC processor loads a set of instructions, forming the operating system, from the FLASH memory for managing assignment of tasks to the other system devices, and the information for arbitration of the concurrent processes, i.e. for assigning the various priorities for shared external memory access.
  • the RISC Before assigning priority to the DSP, the RISC establishes the number of transactions that the DSP can perform when accessing external memories before returning the control to the RISC. This number is regularly changed at each cycle, i.e. decreased to reach a predetermined value, which determines overriding and ending the task performed by the DSP.
  • the RISC can assign a new number of transactions to the DSP, which can be easily programmable a priori.
  • This initial set of instructions can be periodically updated by the external management control software control.
  • FIG. 1 shows a typical architecture implementing the method according to this invention.
  • BD and BR indicate the buses devoted to the DSP processor, indicated with DS, and the RISC processor, indicated with RI. Both buses access the external memory elements F and R, a FLASH memory and a RAM memory, respectively, via an interface device IME.
  • peripherals SL1, ..., SLn are connected to the bus BR for performing the normal functions of an evolved multiprocessor system, such as UART devices, display interfaces, keyboard interfaces, buzzers, etc., and a local memory MR, for the management of temporary data.
  • an evolved multiprocessor system such as UART devices, display interfaces, keyboard interfaces, buzzers, etc.
  • a local memory MR for the management of temporary data.
  • a local memory MD is connected to the bus BD.
  • access requests to the external memories F and R can be advanced on both buses.
  • only one bus is enabled by the RISC by assigning a priority made via a wire FP. If, the priority is assigned to the DSP, this engages a bus BE (via the interface IME), connected to the external memories F and R, and transfers the data on the bus.
  • a programmable counter is arranged in the IME interface.
  • the counter can be dynamically pre-set, via bus BR controlled by the RISC, to an optimal value for performing the task assigned by the DSP at that time.
  • the DSP assumes control of the bus BE, the value set on the counter is decreased at each external memory element access transaction, and when zero is reached, the system control is reassigned to the BR bus and, consequently, to the RISC.
  • This method is repeated for all the subsequent steps with an initial value set in the counter by the RISC, which may be different from the one above, in order to optimise the processing times connected to the DSP in view of the assigned task.
  • the IME interface is illustrated in greater detail in Fig. 2.
  • It comprises a combinatory logic LC, which is accessed by the buses BD, BR and BE, a finite state machine FSM, managing access priority, and a counter C, which can be dynamically pre-set via the BR bus.

Abstract

The method and the apparatus of this invention apply to a multiprocessor system in which a main processor RISC and a secondary processor DSP share the same external memory resources. The method permits arbitration of concurrent processes, particularly shared memory reading and writing operations, so that the DSP can adequately perform the assigned task without precluding the possibility of the RISC to reassume control of the system when required and thus preventing memory resource access redundancy.

Description

Method and apparatus for arbitration of concurrent processes in multiprocessor systems
Technical Field
This invention relates to systems managed by microprocessors and in particular relates to a method and an apparatus for arbitration of concurrent processes in multiprocessor systems.
Background Art
Several processors coexist in multiprocessor systems implemented in diverse technologies, for example in second generation - and presumably third generation - mobile telephone apparatuses. Despite performing different tasks, the processors must asynchronously access common resources. These usually include external memory elements on a shared bus, on which the various devices in the system communicate. A method for the arbitration of said concurrent processes is required.
The various devices in the system comprise "master" devices and "slave" devices. The master devices include processors, such as RISC (Reduced Instruction Set Computer) and DSP (Digital Signal Processor) devices. Slave devices include various interfaces, such as UART (Universal Asynchronous Receiver/Transmitter) devices, display managers, keyboard managers, coprocessors, buzzers, etc.
In order to limit the number of components, reducing the costs of the final system as much as possible, the external memory elements required by the processors for operation are usually reduced to two: one FLASH memory and one RAM (Random Access Memory). Since both must be either read or written by the processors, in undetermined instants of time, arbitration capable of governing the connections on the basis of a priority management is required to prevent the risk of access conflicts.
This function is generally performed by the RISC processor, which manages the RTOS (Real Time Operative System), i.e. for managing tasks and accesses to external memories of all devices on the shared bus.
Conversely, the DSP manages the data processing operations, such as radio communication channel data, audio source samples, which may be compressed in the case of a mobile telephone system.
It is evident that communication between the RISC processor and the DSP is of primary importance and must occur in conditions of maximum security. Generally, communication is not direct but performed via a shared memory area in the RAM, which can be accessed by either processor according to a priority code. Furthermore, again for reasons of cost-effectiveness, a single FLASH memory is usually employed containing the programs of both processors, the so-called "Firmware", which is also accessed via the single shared bus according to the priority code.
In this context, a critical condition occurs when one of the two processors needs to access the memory resources, while connection has been established with the other processor. This is due to the fact that, by working both processors at high priority, the memories must be accessed in an alternating and exclusive way. Consequently, if one of the two is reading or writing data, the other must wait until the end of the operation. These operations may have also very different duration for the two processors, and therefore one of the two could be penalised. In fact, the RISC operating method is a succession of fast task assignments, which is priority with respect to other devices, while the DSP, once enabled to work at top priority, takes on a large amount of processing, which can considerably protract in time. During these operations, the DSP negates return of the control to the RISC, which consequently cannot access the external memories to extract instructions for the subsequent tasks. Consequently, the operating system is in fact blocked.
In order to prevent this problem, control is periodically reassigned to the
RISC, according to empirical rules of priority based on previous experience.
Particularly, different operating times are assigned a priori on the basis of statistical evaluations, not connected to the effective needs of the moment.
It is obvious that this type of solution causes high fragmentation of the tasks assigned to the DSP, which is periodically interrupted, in a way that is disconnected from the data transmission activity, creating process access redundancy of both the DSP and the RISC, consequently causing slowdowns. Another possible solution is obviously that of duplicating the FLASH and RAM memories, so to prevent the access conflicts described above. However, the adoption of additional memories would make the device more expensive.
Disclosure of the Invention
The method and the apparatus according to this invention prevent said shortcomings and solve the technical problem described above, permitting the DSP to fully perform the assigned task without precluding the possibility of the RISC to reassume control of the system when required, avoiding the memory resource access redundancy described above.
Particularly, this invention relates to a method and an apparatus for arbitration of concurrent processes in multiprocessor systems as described in the characterising preamble of claim 1.
Brief Description of Drawings
This invention will be better explained by the following detailed descriptions with reference to the accompanying figure as non-limiting example, where:
Fig. 1 is a block diagram of a multiprocessor system with shared memories,
Fig. 2 is a block diagram of the block indicated as IME in Fig. 1.
Best mode for Carrying out the Invention
According to the method of this invention, during system initialisation, the
RISC processor loads a set of instructions, forming the operating system, from the FLASH memory for managing assignment of tasks to the other system devices, and the information for arbitration of the concurrent processes, i.e. for assigning the various priorities for shared external memory access.
Particularly, before assigning priority to the DSP, the RISC establishes the number of transactions that the DSP can perform when accessing external memories before returning the control to the RISC. This number is regularly changed at each cycle, i.e. decreased to reach a predetermined value, which determines overriding and ending the task performed by the DSP.
During the subsequent working phase, on the basis of the instructions loaded during initialisation, the RISC can assign a new number of transactions to the DSP, which can be easily programmable a priori. This initial set of instructions can be periodically updated by the external management control software control.
The block diagram in Fig. 1 shows a typical architecture implementing the method according to this invention.
In the diagram, BD and BR indicate the buses devoted to the DSP processor, indicated with DS, and the RISC processor, indicated with RI. Both buses access the external memory elements F and R, a FLASH memory and a RAM memory, respectively, via an interface device IME.
Various peripherals SL1, ..., SLn are connected to the bus BR for performing the normal functions of an evolved multiprocessor system, such as UART devices, display interfaces, keyboard interfaces, buzzers, etc., and a local memory MR, for the management of temporary data.
Similarly, a local memory MD is connected to the bus BD. During normal operation, access requests to the external memories F and R can be advanced on both buses. In the event of simultaneous requests, only one bus is enabled by the RISC by assigning a priority made via a wire FP. If, the priority is assigned to the DSP, this engages a bus BE (via the interface IME), connected to the external memories F and R, and transfers the data on the bus.
For implementing the method of this invention, a programmable counter is arranged in the IME interface. The counter can be dynamically pre-set, via bus BR controlled by the RISC, to an optimal value for performing the task assigned by the DSP at that time. When the DSP assumes control of the bus BE, the value set on the counter is decreased at each external memory element access transaction, and when zero is reached, the system control is reassigned to the BR bus and, consequently, to the RISC.
This method is repeated for all the subsequent steps with an initial value set in the counter by the RISC, which may be different from the one above, in order to optimise the processing times connected to the DSP in view of the assigned task.
The IME interface is illustrated in greater detail in Fig. 2.
It comprises a combinatory logic LC, which is accessed by the buses BD, BR and BE, a finite state machine FSM, managing access priority, and a counter C, which can be dynamically pre-set via the BR bus.
When the finite state machine FSM (via a bus FL) acknowledges that the DSP has access to bus BE via LC, it decreases via the bus FC the set counter value
C by one unit for each transaction. When C reaches zero, even if the higher priority is assigned to the DSP, bus BE is overridden and assigned to the RISC, which resumes control of the operations. This action is implemented by means of the LC logic, which permits the mutually exclusive connection of either bus BD or bus BR, on the basis of the signal that the FSM generates on bus FL. The FSM permits these operations in LC in the due sequence, on the basis of controls arriving on either BD or BR.
The description herein is provided as a non-limiting example and obviously variations, and changes are possible within the scope of protection of this invention illustrated in the claims.

Claims

Claims
1. Method for the arbitration of concurrent processes in multiprocessor systems comprising a main processor (RI), a secondary processor (DS), shared external memories (F, R) and other devices (MD, MR, SL1, ..., SLn) in which, during initialisation of the system, the main processor (RI) loads a set of instructions, forming the operating system from an external memory (F) for managing the tasks assigned to other devices in the system, and the information required for arbitration of the concurrent processes, assigning the various priorities for accessing the shared external memories (F, R), characterised in that, before assigning the priority to the secondary processor (DS), the main processor (RI) establishes the number of external memory (R, F) access transactions which the secondary processor (DS) can perform before returning the control to the main processor (RI), the number of transactions can be regularly changed at each cycle to reach a pre-set value to determine overriding and ending the task performed by the secondary processor (DS).
Method according to claim 1, characterised in that at each cycle on the basis of the set of instructions loaded during initialisation, the main processor (RI) assigns the number of transactions that the secondary processor (DS) can perform.
3. Method according to claim 1, characterised in that the set of initial instructions, which contains the number of external memory (R, F) access transactions that the secondary processor (DS) can perform before returning the control to the main processor (RI), can be periodi- cally updated.
. Apparatus for implementing the method in any of the claims above, in which a first bus (BR) is dedicated to the main processor (RI) and a second bus (BD) is dedicated to the secondary processor (DS) and both said busses access said external memories (F, R) via an interface device (IME) and a third external bus (BE), for deciding which simultaneous requests can be advanced, characterised in that either the first or the second bus (BR, BD) is enabled by the main processor (RI) by assigning a priority via a wire (FP) and controlling said interface device (IME), where a programmable counter (C), which can be dynamically pre-set, via said first bus (BR) controlled by the main processor (RI), to an optimal value for performing the task assigned to the secondary processor (DS) in that moment, is arranged, said value being updated at each transaction of the secondary processor (DS) to reach the pre-set value when the system control is reassigned to the first bus (BR) and to the main processor (RI).
5. Apparatus according to claim 4, characterised in that said interface device (IME) comprises a combinatory logic (LC), which is accessed by said first, second and third bus (BR, BD, BE), a finite state machine (FSM), managing access priority, and said counter (C), which can be dynamically reset by said first bus; said finite state machine (FSM), when acknowledging - via a fourth bus (FL) - that the secondary processor (DS) has access to the third bus (BE), changes the value set on the counter (C) at each transaction to reach a prefixed value, at which time the third bus (BE) is enforcedly assigned to the main processor (RI) by means of the combinatory logic (LC).
6. Apparatus according to claim 4 or 5, characterised in that said combinatory logic (LC) permits mutually exclusive connection of either the first or the second bus (BR, BD) with the third external bus (BE) on the basis of the signal which the finite state machine (FSM) generates on the fourth bus (FL), on the basis of commands arriving on either the first or second bus (BR, BD).
PCT/EP2001/007193 2000-06-29 2001-06-25 Method and apparatus for arbitration of concurrent processes in multiprocessor systems WO2002001345A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT2000TO000643A IT1320466B1 (en) 2000-06-29 2000-06-29 PROCEDURE AND EQUIPMENT FOR THE ARBITRATION OF COMPETITIVE PROCESSES IN MULTIPROCESSOR SYSTEMS.
ITTO2000A000643 2000-06-29

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WO2002001345A2 true WO2002001345A2 (en) 2002-01-03
WO2002001345A3 WO2002001345A3 (en) 2003-03-06

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010140945A1 (en) 2009-06-04 2010-12-09 Telefonaktiebolaget L M Ericsson (Publ) Passive selt

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US4679166A (en) * 1983-01-17 1987-07-07 Tandy Corporation Co-processor combination
US5392436A (en) * 1989-11-03 1995-02-21 Compaq Computer Corporation Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration
US5598575A (en) * 1993-11-01 1997-01-28 Ericsson Inc. Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor's access to the program memory
US6078338A (en) * 1998-03-11 2000-06-20 Compaq Computer Corporation Accelerated graphics port programmable memory access arbiter

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US4679166A (en) * 1983-01-17 1987-07-07 Tandy Corporation Co-processor combination
US5392436A (en) * 1989-11-03 1995-02-21 Compaq Computer Corporation Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration
US5598575A (en) * 1993-11-01 1997-01-28 Ericsson Inc. Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor's access to the program memory
US6078338A (en) * 1998-03-11 2000-06-20 Compaq Computer Corporation Accelerated graphics port programmable memory access arbiter

Non-Patent Citations (1)

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Title
"STATE MACHINE IMPLEMENTATION OF SHARED RAM ARBITER" IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 31, no. 7, 1 December 1988 (1988-12-01), pages 83-85, XP000253951 ISSN: 0018-8689 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010140945A1 (en) 2009-06-04 2010-12-09 Telefonaktiebolaget L M Ericsson (Publ) Passive selt

Also Published As

Publication number Publication date
WO2002001345A3 (en) 2003-03-06
IT1320466B1 (en) 2003-11-26
ITTO20000643A1 (en) 2001-12-29
ITTO20000643A0 (en) 2000-06-29

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