WO2001099279A1 - Signal peak reduction circuit for non-constant envelope modulation signals - Google Patents
Signal peak reduction circuit for non-constant envelope modulation signals Download PDFInfo
- Publication number
- WO2001099279A1 WO2001099279A1 PCT/AU2001/000741 AU0100741W WO0199279A1 WO 2001099279 A1 WO2001099279 A1 WO 2001099279A1 AU 0100741 W AU0100741 W AU 0100741W WO 0199279 A1 WO0199279 A1 WO 0199279A1
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- signal
- peak reduction
- reduction circuit
- circuit according
- filter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2614—Peak power aspects
- H04L27/2623—Reduction thereof by clipping
- H04L27/2624—Reduction thereof by clipping by soft clipping
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0294—Variable filters; Programmable filters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70706—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation with means for reducing the peak-to-average power ratio
Definitions
- the present invention relates generally to circuits and methods for reducing the signal peaks in telecommunications signals, and in particular to circuits and methods for reducing the peak to average power ratio of non-constant envelope modulation signals.
- the present invention is suitable for use in applications involving multi-code Code Division Multiple Access (CDMA) signals, Orthogonal Frequency Division Multiplexing (OFDM) signals and critically sampled complex Gaussian signals, and it will be convenient to described the invention in relation to these exemplary applications. It will be appreciated, however, that the invention is not limited to use in these applications only.
- CDMA Code Division Multiple Access
- OFDM Orthogonal Frequency Division Multiplexing
- ACI Adjacent Channel Interference
- Figure 1 illustrates a portion 1 of the transmission path of a multi-code CDMA transceiver, in which a signal's in-phase and quadrature (I & Q) components are up- converted by an up-converter 2 or a number of upconversion stagesfor amplification by an amplifier 3, and subsequent transmission.
- a pulse-shaping interpolation filter 4 or other filtering is used to band limit the signal supplied to the up-converter 2.
- One effective method of preventing saturation of the amplifier 3 is to introduce a signal peak clipper before the amplifier 3.
- There are two possible positions in a transmitter for the clipper namely the placement of a clipper 5 before the filter 4 or the placement of a clipper 6 after the filter 4.
- a clipper after the filter prevents amplifier saturation, eliminating AM to PM distortion in the amplifier saturation region, but still generates ACI.
- the latter can be reduced by peak windowing, or eliminated all together by putting the clipper before the filter.
- the placement of the clipper 5 before the filter 4 can cause regrowth of the clipped peaks, which can again cause amplifier saturation.
- Harder clipping, or over-clipping can prevent peak re-growth but attenuates the signal more than necessary.
- one aspect of the present invention provides a signal peak reduction circuit, comprising: a band-limiting filter or filters for limiting the bandwidth of a data bearing signal, a predictive filter for predicting peaks in the data bearing signal at the output of the pulse-shaping filter, a clipping processor for generating a compensation signal in response to one or more signal peaks predicted by the predictive filter, and a signal combining device for applying the compensation signal to the data bearing signal prior to band limiting and amplification of the data bearing signal.
- the data bearing signal includes I and Q data symbols.
- the data symbols may be zero stuffed for interpolation.
- the signal peak reduction circuit may include a delay line for delaying application of the data bearing signal to the band limiting filter or filters.
- the delay line may include a plurality of delay elements and may form part of the predictive filter.
- the signal combining device may apply the compensation signal at or near the centre of the delay line.
- the compensation signal may include a correction vector.
- the signal combining device may act to apply the correction vector to a single data sample position.
- the correction vector may be applied at the sample position on the delay line activating the largest filter tap.
- the correction vector may include a plurality of vector components, the signal combining device acting to distribute the vector components to a plurality of data symbols or samples.
- the signal combining device may distribute the vector components to the data symbols activating the largest filter tap values.
- the compensation signal may include a plurality of gain adjustment signals for adjusting the gain of a plurality of data symbols in the predictive filter.
- the gain adjustment may be applied to the symbols activating the largest active sub- filter tap values.
- the clipping processor may compare the magnitude of the output of the predictive filter with a threshold level to detect peak values of the data bearing signal.
- the clipping processor may generate a compensation signal for application to the data bearing signal at a maximum peak value of the data bearing signal.
- the clipping processor may generate a compensation signal for application to the data bearing signal every time the amplitude of the data bearing signal exceeds the threshold level.
- a signal clipper may be used to limit the amplitude of the data bearing signal introduced to the signal peak reduction circuit.
- the set clipping levels of the signal clipper and the predictive filter may be independently adjustable with respect to the amplifier clipping level.
- Another aspect of the invention may provide signal peak reduction, circuitry including a plurality of signal peak reduction devices as described above, connected in series.
- Figure 1 which has been previously described, is a schematic diagram of a portion of a transmission path of a multi-code CDMA transceiver
- Figure 2 is a schematic diagram of a first embodiment of a signal peak reduction circuit according to the present invention.
- Figure 3 is a schematic diagram of a second embodiment of a signal peak reduction circuit according to the present invention.
- Figures 4 (a) and (b) are graphical representations of data symbols at various locations in the circuits of Figures 2 and 3;
- Figure 4 (c) shows graphical representation of an output correction vector generated by a clipping processor forming part of the signal peak reduction circuit of Figures 2 and 3;
- Figure 4 (d) shows the component parts of an amplitude sample and the output correction vector as processed by Figure 2 and Figure 3;
- Figure 5 is a graphical representation of vectors formed by the in-phase and quadrature components of data symbols within a data bearing signal processed by the circuit of Figure 2;
- Figure 6 is a graphical representation of vectors formed by the in-phase and quadrature components of data symbols within a data bearing signal processed by the circuit of Figure 7;
- Figure 7 is a schematic diagram of a third embodiment of a signal peak reduction circuit according to the present invention.
- Figure 8 is a graphical representations of vectors formed by the in-phase and quadrature components of data symbols within a data bearing signal processed by the circuit of Figure 9 and 12;
- Figure 9 is schematic diagram of a fourth embodiment of a signal peak reduction circuit according to the present invention.
- Figures 10 (a) and (b) are flow diagrams respectively of a peak detection algorithm and a level detection algorithm for implementation by any of the circuits of Figures 2, 3, 7, 9 and 12;
- Figure 11 is a graphical representation of a data bearing signal processed by any one of the circuits shown in Figures 2, 3, 7 and 9;
- Figure 12 is a schematic diagram of a fifth embodiment of a signal peak reduction circuit according to the present invention.
- Figure 13 is a schematic diagram of a sixth embodiment of a signal peak reduction circuit according to the present invention.
- the circuit 10 includes a zero bit stuffer 11, a predictive interpolation filter 12 and band-limiting filter 13, a delay line 14, a clipping processor 15 and a signal-summing device 16.
- Input I Q data symbols, d(r) are zero stuffed by the zero bit stuffer 11 to form a signal x(n) - as shown in Figure 4 (a) - and then fed to two successive identical or closely matched filters 12 and 13 for interpolation.
- the filter 12 is a predictive filter that models the response of the second filter 13 and optionally any subsequent filtering prior to the P/A to the data bearing signal from the zero bit stuffer 11.
- the predictive filter 12 is used for predicting peaks in the data bearing signal and providing an output signal to the clipping processor 15 for generating the compensation signal in response to the detected peaks, in this case a correction vector, v(n).
- the correction vector is subtracted from the signal, x (appropriately delayed by the delay line 14), before passing through the second interpolation filter 13 and the up-conversion circuitry, as shown in Figure 1.
- the second filter 13 is represented in this Figure by a single element, the second filter 13 may encompass all filtering elements between the predictive filter 12 and the amplifier of a given transceiver.
- the predictive filter 12 is realised as a Finite Impulse Response (FIR) filter.
- the delay line 14 is incorporated into the delay line component of the prediction filter 12 and includes multiple delay elements, such as those referenced 20 and 21. Adjacent delay elements in the delay line separate filter taps, such as those referenced 22 to 25.
- the point at which the compensation signal is applied to the data bearing signal is preferably towards or at the centre of the delay line 12 in order to compensate for the group delay of the filter.
- the compensation vector is applied to the sample activating the largest filter tap value.
- the signal -summing device 16 is located, in this example, in order to apply the correction vector at the output of the clipping processor 15 to the centre of the prediction filter delay line structure.
- the input to the second filter can also be taken from the delay line directly after the signal summing device 16 (just before the delay element 21) to reduce signal latency.
- the clipping processor 15 compares the amplitude of the output of the predictive filter 12 with a threshold level, referred to as a Set Clipping Level (SCL), to detect the peaks of that output.
- a threshold level referred to as a Set Clipping Level (SCL)
- SCL Set Clipping Level
- the correction vector v(ri) is so calculated to limit the magnitude of the output signal of the predictive filter 12 to the SCL value.
- a vector representation of the calculation of y(n) is shown in Figure 4 (d).
- the correction required at the output of the filter 12 to stop clipping is ( ⁇ ) , and is equal to the effect of v( ) on the filter output at time n .
- the clipping processor calculates the required value of SCL as follows:
- the shortest correction vector (n) is in-phase with y( ⁇ ) and simplifies (1 ) to
- the correction vector v(n) is the error introduced to the data bearing signal. Filtering by the predictive filter 12 distributes this error to other signal samples such that each of the received samples in the range of the filter impulse response can receive part of this error.
- the smeared error to a given output sample at time instant m can be expressed as:
- the asynchronous position of the correction vector in the above-described method requires a brute-force structure for the interpolation that is zero sample insertion 11 followed by filtering 12 and 13.
- the complexity can be significantly reduced if polyphase structures are used.
- the correction vector can be distributed among a number, N, of the M data symbols forming the filter output, y(n), as can be seen in Figures 5 (a) and (b).
- the distribution of the correction vector can be optimised by minimisation of the error defined as:
- Equation (13) consists of N equations of the form
- Equation (18) implies that increasing the number of contributing symbols decreases the error. Moreover, the equation suggests that the symbols with the largest tap magnitudes should be chosen for applying the distributed correction vector. These symbols are normally located near or at the centre of the filter's impulse response. The average error can be found by averaging (17) for different positions, p, of the correction vector with regard to its nearest data symbols.
- the distributed-vector-subtraction method always has a higher error than vector- subtraction method, but the error tends to reduce with an increasing number of symbols, N, over which the correction vector is distributed.
- This circuit 30 applies the two correction vector components to those data symbols in the data bearing signal having the highest tap values, that is, those data symbols closest to the peak value, y(n), at time n. This is enabled by the use of two complex signal summing devices 31 and 32 at the centre of the delay line 33 of the predictive filter 34.
- the filters 34 and 13 are realised by a poly-phase structure.
- the filter 34 includes multiple sub-filters, such as those referenced 36, 37 and 38 in Figure 7.
- a rotary switch 35 feeds the output samples at each clock pulse from each sub-filter 36 to 38 to the clipping processor 15, and compares these output samples with the clipping level SCL.
- the appropriate vectors, vo and vi are then calculated by the clipping processor 15 and applied to the complex adders 31 and 32.
- only one correction vector vn would be applied to the symbol position activating the highest tap value, h, from the current sub-filter.
- the gain of a group of complex data symbols is changed to reduce the peak to average ratio, as seen in Figure 8.
- the partial contribution, yp(n), of N selected symbols on the filter output, y(n) is
- N yp(n) ⁇ h_ ⁇ x(n + p + i ⁇ ) tf (19) Applying a gain g on yp(n), can force the output to the SCL (set clipping level):
- Equation (22) can be rearranged as
- the g can be complex. Restricting g to a real positive number can simplify the implementation because only real gain is needed for 42 and 43. In which case
- Precautions must be taken to prevent gain adjustment when A is very small, causing round off errors.
- FIG. 9 A block diagram of a signal peak reduction circuit 40 implementing this gain- adjustment method, similar to the corresponding the previously described circuit implementing the distributed-vector-subtraction method, is shown in Figure 9.
- the circuit uses two symbol correction.
- the delay line 41 in this Figure includes variable gain amplifiers 42 and 43 for adjusting the signal gain at the centre.
- the feed to the subfilters 13 can be taken immediately after the last gain adjustment stage.
- the square error introduced by the gain-adjustment method can be defined as
- Peak detection and compensation may be performed by use of an iterative algorithm to search and find the filter output for peaks larger than the clipping level. Two different compensation strategies may be adopted.
- peak detection algorithm the compensation is performed whenever there is a peak in y(n) which exceeds the SCL (sample n in Figure 4 (b)).
- level detection algorithm LDA
- the compensation is performed every time (sample) that the signal amplitude exceeds SCL whether this is at a peak or not (samples n-1, n, n+1, n+2 in Figure 4 (b)).
- the compensation methods previously described are intended to eliminate overshoot of the set clipping level (SCL) at a single data sample point only.
- SCL set clipping level
- Such filtering causes the introduced compensation signals (correction vectors or gain adjustments) to effect other parts of the output waveform, which can cause amplitude overshoot at sample times where there were none before.
- This effect is particularly noticeable when there are a number of successive peaks, where compensation of one peak may re-grow the previously compensated peaks.
- This phenomenon is common in nearly all the clipping compensation methods and can lead to amplifier saturation.
- One method to prevent this is to use a set clipping level (SCL) lower than the amplifier clipping level (ACL), the level at which the amplifier saturates, as illustrated in Figure 11.
- This lower set clipping level (SCL) reduces the chance of re-grown peaks saturating the amplifier.
- the ACL defines the peak power of the transmitted signal from which the peak to average power ratio (PAPR) of the transmitted signal can be
- a method of preventing peaks overshooting the set clipping level (SCL) is to add a conventional clipper 51 before any of the previously described predictive filters, here referenced 52.
- the additional conventional clipping stage 51 shown in Figure 13 acts as a data preclipper and reduces peak regrowth.
- FIG 12 shows a cascaded version of a signal peak reduction circuit, referred to herein as a clip-filter-clip-filter (CFCF) circuit.
- the CFCF circuit 50 has one more clipping stage than the clipping circuits shown in Figures 2, 3, 7 and 9.
- the second stage clips the re-grown peaks and the last filter attenuates the spectral leakage into adjacent channels that this might cause.
- MSE mean squared error
- the three other implementations adjust the data points themselves, either by adding a correcting vector (distributed-vector-subtraction implementation) or by multiplying them by a gain factor, g, that is between 0 and 1 (gain-adjustment implementation) or by limiting their amplitude (conventional clipping). Preclipping of the data bearing signal has been found to further improve to all implementations. All implementations do not requite a block format for processing, and so are suitable for systems that require continuous transmission, such as CDMA.
- the present invention can be used with any non-constant envelope modulations, such as QAM, PSK, multicarrier signals, OFDM and CDMA.
- the input signal is a multi-code CDMA signal (consisting of a sum of different (pseudo) random codes.
- the input signal is critically sampled, and therefore needs to be bandlimited (through a pulse-shaping filter) and up-converted prior to transmission. Interpolation is performed in the digital domain, which reduces the requirements on the reconstruction filter following digital to analog conversion.
- the impulse response of the overall filter is therefore dominated by the digital interpolation filter, which can be implemented in a poly-phase structure.
- the prediction filter should be designed to model the effect of the actual filtering (including analog, IF and RF filters) prior to the PA.
- An acceptable reduction in complexity is to use only the largest contributing taps in the prediction filter, since these are the dominating contributors to peak regrowth.
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US10/311,872 US7376197B2 (en) | 2000-06-20 | 2001-06-20 | Signal peak reduction circuit for non-constant envelope modulation signals |
AU2001265708A AU2001265708A1 (en) | 2000-06-20 | 2001-06-20 | Signal peak reduction circuit for non-constant envelope modulation signals |
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AUPQ8200 | 2000-06-20 | ||
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10302161A1 (en) * | 2003-01-21 | 2004-08-05 | Infineon Technologies Ag | Crest factor method for altering the crest factor in a time-discrete signal formed by a signal vector's time-consecutive signal value calculates a correcting vector to add to the signal vector |
EP1978696A3 (en) * | 2007-04-05 | 2010-06-23 | Microelectronics Technology Inc. | Crest factor reduction |
Citations (3)
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US4495643A (en) * | 1983-03-31 | 1985-01-22 | Orban Associates, Inc. | Audio peak limiter using Hilbert transforms |
US5493587A (en) * | 1992-07-27 | 1996-02-20 | Alcatel Italia S.P.A. | Method and circuits for reducing the peak power of the filtered signal transmitted in a digital link |
US5608760A (en) * | 1994-07-28 | 1997-03-04 | Alcatel Italia Spa | Method and circuits for the transmission and reception of numeric signals, in which the peak power of the filtered signal transmitted is reduced, compatible with conventional coding techniques |
-
2001
- 2001-06-20 WO PCT/AU2001/000741 patent/WO2001099279A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4495643A (en) * | 1983-03-31 | 1985-01-22 | Orban Associates, Inc. | Audio peak limiter using Hilbert transforms |
US5493587A (en) * | 1992-07-27 | 1996-02-20 | Alcatel Italia S.P.A. | Method and circuits for reducing the peak power of the filtered signal transmitted in a digital link |
US5608760A (en) * | 1994-07-28 | 1997-03-04 | Alcatel Italia Spa | Method and circuits for the transmission and reception of numeric signals, in which the peak power of the filtered signal transmitted is reduced, compatible with conventional coding techniques |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10302161A1 (en) * | 2003-01-21 | 2004-08-05 | Infineon Technologies Ag | Crest factor method for altering the crest factor in a time-discrete signal formed by a signal vector's time-consecutive signal value calculates a correcting vector to add to the signal vector |
EP1978696A3 (en) * | 2007-04-05 | 2010-06-23 | Microelectronics Technology Inc. | Crest factor reduction |
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