WO2001095561A2 - Dispositif d'essai electronique portatif pour reseaux de telecommunications - Google Patents

Dispositif d'essai electronique portatif pour reseaux de telecommunications Download PDF

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Publication number
WO2001095561A2
WO2001095561A2 PCT/CA2001/000615 CA0100615W WO0195561A2 WO 2001095561 A2 WO2001095561 A2 WO 2001095561A2 CA 0100615 W CA0100615 W CA 0100615W WO 0195561 A2 WO0195561 A2 WO 0195561A2
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WO
WIPO (PCT)
Prior art keywords
test
packet
test set
accessory
ethernet
Prior art date
Application number
PCT/CA2001/000615
Other languages
English (en)
Other versions
WO2001095561A3 (fr
Inventor
Sami Yazdi
Nando Di Giambattista
Patrick Ostiguy
Giovanni Forte
Original Assignee
Exfo Protocol Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA002310887A external-priority patent/CA2310887A1/fr
Application filed by Exfo Protocol Inc. filed Critical Exfo Protocol Inc.
Priority to AU2001258081A priority Critical patent/AU2001258081A1/en
Priority to EP01931246A priority patent/EP1290826A2/fr
Publication of WO2001095561A2 publication Critical patent/WO2001095561A2/fr
Publication of WO2001095561A3 publication Critical patent/WO2001095561A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/22—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks comprising specially adapted graphical user interfaces [GUI]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
    • H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
    • H04M3/30—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop
    • H04M3/308—Craftsperson test terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/0016—Arrangements providing connection between exchanges
    • H04Q3/0062—Provisions for network management
    • H04Q3/0087—Network testing or monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M2201/00—Electronic components, circuits, software, systems or apparatus used in telephone systems
    • H04M2201/42—Graphical user interfaces
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/2209—Arrangements for supervision, monitoring or testing for lines also used for data transmission

Definitions

  • the present invention relates to test instrumentation in general and more specifically to instrumentation for testing Digital Circuit (Time Division Multiplex: TDM) and Packet based communication networks.
  • TDM Time Division Multiplex
  • TDM Time Division Multiplex
  • Telecommunication carriers which used to install only TDM based infrastructures, are now building hybrid TDM/Packet based networks and consequently, their field installation technicians need to test both technologies on the same networking equipment in the same physical location.
  • TDM test instruments and packet communication test instruments typically consist of two separate physical and logical entities, which thus reduces the portability versatility and usability of such devices when these two technologies converge.
  • the convergence of TDM based and packet based technologies in the fibre optics communication industry requires an instrument that enables testing both of those two technologies simultaneously, as well as the interaction and integration of both, e.g. testing packet over SONET (POS) communication.
  • POS SONET
  • test instruments capable of testing full-duplex
  • 10/100/1 OOOBaseTX packet based networks at its full-line-rate (1Gbps) typically require the connection of a separate personal computer (PC), monitor, keyboard and mouse to allow configuring it and operating the user interface, thus reducing the portability and usability of the device.
  • PC personal computer
  • TDM signal hierarchies of digital circuit based communications can become very complicated if the testing configurations have to be set up using a complex user interface. Since portable test instruments include a broad range of TDM test functions, the former dials, buttons and function keys of the prior art test devices have now become ineffective and result in an unfriendly and cumbersome user interface.
  • GUI Graphical User Interfaces
  • U.S. Pat. No. 5,808,920 to Zwan et al. discloses a GUI interface that can be used in conjunction with a TDM communication test device.
  • the interface uses a graphical representation of the specific physical test device being used, which requires knowledge and understanding of the internal architecture of that specific physical test device (internal switch matrix, various processors and modules, etc.)
  • U.S. Pat. No. 5,619,489 to Chang et al. discloses a portable TDM communication test device that incorporates a graphical display, a user input device, as well as a graphical method for changing the test configuration of the device.
  • the user input device consists of pushbuttons and function keys as opposed to a touchscreen.
  • IGbps full line rate
  • POS packet over SONET
  • PRBS Pseudo-Random Bit Sequence
  • a portable, field oriented test set for testing TDM and packet based communication networks, comprising: a mother module, for managing the test set; a TDM module, operatively connected to the mother module and to a plurality of physical connectors, said TDM module being adapted to perform test sequences on digital circuit networks; a packet communication test module, operatively connected to the mother module, to the TDM module and to at least one 10/100/1 OOOBaseTX connector, said packet communication test module being adapted to perform test sequences on packet based communications networks; a display area for displaying information relative to the tests under way and to provide information with respect to the test set; input devices, for inputting information into said test set; and a GUI for interfacing between said test set and a user, whereby said test set is adapted to test TDM communication networks and packet based communication networks.
  • a graphical user interface for a test set being adapted to perform testing on a plurality of communications channels
  • said GUI comprising: a display comprising a signal area, a circuit area and a test area; said signal area displaying icons related to the physical communications channels; said circuit area displaying icons related to standard multiplexing steps associated with said signal area icons; and said test area displaying icons related to the test to be executed, wherein when said test set is physically connected to a physical communication channel, an icon in the signal area representing said physical communication channel is highlighted, and icons in the circuit area and the test area related to the icon representing the physical communication channel, and representing valid circuits or tests associated with the physical communication channel are highlighted, so that a user can only select a valid circuit or test icon.
  • Another aspect of the invention is concerned with a loopback accessory for testing a full duplex Ethernet WAN link with a test set, said accessory including: an interface for receiving Ethernet packets from a communications network, an Ethernet MAC Controller for delineating destination and source MAC addresses of a packet; an inverter for inverting the destination and source MAC addresses and for creating another packet with the inverted destination and source addresses; said accessory transmitting the other packet over said communications network.
  • the invention also provides a method for testing full duplex Ethernet WAN links, comprising: preparing a packet including destination and source MAC addresses with a test set, and time-stamping said packet with said test set; sending said packet over a communications network to a loopback accessory; receiving said packet with said loopback accessory; inverting said source and destination MAC addresses with said loopback accessory and accordingly preparing another packet; sending said other packet from said loopback accessory to said test set over said communications network; receiving said other packet with said test set; and analysing said packet with said test set to extract relevant information.
  • the system for testing full duplex 10/100/1 OOOBaseTX communications links comprises: a test set for preparing and sending over the communications link a packet including destination and source MAC addresses, and for time-stamping said packet; and a loopback accessory for receiving the packet, inverting the destination and source MAC addresses, preparing another packet with the destination and source MAC addresses so inverted and transmitting the other packet over the communications link to the test set.
  • Figure 1 is a schematic representation of the front view of the test set according to the present invention
  • Figure 2 is a schematic representation of the rear view of the test set of Fig.
  • Figure 3 is a schematic representation of a loopback accessory for use with the test set of the present invention
  • Figures 4 to 13 are illustrations of the graphical user interface according to a preferred embodiment of the present invention
  • Figure 14 is a schematic representation of a communication through Ethernet link under test
  • Figure 15 is a schematic representation of a method of testing a network using the loopback accessory of Fig. 3;
  • Figure 16 is a schematic representation of the architecture of the loopback accessory
  • Figure 17 is a block diagram of the architecture of the test set;
  • Figure 18 is a block diagram of the TDM communication module;
  • Figure 19 is a block diagram of the mother module
  • Figure 20 is a block diagram of the packet communication module.
  • Figure 21 is a flow chart of the method for performing a BER test on Ethernet according to the present invention.
  • the present invention concerns a portable, field-oriented test gear which permits validation of both digital circuit (TDM) and packet based communications.
  • the invention broadly stated, comprises a configuration method and graphical user interface for configuring DS1 , DS3, SONET and packet communication based tests, as well as a method and system to remotely validate full-duplex 10/100/1 OOOBaseTX Wide Area Network (WAN) communication at full line rate (IGbps) using a single test gear and a low cost accessory included with the test gear.
  • WAN Wide Area Network
  • the test set 10 preferably includes LEDs 11 , an LCD graphical display with a touchscreen overlay 13, arrow keys 15, an enter key 14, a help key 16, a pointing device 17, a right mouse button 19, a left mouse button 21 , rubberized protective endcaps 23, a connector field shown in Fig. 2.
  • an external loopback accessory 25 is preferably provided with the test set 10, as will be hereinafter detailed.
  • LEDs 11 display the summary conditions of the test set (Alarm, History,
  • LCD display 13 displays the test configuration, test results, detailed alarm conditions and acts as an input device through the use of an overlaid touchscreen.
  • Arrow keys 15 allow for movement of the text cursor within text fields
  • the enter key 14 is used to confirm the entry of text information in text fields.
  • the pointing device 17 may be used as an alternative to the touchscreen to control a graphical pointer for inputting configuration, the right mouse button 19 being used to select an object pointed by the pointing device, and the left mouse button
  • the connector panel located at the rear of the test set 10 includes the several connectors used to connect the test set with external communication media, as is well known in the art
  • the test set weighs approximately 10 pounds, which is appropriate for hand-held use.
  • the external loopback accessory 25 is used to assist the user in executing a full-duplex bi-directional 10/100/1 OOOBaseTX WAN link test, requiring only a single test set, using the method described hereinafter.
  • FIG 17 shows a high level block diagram of the internal architecture of the test set 10 according to a preferred embodiment of the present invention.
  • the test set 10 is comprised of three main modules: the mother module 101 , the TDM communication test module 103 and the packet communication test Module 105.
  • the mother module 101 shown in more detail in Fig. 19, is responsible for the hardware management of the graphical user interface (GUI), the memory and data stocking capabilities, user input devices, as well as general "housekeeping" functions such as internal temperature control of the test device, power regulation and distribution and battery management and charging.
  • GUI graphical user interface
  • This module 101 also hosts the main controller unit and is connected to the TDM communication test module 103 and packet communication test module 105 in order to control them.
  • the TDM communication test module 103 provides the ability to perform various test sequences on digital circuit (TDM) networks, namely, providing functions for DS1 , DS3, and SONET digital circuit testing.
  • TDM digital circuit
  • the packet communication test module 105 provides the ability to perform various test sequences on packet based communication networks, namely, providing functions for 10/100/1 OOOBaseTX and Packet Over SONET (POS) based communications.
  • the TDM communication test module 103 can be connected to the external
  • TDM communication media via the various TDM communication connectors, namely the DS1 110, DS3 112, STS-1 114, and OC-N/Nc 116 connectors.
  • the packet communication test module 105 can be connected to the external packet communication media via the two (2) 10/100/1 OOOBaseTX connectors 118 and 120.
  • the packet communication test module 105 is also connected to the TDM communication test module 103.
  • TDM/Packet based networks or "multi-service” Networks
  • POS packet over SONET
  • the present invention advantageously includes a link between the TDM communication test module and the packet communication test module.
  • This link provides the test set 10 of the present invention with the unique ability to perform testing of packet communications embedded inside POS in an all inclusive (test device, computer and user interface), portable, field oriented test platform.
  • the aforementioned link between the TDM and Packet Communication test module also permits the user to direct packet communication coming from within a TDM signal and drop it out of the test equipment on the Ethernet interfaces.
  • This feature for an all inclusive instrument permits the user, for instance, to validate the SONET mapping functions of an external network element such as a POS multiplexer. Accordingly, the packet communication test module must first generate a packet stream. The packet stream is then sent to the TDM communication test module, which then maps these packets within a SONET STS-Nc signal. The mapped packets are sent out of the test device to the external network element.
  • the external network element de-maps the packet stream from the SONET STS-Nc signal and returns it in its native format to the packet communication test module via one of the 10/100/1 OOOBaseTX interfaces.
  • This test configuration allows the user to measure the latency added to the packet stream by the POS multiplexer.
  • the mother module 101 is responsible for the hardware management of the GUI, the memory and data stocking capabilities, user input devices as well as general "housekeeping" functions such as internal temperature control of the test device, power regulation and distribution and battery management and charging, as well as other inherent tasks.
  • This module also hosts the main controller unit and connects it to the TDM communication test module 103 and packet communication test module 105.
  • the mother module 101 comprises:
  • SBC single-board-computer
  • GUI Graphical User Interface
  • LCD liquid crystal display
  • portable-computer-grade hard disk drive connected to the SBC to keep the Operating System, the GUI software and to store the information gathered during the tests;
  • - a Motorola 860 micro-controller used to control the front panel LEDs of the unit, manage internal temperature of the test device via sensors and fans, manage power supply distribution and battery charging and control the TDM and packet communication test modules 103 and 105; - LEDs to inform the user of alarm conditions during the test;
  • the TDM communication test module 103 is shown in Fig. 18.
  • the TDM communication test module allows the user to execute test routines on TDM communication protocols such as DS1 , DS3, and SONET, as well as demultiplexing functions to allow executing test routines on TDM signals when they are a sub-rate of a higher frequency TDM signal, for example, running a test on a DS1 which was incorporated in a DS3 which was incorporated in an STS-1 which was part of an OC-3 signal.
  • the TDM communication test module 103 in a preferred embodiment of the invention, comprises:
  • DS1 line interface that allows conversion of DS1 signal levels coming from a digital network communication transmission line to electrical signal levels suitable for board level processing and vice-versa, the "DS1 line interface” being connected to a "DS1 Framer";
  • DS3 line interface that allows conversion of DS3 signal levels coming from a digital network communication transmission line to electrical signal levels suitable for board level processing and vice-versa, the "DS3 line interface” being connected to a "DS3 Framer";
  • a "DS1 Pattern Generator/Analyzer” used to generate and analyze pseudo-random bit sequences which are used to stress-test DS1 digital communication lines, the "DS1 Pattern Generator/Analyzer” being connected to the "DS1 Framer”; - a "DS1 Framer” used to add the DS1 framing protocol to the raw bit sequence coming from the "DS1 Pattern Generator/Analyzer” and send it to the "DS1 Line Interface", or to remove the DS1 framing protocol from the DS1 signal coming from the "DS1 Line Interface” and send the raw bit sequence to the "DS1 Pattern Generator/Analyzer".
  • the "DS1 Framer” is also connected to the "DS1 to STS-1 Mapper” and to the "DS1 to DS3 Multiplexer” for the same purpose as with the "DS1 Line Interface”;
  • DS1 to DS3 Multiplexer used to insert/extract a single DS1 in/out of a higher frequency DS3 signal.
  • the "DS1 to DS3 Multiplexer” is also connected to the "DS3 Framer";
  • the "DS3 Framer” is also connected to the "DS3 to STS-1 Mapper” and to the "DS1 to DS3 Multiplexer” for the same purpose as with the "DS3 Line Interface”;
  • DS3 Pattern Generator/Analyzer used to generate and analyze pseudo-random bit sequences which are used to stress-test DS3 digital communication lines, the "DS3 Pattern Generator/Analyzer” being connected to the "DS3 Framer"; - a "DS1 to STS-1 Mapper” is used to map/de-map a DS1 signal to/from an
  • STS-1 SONET signal The "DS1 to STS-1 Mapper” is also connected to the "STS- 1 line Interface", to the "STS-1 Overhead & Pattern Processor” and to the "STS-1 to STS-N Multiplexer”;
  • an "STS-1 Overhead & Pattern Processor” used to generate/analyze SONET overhead and pseudo-random bit sequences to/from a SONET STS-1 signal.
  • the "STS-1 Overhead & Pattern Processor” is also connected to the "STS- 1 Line Interface” for analyzing an STS-1 signal coming directly from an STS-1 digital communication line, to the "DS1 to STS-1 Mapper” for analyzing an STS-1 signal which has embedded therein DS1 signals, to the "DS3 to STS-1 Mapper” for analyzing an STS-1 signal which has an embedded DS3 signal, and to the "STS-1 to STS-N Multiplexer" for analyzing an STS-1 signal which was embedded in an STS-N signal;
  • a "DS3 to STS-1 Mapper” is used to map/demap a DS3 signal to/from an STS-1 SONET signal.
  • the "DS3 to STS-1 Mapper” is also connected to the "STS- 1 line Interface", to the "STS-1 Overhead & Pattern Processor” and to the "STS-1 to STS-N Multiplexer”;
  • STS-1 line interface that allows conversion of STS-1 signal levels coming from a digital network communication transmission line to electrical signal levels suitable for board level processing and vice-versa
  • STS-1 to STS-N Multiplexer used to insert/extract a single STS-1 in/out of a higher frequency STS-N signal.
  • the "STS-1 to STS-N Multiplexer” is also connected to the "Selector Circuitry";
  • an "STS-Nc Overhead & Pattern Processor” used to generate/analyze SONET overhead and pseudo-random bit sequences to/from a SONET STS-Nc signal.
  • the "STS-Nc Overhead & Pattern Processor” can be connected to the "OC-N/Nc Line Interface” via the "Selector Circuitry";
  • This component is also connected to the "Selector Circuitry" in order to send the STS-Nc signal to the "OC-N/Nc Line Interface".
  • the packet communication test module is shown in Figure 20 and allows the user to execute test routines on packet communication protocols such as Ethernet and PoS.
  • the packet communication test module comprises: - a "Packet Communication Test Pattern Generator/Analyzer” used to generate and analyze packet communication test patterns.
  • This component is adapted to generate and capture packets at a rate of up to 1 Gigabit per second, thus allowing stressing Ethernet communications at their maximum capacity.
  • This component also allows tagging and verification of packets to verify their source address for latency, burstability, packet loss and throughput measurements.
  • This component is connected to the "Ethernet MAC Controller", to the "DRAM”, to the "CAM”, to the Motorola 860 microprocessor on the mother module 101 , and to the TDM communication test module 103; - an "Ethernet MAC Controller” receiving the packets coming from the
  • Figs. 14 and 15 show block diagrams of two preferred embodiments used to test a 10/100/1 OOOBaseTX link. It is an advantageous aspect of the invention to provide an all inclusive (hardware device, computer and user interface), portable test platform capable of testing 10/100/1 OOOBaseTX communication at full line rate (I Gbps) for all packet sizes and capable of remote communication to a second test device via the actual Ethernet link under test.
  • I Gbps full line rate
  • test sets are mandatory when the Ethernet media under test is of half duplex nature and if the Ethernet link spans over two different sites. However, when testing full duplex, or when the Ethernet link does not span over two different sites, it will be seen that only one test set is required.
  • Communicating through the Ethernet link under test permits a test set to coordinate a test sequence with the remote counterpart, which is not possible with the prior art devices designed for lab applications.
  • the method used is simply to engage communication between the two test devices only before the actual test starts (to communicate the parameters of the test to be done) and once the tests and measurements are actually finished (to communicate the results of the test).
  • an external loopback accessory 25 is used to assist the user in executing a full-duplex bi-directional 10/100/1 OOOBaseTX WAN link test using only a single test set as per the method described below.
  • Fig. 15 shows a block diagram of the setup used to test a
  • This aspect of the present invention results in significant savings to those engaged in turn-up and troubleshooting of such networks, since the cost of such an accessory is far less than the cost of a second test set.
  • the method for performing such a test is, according to a preferred embodiment of the present invention as follows.
  • the packets are first time- stamped inside the test set 10 and sent from the test set (at the right of Fig. 15) through the network under test 201. Once the packets have travelled through the network under test, they are received by the loopback accessory (at the left of Fig. 15).
  • the purpose of the accessory is to modify every packet received by swapping their source MAC addresses and their destination MAC addresses, and then send them back through the network under test towards the test set.
  • the test set receives the original packets with the modified addresses and compares the original time-stamp to the test set's current time to derive the round-trip latency calculation. Even more advantageously, to allow a more accurate measurement, the test set also subtracts a fixed constant value associated with the latency added by the loopback accessory 25 circuitry itself.
  • the same accessory 25 and connection method can also be used when measuring throughput, burstability and amount of packet loss as part of RFC 1944 and RFC 1242 Ethernet standards. It should be noted that the use of this novel loopback accessory method for measuring those standards based parameters also falls within the scope of the present invention.
  • FIG. 16 shows a block diagram of the architecture of the loopback accessory 25, which comprises:
  • an "Ethernet MAC Controller” used to delineate the destination and source MAC addresses of the Ethernet packets received from the "10/100/1 OOOBaseTX Line Interface” and to transfer this delineation information as well as the Ethernet packets themselves to the "MAC Address Inverter and Loopback”;
  • a "MAC Address Inverter and Loopback” component used to invert the destination and source MAC addresses of the received Ethernet packets and send them back to the "Ethernet MAC Controller”;
  • a further aspect of the present invention consists in a method and system for testing an Ethernet WAN link (also called Transparent LAN Service: TLS) by using a Pseudo-Random Bit Sequence (PRBS) pattern in order to count bit errors and derive a Bit Error Rate (BER) measurement.
  • PRBS test patterns and Bit Error Rate measurements have been used for testing the integrity of TDM Digital Circuits such as DS1 or DS3 for example, but, it has never been used for testing the integrity of an Ethernet based packet communication channel such as a TLS.
  • Prior art Ethernet testing devices mostly adapted for laboratory usage, traditionally use parameters such as Packet Loss Ratio. This parameter which was intended and designed to evaluate the performance of devices such as Ethernet Switches, Bridges or Routers is not best suited for the certification of TLS links when being put into service.
  • a tariff is levied on TLS links based on specific Service Level Agreements which include the guarantee of the perfect integrity and transparency of the link being leased.
  • the frame loss parameter given by prior art devices will provide only a coarse verification of this integrity by counting lost packets. A single bit error in a transmitted packet could potentially not affect this specific parameter. Since Ethernet, as a Layer 2 medium, does not command the retransmission of data corrupted during transfer, it defers this task to higher layer protocol which are the applications being run by the customers which thus reduces the usable throughput to the customer in the event of data corruption.
  • Ethernet also provides an intrinsic coarse indication of the integrity of the packets being delivered by the use of a CRC-32 Frame Check Sequence, this indication has an accuracy of the order of One Packet (i.e. it can determine if a packet was corrupted or not but it cannot quantify this corruption).
  • Fig. 21 The method according to a preferred embodiment of the invention is illustrated in Fig. 21.
  • the "Packet Communication Test Pattern Generator/Analyzer” Generates a PRBS test pattern and contiguously fills the Data portion of a flow of Ethernet Packets with the generated bit stream.
  • the Ethernet packets are then passed on to the "Ethernet MAC Controller".
  • the "Ethernet MAC Controller” executes CSMA/CD verification (if Half Duplex) and sends the packets to one of the two "10/100/1 OOOBaseTX Line Interfaces”.
  • a stream of Ethernet Packets is thus transmitted as the PRBS pattern is being generated (both operations happen simultaneously in real time).
  • the Ethernet Packets are then sent across the Ethernet link under test and recuperated at the other end by a second test set.
  • one of the two "10/100/1 OOOBaseTX Line Interfaces” passes the received packet to the "Ethernet MAC Controller".
  • This one verifies the destination MAC address.
  • CRC-32 FCS has been disabled to bypass this verification and allow the packets pass through directly and untouched to the "Packet Communication Test Pattern Generator/Analyzer”.
  • This one verifies the source MAC address and obtains a resulting received PRBS pattern and synchronizes itself on it.
  • This pattern being a known sequence, allows for a precise count of bit errors and accurate computation of a Bit Error Rate by the Motorola 860 microprocessor at the receiving end.
  • both directions would be tested simultaneously, i.e. both test sets would simultaneously act as a receiving end and a transmitting end.
  • a loop- back accessory (as described above) can be used in place of a second test set. The accessory then sends the packets back to the originating test set and this one then acts also as the receiving end (similarly to the loopback method described above).
  • a final aspect of the present invention is a GUI for more easily performing the tests administered by the test set 10 of the present invention, which will be described in reference to Figures 4 to 13.
  • the GUI display comprises three major sections: a signal field 50, a circuit field 70 and a test field 90.
  • the signal field 50 includes six (6) icons representing the various communication signals which can be connected to the test device 10.
  • the circuit field 70 includes four icons representing the various multiplexing steps involved in the standard TDM hierarchy.
  • the test field 90 includes five (5) icons representing tributary traffic termination points as per the standard TDM multiplexing hierarchy, as well as a packet termination point.
  • An important aspect of the present invention is the fact that its graphical user interface is based on the standard TDM multiplexing hierarchy, as opposed to prior art representations which are based on the internal architecture of the test device.
  • the present GUI will be better understood with the following example, which will be for demultiplexing a DS3 signal and testing an embedded DS1 tributary.
  • the user physically connects a DS3 signal to the test set. Therefore, intuitively, as a first step, the user touches (or clicks) on the DS3 "signal" icon 51. Instantaneously, the selected icon becomes highlighted and the valid options for the next choice are highlighted to the user in a different color (see figure 5).
  • An important aspect of the present invention is the fact that the Graphical User Interface guides the user between steps by highlighting the next valid choices for the user, and ONLY those steps. Invalid steps or choices will not be validated by the test set 10 of the present invention, which reduces errors in testing, and increases the learnability of the test set of the present invention.
  • next valid steps could be either demultiplexing the DS3 signal to test an embedded DS1 tributary (by choosing the M13 "circuit” icon ) or directly terminating the DS3 signal for testing (by choosing the DS3 "test” icon 55).
  • the user touches (or clicks) on the M13 "circuit” icon 53, as shown in Fig. 6.
  • a circuit is graphically drawn showing the connection from the DS3 "signal” icon 51 to the DS1 "test” icon 57 via the M13 "circuit” icon 53.
  • FIGs. 7 and 8 show the two user inputs required to activate another test configuration, where an STS-1 (EC-1) signal is used as a starting point and an embedded DS3 signal is to be terminated and tested.
  • an STS-1 (EC-1) signal is used as a starting point and an embedded DS3 signal is to be terminated and tested.
  • the user physically connects an STS-1 (EC-1) signal to the test set; therefore, intuitively, as a first step, the user touches (or clicks) on the EC- 1 "signal" icon 59. The selected icon becomes highlighted and the valid options for the next step are highlighted to the user in a different color (see Fig. 7).
  • next valid steps could be either extracting and terminating a DS3 for testing (by choosing the DS3 "test” icon 61) or directly terminating the STS-1 signal for testing (by choosing the STS-1 "test” icon 63) or demultiplexing an embedded DS3 to extract a DS1 for testing (by choosing the M13 "test” icon 67) or directly extracting a DS1 out of the STS-1 for testing (by choosing the VT1.5 icon 65).
  • the user will touch (or click) on the DS3 "test” icon 61 (see
  • Figures 9 to 13 show three other similar examples for further comprehension of the principle in which the user sets up for testing DS1 out of an OC-N signal, packets out of a 10/100/1 OOOBaseTX interface and packets out of an OC-Nc signal.
  • This last example actually illustrates an example of interaction between the TDM communication test module and the packet communication test module in which packets are tested out of a TDM signal (OC-Nc).

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Human Computer Interaction (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Telephone Function (AREA)

Abstract

La présente invention concerne un dispositif d'essai portatif orienté champ qui permet la validation de communications à la fois basées sur le circuit numérique (MRT) et basées sur les paquets de données. L'ensemble d'essai fait intervenir un procédé et une interface graphique utilisateur servant à configurer des essais basés sur la communication DS1, DS3, SONET et par paquets, un procédé et un système permettant de tester un lien Ethernet WAN par utilisation d'un modèle de séquence binaire pseudo-aléatoire (Pseudo-Random Bit Sequence / PRBS), ainsi qu'un procédé et un système servant à valider à distance une communication 10/100/1000BaseTX WAN duplex intégral en pleine vitesse en ligne (1Gbps) au moyen d'un dispositif d'essai unique et d'un accessoire peu onéreux associé au dispositif d'essai.
PCT/CA2001/000615 2000-06-05 2001-05-02 Dispositif d'essai electronique portatif pour reseaux de telecommunications WO2001095561A2 (fr)

Priority Applications (2)

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AU2001258081A AU2001258081A1 (en) 2000-06-05 2001-05-02 Hand-held electronic tester for telecommunications networks
EP01931246A EP1290826A2 (fr) 2000-06-05 2001-05-02 Dispositif d'essai electronique portatif pour reseaux de telecommunications

Applications Claiming Priority (4)

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US58753600A 2000-06-05 2000-06-05
CA002310887A CA2310887A1 (fr) 2000-06-05 2000-06-05 Controleur electronique manuel pour reseaux de telecommunications
US09/587,536 2000-06-05
CA2,310,887 2000-06-05

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EP1367750A1 (fr) * 2002-05-30 2003-12-03 Agilent Technologies, Inc. - a Delaware corporation - Dispositif pour tester des communications dans un réseau transportant des tramesde données
EP1367749A1 (fr) * 2002-05-30 2003-12-03 Agilent Technologies, Inc. - a Delaware corporation - Dispositif pour tester des communications dans un réseau transportant des trames de données
EP1420543A1 (fr) * 2002-11-15 2004-05-19 Tektronix International Sales GmbH Méthode pour adapter une interface utilisateur sur l' afficheur d'un testeur de protocol et testeur de protocol correspondant
EP1499050A2 (fr) * 2003-07-14 2005-01-19 Anritsu Corporation Dispositif et procédé de génération de trames multiplexées synchrones comprenant des canaux de types TUG3/STS3 et TUG2/VTG
GB2410394A (en) * 2004-01-22 2005-07-27 Agilent Technologies Inc Service disruption time determination in packet switched networks
EP1689152A1 (fr) * 2005-02-08 2006-08-09 Tektronix International Sales GmbH Dispositif et procédé de test de charge pour un réseau de télécommunication
WO2007040482A1 (fr) * 2005-09-23 2007-04-12 Nettest (New York) Inc. Appareil et procede permettant d'effectuer un essai de rebouclage dans un systeme de communications
CN1330138C (zh) * 2003-04-17 2007-08-01 华为技术有限公司 一种对以太网接口进行测试的码流发生器
US7408883B2 (en) 2004-09-01 2008-08-05 Nettest, Inc. Apparatus and method for performing a loopback test in a communication system
US10171127B2 (en) 2017-05-19 2019-01-01 Rohde & Schwarz Gmbh & Co. Kg Method, system and computer program for synchronizing pseudorandom binary sequence modules

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Publication number Priority date Publication date Assignee Title
EP1367749A1 (fr) * 2002-05-30 2003-12-03 Agilent Technologies, Inc. - a Delaware corporation - Dispositif pour tester des communications dans un réseau transportant des trames de données
EP1367750A1 (fr) * 2002-05-30 2003-12-03 Agilent Technologies, Inc. - a Delaware corporation - Dispositif pour tester des communications dans un réseau transportant des tramesde données
EP1420543A1 (fr) * 2002-11-15 2004-05-19 Tektronix International Sales GmbH Méthode pour adapter une interface utilisateur sur l' afficheur d'un testeur de protocol et testeur de protocol correspondant
US8364791B2 (en) 2002-11-15 2013-01-29 Tektronix, Inc. Adapting a user interface on a display device of a protocol tester
CN1330138C (zh) * 2003-04-17 2007-08-01 华为技术有限公司 一种对以太网接口进行测试的码流发生器
EP1499050A2 (fr) * 2003-07-14 2005-01-19 Anritsu Corporation Dispositif et procédé de génération de trames multiplexées synchrones comprenant des canaux de types TUG3/STS3 et TUG2/VTG
EP1499050A3 (fr) * 2003-07-14 2006-06-07 Anritsu Corporation Dispositif et procédé de génération de trames multiplexées synchrones comprenant des canaux de types TUG3/STS3 et TUG2/VTG
GB2410394B (en) * 2004-01-22 2007-04-04 Agilent Technologies Inc Service disruption time determination apparatus and method therefor
GB2410394A (en) * 2004-01-22 2005-07-27 Agilent Technologies Inc Service disruption time determination in packet switched networks
US7408883B2 (en) 2004-09-01 2008-08-05 Nettest, Inc. Apparatus and method for performing a loopback test in a communication system
US7864691B2 (en) 2004-09-01 2011-01-04 Anritsu Instruments Company Apparatus and method for performing a loopback test in a communication system
EP1689152A1 (fr) * 2005-02-08 2006-08-09 Tektronix International Sales GmbH Dispositif et procédé de test de charge pour un réseau de télécommunication
US7496814B2 (en) 2005-02-08 2009-02-24 Tektronix, Inc. Load testing of a telecommunication network
WO2007040482A1 (fr) * 2005-09-23 2007-04-12 Nettest (New York) Inc. Appareil et procede permettant d'effectuer un essai de rebouclage dans un systeme de communications
US10171127B2 (en) 2017-05-19 2019-01-01 Rohde & Schwarz Gmbh & Co. Kg Method, system and computer program for synchronizing pseudorandom binary sequence modules

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WO2001095561A3 (fr) 2002-08-08
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