WO2001093430A1 - Modulateur sigma-delta pourvu d'un recepteur frontal - Google Patents

Modulateur sigma-delta pourvu d'un recepteur frontal Download PDF

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Publication number
WO2001093430A1
WO2001093430A1 PCT/SE2001/001214 SE0101214W WO0193430A1 WO 2001093430 A1 WO2001093430 A1 WO 2001093430A1 SE 0101214 W SE0101214 W SE 0101214W WO 0193430 A1 WO0193430 A1 WO 0193430A1
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WO
WIPO (PCT)
Prior art keywords
standard
delta modulator
bit
sigma
quantizer
Prior art date
Application number
PCT/SE2001/001214
Other languages
English (en)
Inventor
Steffen Albrecht
Bingxin Li
Xiaopeng Li
Constantino Pala
Mohammed Ismail
Hannu Tenhunen
Original Assignee
Spirea Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spirea Ab filed Critical Spirea Ab
Priority to AU2001262859A priority Critical patent/AU2001262859A1/en
Publication of WO2001093430A1 publication Critical patent/WO2001093430A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/392—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type

Definitions

  • the present invention relates to sigma delta modulators. More particularly the present invention involves the integration of multi-standard base-band signal A/D conversion for RF receiver into a single sigma-delta modulator.
  • sigma delta modulators can be used for GSM and DECT base-band signal A/D conversion.
  • Other wireless standards such as DCS1800, PHS can also use a sigma delta modulator to convert its base-band signal as long as the signal band can be handled by oversampling sigma delta modulators.
  • the base-band width of such standards can range from about 100k Hz to several Mega- Hz.
  • the dynamic range requirement of the A/D converter is determined by the receiver front-end architecture.
  • the reasons of using a sigma delta modulator in such applications are mainly to achieve high resolution, to reduce the strict requirement on analog anti-alias filter, to make the use of cheap and robust CMOS process and to achieve high level integration of the whole RF receiver system.
  • a multi-standard RF receiver should be able to process multi-standard signal in a single terminal. Accordingly the A/D converter in such a receiver terminal should have the capability to convert the analog signals with different bandwidth and dynamic range requirements.
  • H- H- l-i TJ > O H O 0 tr H 0 o ⁇ 3 o 0 l-i ⁇ co ⁇ p 0 ⁇ O ⁇ CD l-i rt l-i N ⁇
  • CD O ⁇ CO ⁇ P CD Hi H- 3 ⁇ P H- fD ⁇ 0 1 rt ⁇ 3 0 rt rt ⁇ ⁇ - O CO ⁇ r rr H- • ⁇ CD H H- rf • CD s: - CO ⁇ P CO O O ⁇ - TJ O rt tr ⁇ ⁇ ⁇ - ⁇ P 0 ⁇
  • the invention provides for a mechanism to switch between a 1-bit and a multi-bit quantizer into use for different standard modes.
  • a multi-bit quantizer should be used to achieve the resolution specification, while in other modes a simple one-bit quantizer can be used to save power.
  • a simple one-bit quantizer can be used to save power.
  • each specific mode its corresponding quantizer is selected and the unused quantizer is shut down to minimize the overall power consumption.
  • capacitor sharing and switching mechanism that uses the same capacitor array to form the switched capacitor circuit needed by different standard modes.
  • the choice of capacitor size is decided by the kT/C noise consideration and loop coefficients.
  • Figure 1 shows the block diagram of a multi-standard receiver structure
  • Figure 2 shows a 2-2 cascaded sigma-delta modulator in accordance with an embodiment of the present invention
  • Figure 3 shows the switching between 1-bit and multi-bit quantizers in different standard modes; and Figure 4 shows the capacitor sharing mechanism in switched capacitor integrator. Description of embodiments
  • a RF filter passes the band of interest through an RF/IF process block.
  • This RF/IF process block can have e.g. a direct conversion architecture or a wide-band IF with double conversion architecture.
  • the succeeding A/D block should meet a corresponding dynamic range requirement which is decided by the out-of- band noise distribution.
  • This dynamic range normally can range from 8 ⁇ 9 bits to as high as 15 ⁇ 16 bits for different wireless standards. To achieve such a wide dynamic range, using a sufficiently high order sigma-delta modulator is a necessity.
  • Figure 2 shows a 2- 2 cascaded modulator according to an embodiment of the present invention.
  • a basic 2-2 cascaded modulator was proposed in ⁇ N Fouth Order Sigma-Delta Modulator Circuit for Digital Audio and ISDN Application", IEE European Circuit theory and Design Conference, 1989, P. 223-227.
  • This previously proposed modulator comprises the first stage and a straight forward structure of the second stage of the inventive modulator. That straight forward structure has no alternative signal paths; for example it has a single B-bit quantizer and no adjustable loop coefficients.
  • the 4th order noise shaping promises sufficient in-band noise attenuation, and the cascade structure promises stability of feedback loop.
  • the dynamic range of such a modulator is:
  • DN (in bit) 4.5*log 2 M+ log 2 (2 B -1) - offset
  • M the oversampling ratio
  • B the resolution (in bit) of the second stage's quantizer
  • offset is a value normally around 7 depending on the detailed scaling factor. In real implementations, due to the circuit non- idealities and kT/C noise, this offset can be even larger and the achievable dynamic range is further reduced.
  • the second stage of the modulator comprises a first integrator 21 and a second integrator 22, a first loop coefficient switch 23, connected to the output of the first integrator 21 and switching between a first and a second loop coefficient el and e2 respectively, a second loop coefficient switch 24, constituting part of the feedback loop of the second stage and switching between a third and a fourth loop coefficient fl and fl respectively.
  • the loop coefficients are connected to the second integrator 22.
  • the modulator comprises a 1-bit/3-bit quantizer connected to the output of the second integrator 22, and a l-bit/3-bit DAC 30 connected to the output of the quantizer 25 and constituting a first element of said feedback loop.
  • the l-bit/3-bit quantizer comprises a quantizer switch 26, a 1-bit quantizer 27, and a 3-bit quantizer 28, wherein said quantizer switch is arranged to switch between said 1-bit and 3-bit quantizers 28.
  • the output of the l-bit/3-bit quantizer 25 is further connected to a digital error correction logic 29, which provides an output to a deci ator (not shown) .
  • the l-bit/3-bit DAC comprises a 1- bit DAC 31, a 3-bit DAC 32, and a DAC-switch 33, arranged to switch between the outputs of said 1-bit and 3-bit DACs .
  • the output of the DAC-switch 33 is connected to inter alia said second loop coefficient switch 24.
  • a mode selecting signal ⁇ is used to select a proper sampling frequency and a proper quantizer 27/28 for each standard mode.
  • the mode selection signal ⁇ controls the first and second loop coefficient switches 23 and 24, the quantizer switch 26, and the DAC-switch 33. All the hardware components that have nothing to do with this switching mechanism are shared by all standards.
  • the mode selection signal in turn is generated by another circuit of the multi- standard receiver, which circuit is able to identify the standard which the presently received radio signal complies with.
  • Figure 3 shows the switching method of l-bit/3-bit quantizer 25 of the second stage.
  • the proper quantizer When operating in a specific standard mode, the proper quantizer is switched into use by the mode selection signal ⁇ .
  • the power supply of unused quantizer is also switched off.
  • the presently unused DAC is powered down. This eliminates unnecessary power consumption.
  • the signal and power switches, i.e. the quantizer switch 26, can be realized with properly sized transmission-gates, and more specifically by means of MOS transistors.
  • the loop coefficients are realized by the ratio between capacitors, which ideally is not related to their absolute values.
  • the kT/C noise consideration sets a minimum capacitor value in the high-resolution application.
  • the process mismatch which limits the minimum value of the capacitors so that the deviation of capacitor ratio is under control.
  • the capacitor values should be selected as small as possible because the power used to charge and discharge these capacitors is directly proportional to their values. Since in different standard modes kT/C noise is of different level of importance, the minimum allowed capacitor values are also different.
  • the OTAs in integrators are shared by all the standard modes.
  • the OTAs are designed to meet the strictest specification of all the standards, yet still maintain small area and low power consumption. Thus they are designed to work under the highest sampling frequency with largest capacitance load that are required by all the standards to be handled. These requirements can be translated into a set of specifications such as DC gain, bandwidth and slew-rate for OTA design.
  • the first and the last OTAs should have larger driving capability because their capacitance loads are relatively large. For the first OTA this large capacitance load comes from the kT/C noise considerations which leads to a large sampling and integration capacitor. For the last OTA this large capacitance load comes from the ulti bit quantizer which includes an array of sample-hold circuits and comparators .
  • a 3-bit quantizer is disclosed. This is merely one example of a multi-bit quantizer, which is to be used according to the invention. Thus, other ' resolutions can be chosen as appropriate considering what different standards the modulator should be able to handle. Further, the resolution of the multi-bit DAC is adjusted accordingly.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

La présente invention concerne un modulateur sigma-delta qui fonctionne selon différents modes standards pour traiter des signaux de communications de différentes normes de communications. Ce modulateur comprend un quantificateur à 1 bit et un quantificateur à bits multiples, et un mécanisme de commutation permettant de basculer entre lesdits quantificateurs en fonction du mode standard. Par ailleurs, cette invention concerne un convertisseur A/N intégrant ce modulateur, un récepteur RF multistandard intégrant ce convertisseur A/N, et un procédé de traitement des signaux de communication de différentes normes de communication.
PCT/SE2001/001214 2000-05-31 2001-05-30 Modulateur sigma-delta pourvu d'un recepteur frontal WO2001093430A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001262859A AU2001262859A1 (en) 2000-05-31 2001-05-30 A front-end receiver sigma-delta modulator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE0002065A SE518012C2 (sv) 2000-05-31 2000-05-31 Sigma-Delta-Modulator i frontmottagare samt A/D-omvandlare innefattande en dylik och en metod för signalbehandling
SE0002065-1 2000-05-31

Publications (1)

Publication Number Publication Date
WO2001093430A1 true WO2001093430A1 (fr) 2001-12-06

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PCT/SE2001/001214 WO2001093430A1 (fr) 2000-05-31 2001-05-30 Modulateur sigma-delta pourvu d'un recepteur frontal

Country Status (3)

Country Link
AU (1) AU2001262859A1 (fr)
SE (1) SE518012C2 (fr)
WO (1) WO2001093430A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1394950A2 (fr) * 2002-08-29 2004-03-03 Infineon Technologies AG Quantificateur pour un modulateur sigma-delta et modulateur sigma-delta
US6980139B2 (en) 2002-08-29 2005-12-27 Infineon Technologies Ag Sigma-delta-modulator
DE102004027488A1 (de) * 2004-06-04 2005-12-29 Infineon Technologies Ag Sigma-Delta-Modulator
WO2009053949A1 (fr) * 2007-10-22 2009-04-30 Freescale Semiconductor, Inc. Convertisseur analogique/numérique à modes multiples, système de traitement de signaux et appareil électronique

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454406A1 (fr) * 1990-04-26 1991-10-30 Hughes Aircraft Company Convertisseur à étages multiples sigma-delta analogique-numérique
US5345406A (en) * 1992-08-25 1994-09-06 Wireless Access, Inc. Bandpass sigma delta converter suitable for multiple protocols
EP0757446A2 (fr) * 1995-08-04 1997-02-05 Nokia Mobile Phones Ltd. Convertisseur analogiques-numériques et numériques-analogiques
WO1999025075A2 (fr) * 1997-11-07 1999-05-20 Koninklijke Philips Electronics N.V. Dispositif de communication sans fil
EP0954107A2 (fr) * 1998-04-27 1999-11-03 Motorola, Inc. Méthode de modulation et modulteur sigma-delta

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454406A1 (fr) * 1990-04-26 1991-10-30 Hughes Aircraft Company Convertisseur à étages multiples sigma-delta analogique-numérique
US5345406A (en) * 1992-08-25 1994-09-06 Wireless Access, Inc. Bandpass sigma delta converter suitable for multiple protocols
EP0757446A2 (fr) * 1995-08-04 1997-02-05 Nokia Mobile Phones Ltd. Convertisseur analogiques-numériques et numériques-analogiques
WO1999025075A2 (fr) * 1997-11-07 1999-05-20 Koninklijke Philips Electronics N.V. Dispositif de communication sans fil
EP0954107A2 (fr) * 1998-04-27 1999-11-03 Motorola, Inc. Méthode de modulation et modulteur sigma-delta

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1394950A2 (fr) * 2002-08-29 2004-03-03 Infineon Technologies AG Quantificateur pour un modulateur sigma-delta et modulateur sigma-delta
EP1394950A3 (fr) * 2002-08-29 2004-07-14 Infineon Technologies AG Quantificateur pour un modulateur sigma-delta et modulateur sigma-delta
US6980139B2 (en) 2002-08-29 2005-12-27 Infineon Technologies Ag Sigma-delta-modulator
DE102004027488A1 (de) * 2004-06-04 2005-12-29 Infineon Technologies Ag Sigma-Delta-Modulator
WO2009053949A1 (fr) * 2007-10-22 2009-04-30 Freescale Semiconductor, Inc. Convertisseur analogique/numérique à modes multiples, système de traitement de signaux et appareil électronique

Also Published As

Publication number Publication date
SE0002065D0 (sv) 2000-05-31
SE0002065L (sv) 2001-12-01
SE518012C2 (sv) 2002-08-13
AU2001262859A1 (en) 2001-12-11

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