WO2001090865A1 - Synchronisation temporelle dans un systeme de traitement reparti - Google Patents

Synchronisation temporelle dans un systeme de traitement reparti Download PDF

Info

Publication number
WO2001090865A1
WO2001090865A1 PCT/US2001/015945 US0115945W WO0190865A1 WO 2001090865 A1 WO2001090865 A1 WO 2001090865A1 US 0115945 W US0115945 W US 0115945W WO 0190865 A1 WO0190865 A1 WO 0190865A1
Authority
WO
WIPO (PCT)
Prior art keywords
synchronization
real time
distributed
central
computer system
Prior art date
Application number
PCT/US2001/015945
Other languages
English (en)
Inventor
Brian C. Deck
Joseph D. Kidder
Roland T. Provecher
Peter B. Everdell
Original Assignee
Equipe Communications Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/574,343 external-priority patent/US6639910B1/en
Priority claimed from US09/574,341 external-priority patent/US7062642B1/en
Application filed by Equipe Communications Corporation filed Critical Equipe Communications Corporation
Priority to AU2001261711A priority Critical patent/AU2001261711A1/en
Publication of WO2001090865A1 publication Critical patent/WO2001090865A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/22—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks comprising specially adapted graphical user interfaces [GUI]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements

Definitions

  • a distributed processing system is a collection of independent computers that appear to the user of the system as a single computer.
  • a distributed processing system includes a main or central control processing module, card or printed circuit board (herein after module) having a central control processing subsystem (“central controller") that actively controls system operation by performing a major portion of the control functions (e.g., booting and system management) for the system, hi addition, a distributed processing system includes multiple distributed processing modules that each include a control processor subsystem ("distributed controllers").
  • Each control processor subsystem including the central controller and distributed controllers, executes software to control their local module and to communicate with the other control processor subsystems.
  • Each control processor subsystem operates in an autonomous fashion but the software presents the distributed processing system to the user as a single computer.
  • the central controller and the distributed controllers operate independently, there are many instances when it is important that they are synchronized to the same clock signal.
  • events when faults, errors or other types of events occur (hereinafter collectively referred to as events), generally a record in a log is created including a time-stamp.
  • the time-stamp helps relate one event to other events, which may help in determining a cause, a solution and/or next steps to take as a response to the event.
  • the time-stamps may be used to help determine if events on multiple modules are related. Unfortunately, it is difficult to synchronize control subsystems on different modules.
  • time-stamps are typically only one second, corresponding to the low resolution provided by publicly available real-time clock (RTC) chips. Since a great many events may occur within the same second, it may be impossible to determine the order in which logged events occurred.
  • RTC real-time clock
  • synchronization of a distributed processing system is initiated by sending a synchronization command across a software controlled communication bus to each controller (central and distributed).
  • each controller central and distributed.
  • one or more controllers may be busy handling other commands or interrupts and, thus, the execution of the synchronization command by each controller may vary. Such variation may lead to inaccurate or insufficient synchronization across the distributed processing system, which may cause faults and/or a system crash.
  • the present invention provides a method of synchronizing a distributed processing computer system including the steps of sending a synchronization set up command over a first bus to one or more distributed processor modules and sending a synchronization execution command over a second bus to the distributed processor modules.
  • Sending the synchronization execution command may include detecting a system reference clock pulse and sending the synchronization execution command over the second bus to the distributed processor modules in response to the detection of the system reference clock pulse.
  • the method may also include the steps of clearing high resolution real time clocks on the distributed processor modules and a central processor module in response to the synchronization execution command and sending an interrupt signal to local controller processing subsystems on the distributed processing modules and the control processor module in response to the synchronization execution command.
  • the method may further include writing a synchronization time into low resolution real time clocks on the distributed processor modules and the central processing module in response to the interrupt.
  • the high resolution real time clocks may include counters, and clearing high resolution real time clocks may include resetting the high resolution clocks.
  • the low resolution real time clocks may include real time clock integrated circuits, and writing the synchronization time into low resolution real time clocks may include resetting the low resolution real time clocks.
  • Writing the synchronization time into low resolution real time clocks includes reading a synchronization command from a control register within the hardware controller on the distributed processor modules and the central processor module and writing the synchronization time provided with the synchronization set up command into the low resolution real time clocks.
  • a central processor may send the synchronization set up command, and the distributed processing computer system comprises a network device.
  • the present invention provides a method of distributing a real time clock in a distributed processing computer system including the steps of providing a system reference clock to one or more distributed processing modules and a central processing module, broadcasting a synchronization execution command to the distributed processing modules, clearing a real time counter in each of the distributed processing modules and in the central processing module in response to the broadcast synchronization execution command and using the system reference clock to increment each of the real time counters.
  • the distributed processing computer system may include a network device.
  • the present invention provides a distributed processing computer system including a central controller, one or more distributed controllers, a first communication bus coupled to the central controller, wherein the central controller is capable of transmitting synchronization set up commands over the first communication bus to the distributed controllers and a second communication bus couple to the central controller, wherein the central controller is capable of transmitting synchronization execution commands over the second communication bus to the distributed controllers.
  • the distributed processing computer system may also include a central hardware controller coupled to the central controller for transmitting synchronization execution commands over the second communication bus.
  • the first communication bus may be an Ethernet bus
  • the second communication bus may be an Inter-IC communications bus.
  • the distributed processing computer system may be a network device.
  • the present invention provides a computer system including a real time clock having both a low resolution real time clock and a high resolution real time clock.
  • the low resolution real time clock may be a real time clock integrated circuit component.
  • the computer system may include a system reference clock, and the high resolution real time clock may be a time counter incremented by the system reference clock.
  • FIG. 1 is a block diagram of a computer system with a distributed processing system
  • Fig. 2 is a block diagram of a computer system with a hardware controlled communication bus
  • Fig. 3 is a block diagram of a distributed hardware controller and a distributed controller
  • Fig. 4 is a block diagram of a distributed processing computer system having central and distributed timing subsystems.
  • Figs. 5 and 6 are flow diagrams depicting a method of synchronizing a distributed processing computer system.
  • the present invention provides time synchronization across a distributed processing system by sending a synchronization set up command over a first bus and sending a synchronization execution command over a second bus.
  • a distributed system reference clock is also used to insure that central and distributed controllers each synchronize to the same clock signal. Synchronization is set up through a software controlled commumcation bus and actual synchronization is executed through a hardware controlled communication bus. Use of a hardware controlled communication bus provides immediate synchronization of a high resolution real time clock and permits delayed synchronization of a lower resolution real time clock. Consequently, within a predetermined amount of time, the central and distributed controllers are accurately synchromzed. In addition, the increased resolution of the real time clock allows for more granular time stamps and more accurate time synchronization across the distributed processing system.
  • computer system 10 includes a central controller module 12 with a central control processor subsystem (“central controller") 14 that executes an instance of kernel software 20 including master control programs and server programs to actively control system operation by performing a major portion of the control functions (e.g., booting and system management) for the system.
  • central controller central control processor subsystem
  • computer system 10 includes multiple distributed controller modules 16a-16n.
  • Each distributed controller module includes a distributed control processor subsystem (“distributed controller") 18a- 18n, which runs an instance of kernel software 22a-22n including slave and client programs as well as module specific software applications.
  • Each control processor subsystem 14, 18a-18n operates in an autonomous fashion but the software presents computer system 10 to the user as a single computer.
  • Each control processor subsystem includes a processor integrated circuit (chip) 24, 26a-26n, for example, a Motorola 8260 or an Intel Pentium processor.
  • the control processor subsystem also includes a memory subsystem 28, 30a-30n including a combination of non- volatile or persistent (e.g., PROM and flash memory) and volatile (e.g., SRAM and DRAM) memory components.
  • Computer system 10 also includes a software controlled internal communication bus 32 coupled to each processor 24, 26a- 26n.
  • the software controlled communication bus is a switched Fast Ethernet providing 100Mb of dedicated bandwidth to each processor allowing the distributed processors to exchange control information at high frequencies.
  • a backup or redundant Ethernet switch may also be connected to each board such that if the primary Ethernet switch fails, the boards can fail-over to the backup Ethernet switch.
  • Computer system 10 may be a network device, for example, a switch, router or hybrid switch-router, in which case, computer system 10 may also include a data path 34.
  • Ethernet 32 provides an out-of-band control path, meaning that control information passes over Ethernet 32 but the network data being switched by computer system 10 passes to and from external network connections 31a-31x over data path 34.
  • External network control data is passed from the distributed controller modules to the central controller module over Ethernet 32.
  • Computer system 10 also includes a hardware controlled communications bus 33.
  • Hardware controlled communications bus 33 is provided for low level system service operations, including, for example, the detection of newly installed (or removed) hardware, reset and interrupt control and real time clock (RTC) synclironization across the system.
  • RTC real time clock
  • this is an Inter-IC communications (I 2 C) bus. See http://www.semiconductors.philips.com for an I C specification which is incorporated herein by reference.
  • hardware controlled communications bus 33 is coupled with a central hardware controller 36 on the central controller module 12 and with a distributed hardware controller 38a-38n on each of the distributed controller modules 16a-16n.
  • the hardware controllers 36, 38a-38n are connected to the central controller 14 and distributed controllers 18a-18n, respectively as well as various other hardware.
  • the hardware controllers are field programmable gate arrays (FPGAs), available, for example, from Xilinx Corporation of San Jose, CA.
  • the hardware controllers may be discrete logic or application specific integrated circuits (ASICs).
  • ASICs application specific integrated circuits
  • bus 33 may include multiple busses.
  • a backup or redundant hardware communications bus may also be connected to each board such that if the primary hardware commumcations bus fails, the boards can fail-over to the backup hardware communications bus.
  • each distributed hardware controller 38a-38n includes two registers, a control register 40 and a status register 42.
  • these registers are eight bits wide corresponding to eight bit I 2 C commands and allowing for up to 256 different commands and 256 different statuses.
  • Each distributed controller 18a-18n writes data representing the status of its module into its status register 42, and central controller 14 uses communications bus 33 to read the data from each of the status registers 42. If the distributed controller does not write status into status register 42, then a default value of, for example, 00000001, will be present and when read by the central controller may be used as an indication that the distributed controller did not boot properly. If the distributed controller does boot properly, it may enter a value of, for example, 00000002, in the status register and when read by the central controller may be used as an indication that the distributed controller booted properly but has not yet passed its diagnostic tests. If the distributed controller does pass its diagnostic tests, it may enter a value of, for example, 00000003, in the status register and. when read by the central controller will indicate that the distributed controller is operating properly. Various other statuses may be written into status register 42 to notify the central controller of the distributed module's status.
  • Central controller 14 uses communications bus 33 to write data representing encoded commands into control register 40.
  • Control hardware 44 within distributed hardware controllers 38a-38n detects newly written commands, decodes the commands and takes actions in accordance with the decoded commands. For example, a reset command may be decoded and the distributed hardware controller 38a-38n may cause a reset line 46 to send a reset signal to multiple hardware components on the distributed controller module.
  • a synchronization command may be decoded and acted on as described below.
  • a high resolution clock signal may be used within computer system 10 to improve synchronization across all modules and to provide for finer granularity time- stamps on logged events.
  • the central controller module 12 includes a real time clock
  • RTC distributed controller
  • each distributed controller module 16a-16n includes an RTC chip 50a-50n.
  • RTC chips 49 and 50a-50n are connected to the central controller 14 and distributed controllers 18a-18n, respectively, and the central and distributed controllers may read a time from their local RTC chip, including the year, month, day, hour, minute and second. Typically, the lowest resolution provided by publicly available RTC chips is seconds.
  • the distributed controllers may also write a time into the RTC chip to reset or synchronize the RTC chip with other RTC chips within the system.
  • the central and distributed controllers may use the time read from their local RTC chip as a time-stamp for logged events. Many events, however, may happen in the same second and when logged each event may be assigned the same time-stamp. Having the same time-stamp for multiple events increases the difficultly of later determining the correct sequence of the logged events. Similarly, if the RTC chips used by the central and distributed controllers are not synchronized, then time stamps alone may not accurately reflect the sequence of events on multiple modules.
  • the central hardware controller includes a time counter 51 and the distributed hardware controllers include time counters 52a-52n.
  • the hardware controllers (central and distributed) increment the time counters on microsecond intervals.
  • the controller e.g., central controller 14 or distributed controllers 18a-18n
  • the controller responsible for logging the event reads the time from both the local RTC chip 49 or 50a-50n and the time counter 51 or 52a-52n. Consequently, the time-stamp resolution is increased from seconds to microseconds providing significantly better granularity.
  • the time counter is 32 bits allowing the hardware controllers to count microseconds, seconds, minutes and hours, up to one hundred and forty-nine hours.
  • the controller e.g., central controller 14 and distributed controllers 18a-18n
  • the added hardware required to provide a real time clock with higher resolution consumes valuable system resources, however, higher resolution provides significant advantages such as more accurate synchronization and finer granular time-stamps.
  • an 8KHz clock signal 53 and 54a-54n is delivered to each hardware controller. The hardware controllers may then increment the time counters upon the detection of each clock pulse.
  • the 8KHz clock signal may be provided in various ways.
  • an oscillator chip may be present on each board and used to provide the 8KHz clock signal to each chip either directly from the oscillator chip if it is 8KHz or through other discrete logic that may multiply or divide the signal from the oscillator chip to provide 8KHz.
  • system reference clock signals are sent instead from a central timing subsystem 56 on the central controller module to a distributed timing subsystem 57 and 58a-58n on each module.
  • the central timing subsystem may send 8KHz signals directly to each of the distributed timing subsystems or, preferably, combination clock signals 59 and 60a-60n are sent from central timing subsystem 56 to each distributed timing subsystems 57 and 58a-58n. Often, many different clock signals are required by each module, and hardware within the distributed timing subsystems derive the necessary clock signals from the combination clock signal.
  • central timing subsystem 56 provides a hard-wired clock signal 59, 60a-60n to each distributed timing subsystem 58a-58n which is a combination of a 19.44MHz clock signal and an 8KHz clock signal.
  • Clock signals 59 and 60a-60n are separate hard-wired signals due to load restrictions and the importance of clean, strong clock signals.
  • one clock signal may be shared by two or more of the distributed timing subsystems.
  • the distributed timing subsystem then extracts the 8KHz clock signal from the combination clock signal and provides the 8KHz clock signal 53, 54a- 54n to central hardware controller 36 and distributed hardware controllers 38a-38b, respectively.
  • the hardware controllers use the 8KHz clock signals to synchronously increment their time counters.
  • the distributed processing system is a network device connected to external optical fibers carrying signals following the synchronous optical network (SONET) protocol, and the 8KHz clock signal also provides timing for SONET framing.
  • SONET synchronous optical network
  • Multiples of 19.44MHz provide base frequencies for various SONET data transfer rates. For example, four times 19.44MHz is 77.76MHz which is the base frequency for an OC1 SONET stream, two times 77.76MHz provides the base frequency for an OC3 SONET stream and eight times 77.76MHz provides the base frequency for an OC12 SONET stream.
  • central controller 14 initiates (block 70) a synchronization cycle.
  • the synchronization cycle includes synchronization set up and synchronization execution.
  • For synchronization set up the central controller sends (block 72) a synchronization command across software controlled commumcation bus 32 (e.g., Ethernet bus) to each distributed controller.
  • the synchronization command tells each distributed controller to prepare for a synchronization execution and provides a synchronization time to be used at the next synchronization execution.
  • central controller 14 sets up (block 74) central hardware controller 36 to perform a broadcast write over hardware controlled communications bus 33 (e.g., I 2 C bus, Fig. 4) to write a synchronization command into control register 40 (Fig. 3) within each hardware controller 38a-38n.
  • hardware controlled communications bus 33 e.g., I 2 C bus, Fig. 4
  • central hardware controller 36 then broadcast writes a synchronization command over the hardware controlled communication bus to the control register within each distributed hardware controller 38a-38n.
  • Both the central and distributed hardware controllers then clear their time counters 51 and 52a-52n prior to the next 8KHz clock pulse and send an interrupt over lines 75 and 77a-77n to their local controller (e.g., central controller 12 or distributed controllers 18a-18n).
  • the 8KHz system reference clock on line 53 may be treated by central hardware controller 36 as an interrupt and masked until central controller 14 sets up central hardware controller 36 for the broadcast write.
  • a distributed controller receives (block 76) a synchronization set up command and synchronization time over software controlled communication bus 32, the distributed controller prepares (block 78) to write the synchronization time into its local RTC chip 50a-50n.
  • the central controller After sending the synchronization set up command, the central controller also prepares (block 78) to write the synchronization time into its local RTC chip 49.
  • the distributed hardware controllers receive (block 80) a broadcast synchronization command over hardware controlled bus 33, they clear (block 82) their time counter 52a-52n and send (block 84) an interrupt to their local distributed controller 18a-18n.
  • the central hardware controller sends the broadcast synchronization command over the hardware communication bus
  • the central hardware controller clears (block 82) its time counter 51 and sends (block 84) an interrupt to central controller 14.
  • central controller 14 and distributed controllers 18a-18n When central controller 14 and distributed controllers 18a-18n receive an interrupt from their local hardware controllers 36, 38a-38n, respectively, they read the control register within their local hardware controller.
  • the synchronization command read from the control register causes the central and distributed controllers to write the synchronization time previously received during the synchronization set up command sent over the software controlled communication bus 32 into their local RTC chip 49 and 50a-50n. Once the synchronization time is written into the RTC chips, then all modules within the computer system are synchronized.
  • the central and distributed controllers may be busy handling other commands and interrupts when they receive the interrupt from the hardware controller, thus, each may be delayed a different amount of time with respect to the others with regard to synchronizing their local RTC chips. These delays are not long, however, and in any event, the high resolution real time clock stored in the time counters are synchronized immediately upon receipt of the broadcast synchronization command. Broadcasting the synchronization command on the rising edge of the 8KHz system reference clock insures that each of the hardware controllers will have enough time to clear their time counter before the next 8KHz clock pulse, thus, synchronizing each time counter to the same 8KHz clock pulse.
  • each of the modules are immediately synchronized at the highest resolution.
  • the RTC chips generally hold the year, month, day, hour, and second.
  • the central and distributed controllers may use the year, month and day from the RTC chip and the hour, minute, second, millisecond and microsecond from the time counter. In this case, the controllers would have a full day or 24 hours to synchronize their RTC chips. Instead, the central and distributed controllers may use the year, month, day and hour from the RTC chip and the minute, second, millisecond and microsecond from the time counter.
  • the controllers would have 1 hour or 60 minutes to synchronize their RTC chips.
  • the central and distributed controllers may use the year, month, day, hour and minute from the RTC chip and the second, millisecond and microsecond from the time counter. In this case, the controllers would have 1 minute or 60 seconds to synchronize their RTC chips.
  • the central and distributed controllers may use the year, month, day, hour, minute and second from the RTC chip and the millisecond and microsecond from the time counter. In this case, the controllers would have 1 second to synchronize their RTC chips. In most systems, one second is a sufficient amount of time within which to have each controller synchronize their RTC chip.
  • the real time clock - a combination of the value read from the RTC chip and the time counter within the hardware controller ⁇ may be simultaneously used by hardware as a run-time clock and used by software to time stamp events.
  • the central or distributed controller that detected the event or the controller responsible for logging the event reads the time from both the RTC chip and the time counter - in less than 125 microseconds— and stores the time as the time stamp for the logged event.
  • the high resolution time synchronization across the distributed processing computer system insures that the time stamps logged with each event are accurate across the entire system.
  • the time counter may be used in combination with software managed extensions.
  • the year, month, day, hour and second may be stored and updated by software based on the time counter.
  • software increments the higher order values.
  • the RTC chip is used at powerup and/or on synchronization to initialize the higher order values stored in software.
  • the synchronization set up command may be sent across hardware controlled communication bus 33.
  • the synchronization set up command and synchronization time may take more time and effort to establish through the hardware controlled communication bus (e.g., I 2 C bus) since the I 2 C bus is a two serial line bus and commands are only eight bits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne la synchronisation temporelle d'un système (10) de traitement réparti, mise en oeuvre par l'envoi d'une commande d'établissement de synchronisation sur un premier bus (72) et l'envoi d'une commande d'exécution de synchronisation sur un second bus (80). Une horloge (56) de référence de système réparti permet de synchroniser des organes de commande central (14) et répartis (38) sur le même signal d'horloge. La synchronisation est établie par l'intermédiaire d'un bus de communication (32) commandé par logiciel, et la synchronisation réelle est exécutée par le biais d'un bus de communication (33) commandé par matériel. L'utilisation d'un bus de communication (33) commandé par matériel permet d'obtenir la synchronisation immédiate d'une horloge en temps réel haute résolution, et la synchronisation retardée d'une horloge en temps réel de résolution inférieure.
PCT/US2001/015945 2000-05-20 2001-05-16 Synchronisation temporelle dans un systeme de traitement reparti WO2001090865A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001261711A AU2001261711A1 (en) 2000-05-20 2001-05-16 Time synchronization within a distributed processing system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/574,341 2000-05-20
US09/574,343 2000-05-20
US09/574,343 US6639910B1 (en) 2000-05-20 2000-05-20 Functional separation of internal and external controls in network devices
US09/574,341 US7062642B1 (en) 2000-05-20 2000-05-20 Policy based provisioning of network device resources

Publications (1)

Publication Number Publication Date
WO2001090865A1 true WO2001090865A1 (fr) 2001-11-29

Family

ID=27076362

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/015945 WO2001090865A1 (fr) 2000-05-20 2001-05-16 Synchronisation temporelle dans un systeme de traitement reparti

Country Status (2)

Country Link
AU (1) AU2001261711A1 (fr)
WO (1) WO2001090865A1 (fr)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1027147C2 (nl) * 2004-06-02 2007-01-08 Intel Corp Pakketuitwisseling voor het besturen van vermogensprocedures van een systeem.
WO2008013744A2 (fr) 2006-07-27 2008-01-31 Cisco Technology, Inc. Compteurs d'horodatage distribués cohérents
EP1986071A2 (fr) 2007-04-24 2008-10-29 Schneider Electric Industries SAS Système et méthode pour gérer le temps dans un équipement d'automatisme
CN103345237A (zh) * 2013-07-29 2013-10-09 浙江中控技术股份有限公司 实时数据时间标签的调整方法、上位机及分散控制系统
CN104486319A (zh) * 2014-12-09 2015-04-01 上海爱数软件有限公司 适用于高可用系统的配置文件实时同步方法及其系统
US9244323B2 (en) 2009-12-18 2016-01-26 Semiconductor Energy Laboratory Co., Ltd Liquid crystal display device and electronic device
CN112558685A (zh) * 2020-12-11 2021-03-26 南京四方亿能电力自动化有限公司 一种配电终端模块间对时同步的方法
CN112602031A (zh) * 2018-06-26 2021-04-02 北欧半导体公司 系统间的精确定时
CN112947678A (zh) * 2021-02-09 2021-06-11 南方电网科学研究院有限责任公司 一种SoC双核系统时钟同步方法及装置
FR3106674A1 (fr) * 2020-01-23 2021-07-30 Thales Procede de synchronisation temporelle entre une carte mere et une carte fille
CN113271169A (zh) * 2021-04-27 2021-08-17 东风汽车集团股份有限公司 基于无线通信终端的车辆授时方法及系统
US12073254B2 (en) 2020-02-20 2024-08-27 Analog Devices International Unlimited Company Real time sense and control using embedded instruction timing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530846A (en) * 1993-12-29 1996-06-25 International Business Machines Corporation System for decoupling clock amortization from clock synchronization
US5715438A (en) * 1995-07-19 1998-02-03 International Business Machines Corporation System and method for providing time base adjustment
US5826066A (en) * 1996-08-08 1998-10-20 Tandem Computers Incorporated Method for keeping accurate time in a computer system
US5907685A (en) * 1995-08-04 1999-05-25 Microsoft Corporation System and method for synchronizing clocks in distributed computer nodes
US6266625B1 (en) * 1999-01-29 2001-07-24 International Business Machines Corporation Calibrating high resolution measurements

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530846A (en) * 1993-12-29 1996-06-25 International Business Machines Corporation System for decoupling clock amortization from clock synchronization
US5715438A (en) * 1995-07-19 1998-02-03 International Business Machines Corporation System and method for providing time base adjustment
US5907685A (en) * 1995-08-04 1999-05-25 Microsoft Corporation System and method for synchronizing clocks in distributed computer nodes
US5826066A (en) * 1996-08-08 1998-10-20 Tandem Computers Incorporated Method for keeping accurate time in a computer system
US6266625B1 (en) * 1999-01-29 2001-07-24 International Business Machines Corporation Calibrating high resolution measurements

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1027147C2 (nl) * 2004-06-02 2007-01-08 Intel Corp Pakketuitwisseling voor het besturen van vermogensprocedures van een systeem.
WO2008013744A2 (fr) 2006-07-27 2008-01-31 Cisco Technology, Inc. Compteurs d'horodatage distribués cohérents
EP2047619A2 (fr) * 2006-07-27 2009-04-15 Cisco Technology, Inc. Compteurs d'horodatage distribués cohérents
EP2047619A4 (fr) * 2006-07-27 2012-06-13 Cisco Tech Inc Compteurs d'horodatage distribués cohérents
EP1986071A2 (fr) 2007-04-24 2008-10-29 Schneider Electric Industries SAS Système et méthode pour gérer le temps dans un équipement d'automatisme
FR2915589A1 (fr) * 2007-04-24 2008-10-31 Schneider Electric Ind Sas Systeme et methode pour gerer le temps dans un equipement d'automatisme
EP1986071A3 (fr) * 2007-04-24 2009-09-23 Schneider Electric Industries SAS Système et méthode pour gérer le temps dans un équipement d'automatisme
US7983115B2 (en) 2007-04-24 2011-07-19 Schneider Electric Industries Sas System and method for managing time in automatic control equipment
US9620525B2 (en) 2009-12-18 2017-04-11 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
US11282864B2 (en) 2009-12-18 2022-03-22 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
US9244323B2 (en) 2009-12-18 2016-01-26 Semiconductor Energy Laboratory Co., Ltd Liquid crystal display device and electronic device
US11798952B2 (en) 2009-12-18 2023-10-24 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
US10256254B2 (en) 2009-12-18 2019-04-09 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
CN103345237B (zh) * 2013-07-29 2015-11-18 浙江中控技术股份有限公司 实时数据时间标签的调整方法、上位机及分散控制系统
CN103345237A (zh) * 2013-07-29 2013-10-09 浙江中控技术股份有限公司 实时数据时间标签的调整方法、上位机及分散控制系统
CN104486319B (zh) * 2014-12-09 2018-06-19 上海爱数信息技术股份有限公司 适用于高可用系统的配置文件实时同步方法及其系统
CN104486319A (zh) * 2014-12-09 2015-04-01 上海爱数软件有限公司 适用于高可用系统的配置文件实时同步方法及其系统
CN112602031A (zh) * 2018-06-26 2021-04-02 北欧半导体公司 系统间的精确定时
CN112602031B (zh) * 2018-06-26 2024-05-17 北欧半导体公司 系统间的精确定时
FR3106674A1 (fr) * 2020-01-23 2021-07-30 Thales Procede de synchronisation temporelle entre une carte mere et une carte fille
US12073254B2 (en) 2020-02-20 2024-08-27 Analog Devices International Unlimited Company Real time sense and control using embedded instruction timing
CN112558685A (zh) * 2020-12-11 2021-03-26 南京四方亿能电力自动化有限公司 一种配电终端模块间对时同步的方法
CN112558685B (zh) * 2020-12-11 2024-05-10 南京四方亿能电力自动化有限公司 一种配电终端模块间对时同步的方法
CN112947678A (zh) * 2021-02-09 2021-06-11 南方电网科学研究院有限责任公司 一种SoC双核系统时钟同步方法及装置
CN113271169A (zh) * 2021-04-27 2021-08-17 东风汽车集团股份有限公司 基于无线通信终端的车辆授时方法及系统

Also Published As

Publication number Publication date
AU2001261711A1 (en) 2001-12-03

Similar Documents

Publication Publication Date Title
US7451339B2 (en) Pulse-per-second attachment for STP
US9916113B2 (en) System and method for mirroring data
WO2001090865A1 (fr) Synchronisation temporelle dans un systeme de traitement reparti
Fetzer Perfect failure detection in timed asynchronous systems
US7761726B2 (en) Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer
EP2147382B1 (fr) Procédé et système de réduction de la latence de déclenchement dans une acquisition de données de bus série universel
JP2002517819A (ja) 耐障害性演算用の冗長コンピュータ・ベース・システムを管理するための方法及び装置
US9298523B2 (en) Method and system for time synchronization among systems using parallel sysplex links
US20040049706A1 (en) Systems and methods for synchronizing time stamps
US10169171B2 (en) Method and apparatus for enabling temporal alignment of debug information
CN103458036A (zh) 一种集群文件系统的访问装置和方法
CN102752065A (zh) 一种时间同步方法及系统
US10530562B2 (en) Correlating local time counts of first and second integrated circuits
EP2975517B1 (fr) Procédé et dispositif d'exécution synchronisée d'une application dans un environnement à haute disponibilité
CN111506156B (zh) 一种处理器阵列的授时方法及系统
US8055801B2 (en) Pulse-per-second attachment for STP
Smith Jr et al. Development and evaluation of a fault-tolerant multiprocessor (FTMP) computer. Volume 1: FTMP principles of operation
US12019466B2 (en) Virtual precision time protocol clock devices for virtual nodes
Ermoline et al. LHCb Level-1 vertex topology trigger
Smith et al. Development and evaluation of a fault-tolerant multiprocessor (FTMP) computer
KR20000041926A (ko) 아이피씨 시스템에서 특정 프로세서에 대한 재시동장치 및방법
Memo EVLA Correlator Monitor and Control System, Test Software, and Backend Software Requirements and Design Concepts
CN110825596A (zh) 具有分布式时钟的集成电路的高效性能监控
Peuhkuri et al. Clock synchronisation in industry-standard computer hardware
JPH08137711A (ja) Ｒａｓ機構

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP