WO2001084755A1 - Subscriber transmission system, relay transmission device and subscriber transmission device - Google Patents

Abstract

Information about time slot allocation data of channel signals transmitted through relay lines (4-i;i=1 to N) connected to a subscriber transmission device (2) is integrally managed by a time slot management section (323) of a relay transmission device (3). According to the information, a time slot common control section (324) of the relay transmission device (3) controls the time slot allocation for each relay line (4-i) commonly to the relay lines (4-i), thus adapting the system to any of different line connection modes and line switching modes without changing the basic architecture of the existing subscriber transmission device (2).

Description

 Description Subscriber transmission system and

 Relay transmission equipment and subscriber transmission equipment

 The present invention relates to a subscriber transmission system, a relay transmission device, and a subscriber transmission device, for example, a North American communication requiring signal relay at DS1 (Digital Signal level 1) signal level and line switching. Subscriber transmission suitable for use in networks

 , And a relay transmission device and a subscriber transmission device. Background art

 (1) Description of existing optical communication network

 FIG. 20 is a block diagram showing an example of an existing optical communication network. The optical communication network 100 shown in FIG. 20 includes an exchange (digital switch) 10 la and an optical multiplexing / demultiplexing unit (optical MUX / DMUX) 1. 01 Central office (CO: Central Office) with 1 b, etc., and multiple subscriber terminals (telephone terminals, personal computers, etc.) in remote subscriber communities. Each of them has an appropriate number of remote transmission devices (RT: Remote Terminal) 102 that can accommodate 3-N through the subscriber line (metallic line) 13 0-1 through 13 0-N, respectively. The central station 101 and each remote transmission device 102 are connected to each other via a large-capacity optical network (ring network in FIG. 20) 104 such as a SONET (Synchronous Optical Network). The remote transmission device 102 belongs to a subscriber transmission system called a digital loop carrier (DLC) system.

In such an optical communication network 100, a digital signal in the downlink direction for the subscriber terminal 103-i (i = 1 to N) [for example, DS0 (Digital Signal level-0); 64 kbps ) Is, for example, an optical signal after being subjected to exchange processing in the exchange 101a. Multiplexed by the optical multiplexing / demultiplexing unit 101b for multiple channels, and converted into a large-capacity optical network as an optical signal such as OC-3 (Optical Carrier level-3) or {C_12}. Sent to the task 104.

 When this optical signal is received by the target remote transmission device 102, the remote transmission device 102 terminates the received optical signal and finally separates it into a plurality of DS0 data (channel signals). After that, cross-connect processing is performed, and a channel signal to the intended subscriber terminal 103-i is extracted and transmitted to the subscriber terminals 103-1-1 to 103-N. That is, the remote transmission device 102 distributes the multiplexed signal from the central station 101 as a higher-level device to the subscriber terminals 103-1--1: L03_N.

 Conversely, an upstream signal (such as a DS0 or DS0-based analog signal) transmitted from the subscriber terminal 103-i is transmitted to another subscriber terminal 103-i at the remote transmission device 102. After being time-division multiplexed with the DS0 data from the network and subjected to cross-connect processing, it is multiplexed with the optical signal addressed to the central station 101 of the OC-3 or 〇C112 and the backbone network 104 Sent to

 The central office 101 finally separates the DS0 data from the optical signal received from the remote transmission device 102 in the optical multiplexing / demultiplexing unit 101b, and then uses the switch 101a to switch the DS0 data. The exchange process of the place is performed.

 As described above, in the existing optical communication network 100, by providing the remote transmission device 102 near a certain subscriber settlement, the optical transmission from the central office 101 to the remote transmission device 102 is performed by optical signals. Signal transmission, and it is possible to provide the desired high-speed communication service to the subscriber terminal 103-i of the subscriber community located in an area away from the central office 101. is there.

 (2) Detailed explanation of remote transmission equipment

Next, details of the remote transmission device 102 will be described. For example, as shown in FIG. 21, the cross-connect unit 111, the demultiplexer (MUX / DEMUX) unit 112, A backboard 110 having a knockport bus 114 and the like, and a channel slot provided in the backport 110 can communicate with the backport 110 via the backport bus 114. Multiple channels for DS 0 1-D shelf (service card; channel unit) 1 1 3—1 to: L 1 3—N and a shelf (common shelf) 102 A with N are provided.

 Here, the above-mentioned cross-connect unit 111 is for performing cross-connect processing (time slot exchange) in DS0 units by a time switch (T-SW) 111a, for example. The unit 112 multiplexes the DS0 data cross-processed by the cross-connect unit 111 in a time-division multiplexed manner and sends it to the backboard bus 114, while the unit 111 receives the data from the backboard bus 114. This is for separating the DS0 time-division multiplexed signal into each DS0 demultiplexer and sending it to the cross connect unit 111. For this purpose, a multi-Z demultiplexer (MUX / DEMUX) 1 1 2a And a backboard interface 112b having a buffer (not shown) for temporarily holding the DS0 time-division multiplexed signal.

 In addition, each channel card 113-i receives the DSO data addressed to its own subscriber terminal 103-i from the DS0 time-division multiplexed signal stream (time slot group) on the backboard bus 114, respectively. (Time slot data), and the signal transmitted from the subscriber terminal 103 — i is converted into DS 0 data at a predetermined time slot of the DS 0 time-division multiplexed signal stream on the backboard bus 114. It is for entering. In addition, 1 DS0 data is allocated to one time slot on the knock board bus 114.

 Therefore, as shown in FIG. 21, each channel card 113-i has a time slot position adjusting / extracting circuit 115, a line interface circuit 116, and a buffer circuit 117, respectively. a, 117 b are provided, and the access timing (access time slot position) to the backboard bus 114 determined by the time slot position adjustment and extraction circuit 115 is on the back board bus 114. The extraction Z insertion processing of the DS0 data is performed on the DS0 time-division multiplexed signal stream.

Specifically, the time slot position adjustment and extraction circuit 115 described above uses the slot board data # i specific to the mounting slot for the back board 110 of the own channel card 113_i as the back board 111 By acquiring from your own channel The card 1 1 3—recognizes in which slot the i is installed, and determines which time slot on the back board bus 1 14 is to be accessed accordingly, and determines the time slot position. By setting the output of the buffer circuit 1 17a in the up direction to a conductive state by the bus arbitration signal 1 18 and transmitting the DS0 data from the line interface circuit 1 16 to the back board bus 1 1 4 By inserting the DS0 data and the time slot data on the backboard bus 114 stored in the downstream buffer circuit 117b, the self-accommodating from the backboard bus 114 is obtained. It extracts downstream DS0 data addressed to subscriber terminal 103-i.

 Here, the above slot address data #i is, for example, a bit “1” for opening a connection pin with a channel card 1 13 3—i provided on the knock board 20 and a bit “0” for ground. In this case, by changing the open Z ground arrangement for each slot, data of a different bit arrangement can be obtained for each slot.

 Note that the above time slot position adjustment and extraction circuit 115 recognizes (determines) the time that has been recognized (determined) in order to prevent contention of the access time slot of each channel card 113_i with the backboard bus 114. At the time slot position other than the slot, the output of the buffer circuit 1 17a in the upstream direction is masked by the bus arbitration signal 1 18 so that the DS 0 data is not transmitted to the back board bus 1 14 .

 In addition, the line-in interface circuit 1 16 of each of the above-mentioned channel cards 1 1 3—i takes an interface between the channel card 1 1 3—i and the subscriber line 1 3 0—i. For example, an impedance matching circuit for impedance matching with the subscriber line 130-i and a signaling processing circuit for processing signaling for establishing a communication path are provided. Subscriber line 1 3 0—If i is an analog line, a digital Z-to-analog (DZA) converter to convert DS0 data into an analog signal, or to convert an analog signal to DS0 data A / D converters are also provided.

Hereinafter, the operation of the remote transmission device 102 configured as described above will be described. First, the DS0 data for the subscriber terminal 103-i (downstream direction) is cross-connected. After cross-connect processing and time slot exchange are performed by the unit 111 (time switch 11 la), time-division multiplexing is performed in the demultiplexing unit 111 (multi-Z demultiplexer 111a). Sent out on the backboard bus 114.

 At this time, in each of the channel cards 1 13 3—i, the time slot position adjustment / extraction circuit 1 15 is mounted on the back board 110 by the slot address data notified from the back board 110 as described above. By recognizing the (slot position), it knows which time slot on the backboard bus 114 is to be accessed, and the self-contained subscriber terminal 103 assigned to that time slot. Extract DS 0 data for i.

 The DS0 data extracted from the backboard bus 114 by the time slot position adjusting / extracting circuit 115 in this way is then converted to the subscriber terminal 110 by the line interface circuit 116. After being converted into a format signal conforming to the user interface on the 3-i side, it is transmitted to the subscriber terminal 103-i via the subscriber line 1301-i.

 On the other hand, the signal transmitted from the subscriber terminal 103 is transmitted to the central station 101 through processing reverse to the above-described processing in the downward direction. That is, the signal from the subscriber terminal 103 is first converted to DS0 data by the corresponding line card interface circuit 113 of the corresponding channel card 113-i, and then converted to the time slot position. Adjustment · Extraction circuit Input to 1 1 5 The time slot position adjustment / extraction circuit 115 controls the output of the upstream buffer circuit 117 a at the timing of the determined time slot position to be in a transparent state by the bus arbitration signal 118 so that the back board bus The DS0 data received from the line interface circuit 116 is inserted into a predetermined time slot position on 114.

After that, the DS0 data is input to the demultiplexing unit 112 from the backboard bus 114 along with the DS0 data inserted from each of the other channel cards 133-0—i, and is input to the multi-Z demultiplexer 112a. After time-division multiplexing, the cross-connect unit (time slot exchange) is applied in the cross-connect unit 111, and finally, as an optical signal such as 〇C_3 or OC-12, the backbone network 1 0 Sent to 4.

 Incidentally, the optical communication network 100 as described above has been put to practical use in, for example, North America, but can be covered by one subscriber transmission device 102 (master shelf 102 A). There is a limit in the area.In other words, if the subscriber line 130_i is a metallic line, if it is extended beyond a certain distance, it will be susceptible to noise, etc. When subscriber communities are scattered in such a vast area, it is necessary to newly lay an optical fiber and a subscriber transmission device 102 to the subscriber communities.

 However, in this case, enormous costs and labor are required to cover even a relatively small number of subscriber communities as a service target.

 Therefore, by enabling relay transmission with a digital (metallic) line (for example, DS1 line) from the existing subscriber transmission device 102 to the new subscriber settlement to be newly covered, new transmission is possible. It is desired to be able to cover the subscriber's settlement without laying the optical fiber and the subscriber transmission device 102 in the system. At this time, if a major change in the basic equipment configuration (basic architecture) of the existing subscriber transmission equipment 102 is required, it is necessary to develop a new subscriber transmission equipment 102. Therefore, it is necessary to keep the basic architecture of the existing subscriber transmission device 102 as unchanged as possible.

 The present invention has been devised in view of such problems, and can cope with various line connection modes and line switching modes without changing the basic architecture of an existing master shelf (subscriber transmission apparatus). It is an object of the present invention to provide a subscriber transmission system, a relay transmission device, and a subscriber transmission device at low cost. Disclosure of the invention

In order to achieve the above object, a subscriber transmission system of the present invention includes a subscriber transmission device, a relay transmission device capable of accommodating a plurality of subscriber terminals, and a subscriber transmission device. In addition to providing a plurality of relay lines interposed between the relay device and the relay transmission device, the time of the channel signal transmitted through each of the above relay lines is provided to the relay transmission device. A time slot management unit that collectively manages information related to lot allocation, and a time slot common control that controls the time slot allocation for each of the above trunk lines in common to each of the trunk lines based on the information managed by the time slot management unit. And a unit is provided.

 In the subscriber transmission system of the present invention configured as described above, the time slot control unit of the relay transmission apparatus commonly controls the time slot allocation of the subscriber terminal channel signal to an arbitrary relay line. Line switching independent of the number of relay lines and line switching mode can be realized without changing the basic architecture on the device side.

 Therefore, it is possible to provide a subscriber transmission system corresponding to various trunk line connection modes and line switching modes at extremely low cost.

 Here, the above-mentioned subscriber transmission apparatus has a plurality of channel units for interfacing each of the above-mentioned trunk lines, and each of these channel units stores information on the accommodation slot position, respectively. An accommodation slot position information transmitting unit for transmitting to the relay transmission device via the relay line is provided, and the time slot management unit of the relay transmission device is configured to transmit the time slot information of each channel unit. It may be configured to collectively manage the information on the accommodation slot positions sent from the PC.

 In this way, the accommodation position of each channel unit on the subscriber transmission device side can be managed collectively without providing a dedicated line for transmitting information on the accommodation position of each channel unit. The common control of the time slot allocation by the time slot common control unit can be easily realized.

 Therefore, the above line switching can be realized without changing the basic architecture of the subscriber transmission device side and without complicating the system configuration.

 Further, the time slot common control unit in the above-mentioned relay transmission device is configured to assign the above-mentioned time so as to allocate a subscriber terminal channel signal allocated to a certain time slot on a certain relay line to a time slot on another relay line. A time slot changing unit that can change the slot assignment may be provided.

As a result, a subscriber terminal channel signal transmitted through a certain trunk line is transmitted to the subscriber terminal. Since transmission can be performed on an arbitrary trunk line in units of terminal channel signals, for example, a subscriber channel signal on the trunk line on which an alarm has occurred can be transmitted on another trunk line.

 Therefore, 1: 1 line switching, 1: N line switching, line switching based on priority, and the like can be realized, and the degree of freedom in line switching can be increased. Also, since the above-described line switching is controlled from the relay transmission device, the subscriber transmission device does not need to be aware of the connection even if a plurality of the relay transmission devices are connected. That is, it is possible to connect a plurality of the above-mentioned relay transmission devices to the subscriber transmission device without changing the basic architecture of the subscriber transmission device. Further, for the same reason, in the subscriber transmission device, a desired communication service device is connected via a line other than the above-mentioned relay line, and the relay transmission device and the desired communication service device are mixed. Even in the connected state, there is no need to be aware of this, so that the relay transmission device and the desired communication service device can be mixed together without changing the basic architecture of the subscriber transmission device. It is possible to connect to a transmission device.

 In other words, at least one relay transmission device for accommodating a plurality of subscriber terminals constituting the first subscriber terminal group, multiplexing and outputting signals from these subscriber terminals, and this relay transmission device And a plurality of subscriber terminals forming the second subscriber terminal group, and a subscriber transmission device for multiplexing signals from these subscriber terminals and the relay transmission device and outputting the multiplexed signal to the higher-level device. It is possible to construct a subscriber transmission system that includes BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a block diagram showing a configuration of a DLC (subscriber transmission) system as one embodiment of the present invention.

 FIG. 2 is a block diagram showing a detailed configuration focusing on a portion from the backboard bus in the master shelf to the main signal bus in the slave shelf shown in FIG. FIG. 3 is a diagram for explaining the DS1 format.

FIG. 4 is a diagram for explaining a DS1 multi-frame format. FIG. 5 is a diagram for explaining the operation of the DLC system shown in FIG. 1 (operation when a DS1 channel card is mounted).

 FIG. 6 is a diagram for explaining the operation (transparent time slot indication operation) of the DLC system shown in FIG.

 7 (A) to 7 (G) are time charts for explaining the time slot arrangement on the backboard bus in the mass storage shelf shown in FIG. 8 (A) to 8 (G) are time charts for explaining the time slot arrangement on the main signal bus in the slave shelf shown in FIG.

 FIG. 9 is a block diagram for explaining the protection line setting between the master shelf and the slave shelf.

 FIGS. 10 (A) to 10 (G) are time charts for explaining the time slot arrangement (when protection is set) on the back-up bus in the mass storage shelf shown in FIG. .

 Figures 11 (A) to 11 (G) are time charts for explaining the time slot arrangement (when protection is set) on the main signal bus in the slave shelf shown in Fig. 1. .

 FIG. 12 is a block diagram for explaining a work circuit that has been disconnected between the master shelf and the slave shelf.

 Fig. 13 is a diagram for explaining the operation of the DLC system shown in Fig. 1 (operation when the DS1 line disconnection is detected).

 FIGS. 14 (A) to 14 (G) are time charts for explaining the operation of the DLC system shown in FIG. 1 (time slot switching operation on the master shelf).

 FIGS. 15 (A) to 15 (G) are time charts for explaining the operation of the DLC system shown in FIG. 1 (time slot switching operation on the slave shell side).

FIG. 16 is a block diagram for explaining a 1: 1 DS 1 line switching mode. FIG. 17 is a block diagram for explaining a DS 1 line switching mode with priority. FIG. 18 is a block diagram showing a configuration in a case where a plurality of slave shelves shown in FIG. 1 are accommodated in a master shelf.

 FIG. 19 is a block diagram showing a mixed accommodating configuration of channel forces in the master shelf shown in FIG.

 FIG. 20 is a block diagram showing an example of an existing DLC system.

 FIG. 21 is a block diagram showing the configuration of the remote transmission device (R T) shown in FIG. FIG. 22 is a block diagram for explaining a DS1 line connection / switching mode between the master shell and the slave shelf.

 FIG. 23 is a block diagram illustrating a configuration example of an optical network according to an embodiment of the present invention.

 FIG. 24 is a block diagram illustrating a configuration example of an optical network according to an embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

 As described above, when it is desired to newly cover a subscriber settlement existing in an area that exceeds the extendable distance of the metallic circuit 130-i from the existing subscriber transmission equipment 102, as shown in Figure 23 Various configurations are conceivable. That is, the relay transmission device 105 (slave shelf 3) is connected to the subscriber transmission device 102 (master-shelf 2) by a digital (metallic) line (for example, a DS1 line). By connecting with 4-N (N is a natural number), the subscriber terminals 6-1 to 6-M (M is a natural number) of the subscriber settlement 6 are covered as services.

 In the following, for convenience of explanation, is assumed that the above-mentioned subscriber transmission device 102 and the master shelf 2 are equivalent, and that the relay transmission device 105 and the slave shelf 3 are equivalent. The transmission device 102 may be referred to as a subscriber transmission device 2, or the relay transmission device 105 may be referred to as a relay transmission device 3.

However, the number of DS1 lines between shelves and the presence or absence of DS1 line switching (the presence or absence of FACILITY PROTECTION) vary depending on the line capacity, line importance, and other factors in the connection between the shelves 2 and 3 described above. Also, multiple units on one unit When the slave shelves 3 are connected, a situation may occur in which the connection form differs for each slave shelves 3.

 For example, as shown in Fig. 22, between the master shelf 2 and the slave shelf 3 (# 1), two of the three DS 1 lines 4-1 to 4-3 are active (work) and the rest are One is used as protection (protection), 2: 1 DS 1 line switching mode, one work line 4-1 is provided between master shelf 2 and slave shelf 3 (# 2) Non-line switching mode, multiple types of connections between the master one shelf 2 and the slave shelf 3 (# 3), such as a non-line switching mode with two work lines 4-5, 4-6 Forms exist.

 In order to cope with such a difference in the connection mode, the function of controlling the number of DS 1 lines, the presence or absence of DS 1 line switching, and the type of DS 1 line switching when there is a DS 1 line switching, etc. on the side of the shelf 1 This has to be done, but this is very costly, as the architecture of the mass storage shelf 2 has to be changed significantly.

 Therefore, in the present embodiment, a configuration as shown in FIG. 1 is adopted. That is, FIG. 1 is a block diagram showing a configuration of a DLC (subscriber system) system as an embodiment of the present invention. The DLC system 1 shown in FIG. DS 1 line (metallic line) as a relay line to mass storage 1 shelf 2 (slave (service)) connected via 4 1 1 to 4 1 N and subscriber line (metallic line) to this slave shelf 3 5—1 to 5—Subscriber terminals such as telephone terminals and personal computers housed through M 6— :! It is configured with ~ 6_M.

The master shelf 2 includes a backboard 20 (a cross-connect unit 21 with a time switch 211, a multi-Z demultiplexer 221, and a Multiplexing / demultiplexing units 1 1 2 and knock board bus 2 4) with backboard interface 2 2 2, and channel slots provided in this back port 20 are mounted on DS 1 line 4-i, respectively. (However, multiple channel cards for DS 1 (channel unit) for taking in-face with i = l ~ N) ~ 23-N. On the other hand, as shown in FIG. 1, the slave shelf 3 has a DS1 channel card (hereinafter also referred to as a master channel card) 23-i on the master shelf 2 side via the 031 line 4-1. The connected DS 1 channel card (hereinafter also referred to as the slave channel card) 3 1—1 to 3 1—N and the master control card 32 1—i common to each of these master channel cards 3 1—i , Respectively, a DS0 channel card 33-1 to 33-M for interfacing with the subscriber terminal 6_j (subscriber line 5—j; j = 1 to M), a main signal bus 34, and a control bus 35 are provided.

 FIG. 2 is a block diagram showing a detailed configuration focusing on a portion from the back board bus 24 in the master shelf 2 to the main signal bus 34 in the slave shelf 3. The above relationship between N and M is based on the signal speed (bit rate; that is, each subscriber line 5—) handled by each subscriber terminal 6-j (where j = 1 to M) accommodated by the slave shelf 3. j line speed). For example, assuming that the line speed of each subscriber line 5—j is 64 kbps (kilobits Z seconds) based on DS0, a DS1 line with a line speed of approximately 1.544 Mbps (megabits / second) per line 4-i (where i == l ~ N), it is possible to transmit up to 24 channels of DS0 data (subscriber terminal channel signals). Become.

In other words, the DS1 channel card 3 1—i on the slave shelf 3 side has a maximum of 24 subscriber lines (channels) per node 5—DS 0 data on j (that is, the DS 0 channel card). The interface 33-j interfaces the 24 cards worth of DS0 data) to the DS1 line 4-i. Specifically, the DS 1 handled in the present embodiment has a format as shown in FIG. 3, for example. In other words, one period of master clock 10 in each shelf 2 and 3 [1Z 1.544 (MHz) = 648 ns (nanosecond)] is defined as one time slot (= 8 bits = 1 knot) 11 In this case, DS0 data for 24 time slots (channels) and framing byte (sync byte) F for one time slot constitute 1 DS1 frame 12 and this DS1 frame 12 is collected into 24 frames. In addition, an IDS 1 multiframe 13 is configured, and a signal having such a configuration is formed. The signal is transmitted on each DS 1 line 4-i.

 Figure 4 shows the details of the multi-frame structure. However, in FIG. 4, "FPS" is a frame synchronization pattern signal, "DL" is a data link signal, "CRC" is a CRC (Cyclic Redundancy Check) code, and "VF signal" is one time slot. "SIG" is inserted in one time slot, and the "SIG bit" is inserted in that bit position. Indicates a value.

 In other words, from FIG. 4, the 1 DS1 multiframe 13 contains the frame synchronization pattern signal for every 4 DS1 frame 12 from the beginning, the data link signal for every 2 DS1 frame 12, and the 2 DS from the beginning. From the first frame onwards, CRC code is inserted every 4 DS 1 frame 1 and 2 and signaling using LSB (Least Significant Bit; 8th bit) of 1 time slot 11 every 6 DS 1 frame 12 from the beginning It can be seen that bits are inserted.

 Next, details of each component in the master shelf 2 and the slave shelf 3 will be described.

 First, in the master shelf 2 shown in FIG. 2, the above-mentioned DS 1 channel card 23 1-i is basically the DS 0 channel card 1 13 _ i described above with reference to FIG. In a specific time slot position on the backboard bus 24 assigned according to the self-contained slot position, the DS0 data for the subscriber terminal 6—j from the backboard bus 24 (For 24 channels), while inserting DS0 data (for 24 channels) from the subscriber terminal 6-j into the backboard bus 24.

For this reason, these DS1 channel cards 23-i have a short slot position adjustment and extraction circuit 231, a DS1 interface circuit 232 and a buffer circuit 2334a, 2 respectively. At the specific time slot position, the time slot position adjustment / extraction circuit 2 3 1 stores the data on the back board bus 24 temporarily stored in the buffer circuit 2 3 4. By taking in, the downstream DS0 data for the subscriber terminal 6—j is extracted from the backboard bus 24, while the bus arbitration buffer circuit 2324a is turned on by the bus arbitration signal 235. Thus, the upstream DS0 data from the DS1 interface circuit 232 is transmitted and inserted into the backboard bus 114.

 Note that the time slot position adjustment / extraction circuit 23 1 arbitrates bus arbitration at time slot positions other than the specific time slot in order to prevent contention of access time slots to the backboard bus 24 for each channel card 23-i. The output of the buffer circuit 234 a is masked by the signal 235 to control not to transmit the time slot data (DSO data) to the back board bus 24. By the way, in the present embodiment, the time slot position adjustment / extraction circuit 231 determines the time slot position at which the back slot 24 is accessed by the time slot position adjustment / extraction circuit 231. Instead, the slave shelf 3 follows the decision of the shelf control unit 32 in the shelf 3. For this purpose, each DS 1 channel card 23-i is provided with a data link control circuit 23 3 as shown in FIG. 2, and the data link control circuit 23 3 By communicating with the data link control circuit 3 13 on the slave shelf 3 side using the data link signal (DL) described above, the transmission time slot information (access time (Slot position information) and notifies the time slot position adjustment / extraction circuit 231 of the instruction to access the backboard bus 24 at the specified time slot position (DS0 data insertion) / Extraction).

 Here, in order for the Shelf control card 32 to generate the above transparent time slot information, the Shelf control card 32 must know the mounting position (accommodation slot position) of each master channel card 23-i. There must be.

Therefore, in the present embodiment, the data link control circuit 23 3 on the master shelf 2 side transmits information (slot address data #i) on the mounting position (accommodation slot position) of the own channel card 23-i on the backboard 2. The slot address data is obtained by inserting the data #i into the data link signal and transmitting it to the data link control circuit 313 on the slave shelf 3 side. Is notified to the shelf control circuit 32 via a channel control circuit 314 and a control bus 35 described later. In other words, the data link control circuit 233 on the master shelf 2 side transmits the information on the accommodation slot position of its own master channel card 2 3 — i to the backboard bus 24 via the DS 1 line 41 i via the slave system. It has a function as a storage slot position information sending unit to send to Elf 3.

 The DS1 interface circuit 232 described above uses the DS0 data for 24 channels extracted from the backboard bus 24 in order to interface with the DS1 circuit 4-i. Functions for assembling into DS1 frames 1 and 2 and decomposing DS1 frames 1 and 2 received from DS1 circuits 4 i into 24 channels of DS0 data, 0 3 1 circuits 4 _ 1 It also has a function to detect faults (signal loss, clock loss, remarkable line quality deterioration, etc.). When such a fault is detected, an alarm signal 236 generates an upstream buffer circuit 234a. By masking the output of, the process of inserting the DS0 data into the backboard bus 24 is stopped (masked).

 Such mask processing is not performed on the downstream buffer circuit 2 3 4 b, but the output of the downstream buffer circuit 3 1 2 a in the slave channel card 3 1-i to be described later is Similarly, masking is performed, so that DS0 data is not transmitted to the subscriber terminal 6—j. The bus arbitration signal 235 is also generated by the data link control circuit 232 when data link communication is abnormal, and the process of inserting the DS0 data into the back board bus 24 is stopped as in the case of detecting a line failure. Is done.

 On the other hand, in the slave shelf 3 shown in FIG. 2, the above-mentioned DS 1 channel card 3 1—i has the same basic functions as the master channel card 2 3—i, and the main signal bus. At a specific time slot position on 34, the DS 0 data (for 24 channels) for the subscriber terminal 6—j is inserted into the main signal bus 34, while the DS from the subscriber terminal 6—j is inserted. This is for extracting 0 days (24 channels) from the main signal bus 34.

For this reason, these DS1 channel cards 31-i also have a short slot position adjustment and extraction circuit 311, a buffer circuit 312a, 312b, and a DS1 interface circuit 315, respectively. On the 3rd side of the slave shelves At the specified time slot position, the time slot position adjustment / extraction circuit 3 1 1 is controlled by the bus arbitration signal 3 16 to control the output of the downstream buffer circuit 3 1 2 a to be in a transparent state. While transmitting the downstream DS0 data sent from the interface circuit 315 and inserting it into the main signal bus 34, the time slot data (temporarily stored in the upstream buffer circuit 312b) By taking in DS0 data, upstream DS0 data is extracted from the main signal bus 34.

 The time slot position adjustment / extraction circuit 311 in each of the slave channel cards 31-i also prevents contention of access time slots for the main signal bus 34 of each channel card 31-i. In the short slot position other than the specific time slot, the bus arbitration signal 3 16

The output of 2a is masked so that time slot data (downstream D S0 data) is not transmitted to the main signal bus 34.

 In this embodiment, the access time slot position (time slot allocation) for the main signal bus 34 is also controlled according to the transparent time slot information generated in the shelf control card 32 in the present embodiment.

 For this purpose, each slave channel card 3 1—i is provided with a channel control circuit 3 14, respectively, and this channel control circuit 3 1 4

It communicates with the shelf controller 3 2 via 3 5, acquires transparent time slot information from the shelf controller 3 2, and transmits the transparent time slot information to the time slot position adjustment / extraction circuit 3 1 1. By notifying, the main signal bus 34 is accessed at the designated time slot position.

The above-mentioned channel control circuit 3 14 also notifies the data link control circuit 3 13 of the transmission time slot information obtained from the shelf control card 32, thereby providing the transmission time As described above, the slot information is also notified to the time slot position adjustment / extraction circuit 2 31 of the master shelf 2 by the overnight link communication between the data link control circuits 3 13 and 2 33 as described above. However, as a result, the access to the backport bus 24 at the time slot position indicated by the above-mentioned transparent time slot information is also performed in the master-shelf 2. You.

 The DS 1 interface circuit 3 15 is used to interface with the DS 1 line 41 i in the same manner as in the master channel card 23-i. The upstream DS0 data for 24 channels extracted from the main signal bus 24 is assembled into the upstream DS1 frame 12 and transmitted to the DS1 line 41-i or received from the DS1 line 4-i. In addition to the function of disassembling the downstream DS 1 frame 1 2 into 24 downstream DS 0 data, the DS 1 line 41 i has a failure (signal loss, clock loss, remarkable line quality deterioration, etc. It also has a function as an alarm detection unit that detects the occurrence of).

 Further, the data link control circuit 3 13 on the slave shelf 3 side described above instructs the channel control circuit 3 13 to generate the bus arbitration signal 3 16 when data link communication is abnormal. The output of the direction buffer circuit 234 a is masked so that the insertion of the downstream DS0 data into the main signal bus 34 is stopped.

 Next, the Shelf control card 32, as shown above, each master one channel card

2 3—i (time slot position adjustment 'extraction circuit 2 3 1) access time slot position to backboard bus 2 4 and main of each slave channel card 3 1-i (time slot position adjustment and extraction circuit 3 1 1) This is for controlling the access time slot position for the signal bus 34, respectively. For this purpose, focusing on the function of the main part, as shown in FIG. It has a unit control circuit 3 2 2.

 Here, the DS 1 switching determination unit 3 2 1 transmits the slot address data # i obtained by each channel control circuit 3 14 by the data link communication described above to the control bus.

In addition to receiving the data via 3 5 and managing them collectively, based on the management data, the access time of each channel and channel card 2 3 — i to the backboard bus 24 and the location of each slave channel card 3 1 — i By determining the position of the access time slot to the main signal bus 34 of each DS, the time slot assignment of the DS0 data to each DS1 line 4-i is determined. In addition, the unit control circuit 3 2 2 determines whether each slave channel card 3 1 -i and each master channel card 2 3 -i according to the time slot allocation determined by the DS 1 switching determination section 3 2 1. This is for generating information about the time slot to be transmitted (transparent time slot information).

 Here, this transparent time slot information is stored in each channel card as described above.

2 3-i, 3 1-The time slot position adjustment / extraction circuit of i is notified to the extraction circuit 2 3 1, 3 1 1, so that the access time slot position for the backport bus 24 on the master shelf 2 and the slave The position of the access time slot to the main signal bus 34 in the elf 3 is controlled, and the time slot allocation of DS0 data to each DS1 line 41i is controlled.

 In other words, the DS1 switching determination section 3 21 described above functions as a time slot management section 3 23 that collectively manages the slot address data #i as information on the time slot allocation to each DS 1 line 4—i. On the basis of the management data, it also has a function as a time slot common control unit 324 that controls the assignment of the time slot to each DS 1 line 41 i in common to each DS 1 line 41 i.

 It should be noted that the DS 1 switching judgment section 3 2 1 (time slot common control section 3 2 4) has detected that a failure (signal loss, clock loss, remarkable line quality deterioration, etc.) has occurred in a certain DS 1 line 41 i. Is detected by the DS1 interface circuit 3 15 on the slave shelf 3 side, the DS 0 data assigned to the time slot on the DS 1 line 4—i where the fault (alarm) occurred However, it also has a function as a time slot changer 3 25 that changes the above time slot allocation so that it can be allocated to an empty time slot other than the DS 1 line 4—i. It is possible to switch DS1 lines in DS0 units when an error occurs.

 Next, in the slave shell 3, each of the DS 0 channel cards 3 3 — j is used to take an interface with the subscriber line 5 — j, and is described above with reference to FIG. 21. Time slot position adjustment-extraction circuit 3 31, line interface circuit circuit 3 32 2, notch circuit 3 3 3 a, 3

It has 3 3 b. Then, at a specific time slot position, the time slot position adjustment and extraction circuit 331 captures the time slot data temporarily stored in the downstream buffer circuit 333 b to obtain the main signal. The downstream DS0 data for the subscriber line 5—j (subscriber terminal 6_j) is extracted from the bus 3 4 and the output of the upstream buffer circuit 3 3 3a is conducted by the bus arbitration signal 3 3 4 By controlling the state, the upstream DS0 data from the subscriber line 5-j (subscriber terminal 6—j) sent from the line interface circuit 3 32 is transmitted, and the main signal bus 3 4 To be inserted into

 Here, the time slot position adjustment / extraction circuit 3 31 in each of the DS 0 channels 3 3 -i described above is also used to avoid contention of the access time slot position with respect to the main signal bus 34 4 except for the specific time slot. At the time slot position, the output of the buffer circuit 33 33 a is masked by the bus arbitration signal 3 16 so that the main signal bus 34 is controlled not to transmit the time slot data (DS 0 data). . However, the position of the access time slot to the main signal bus 34 by each of the DS0 channel cards 33-j is not controlled by the above-mentioned shelf control card 32, but is controlled by FIG. 1, each time slot position adjustment / extraction circuit 331 receiving information (slot address data #) on the mounting position (accommodation slot position) for the main signal bus 34 is determined independently. · Controlled.

 In other words, each DS0 channel card 33_j does not need to be aware of the DS1 line switching by the shelf control card 32 as described above, and the access determined according to the accommodation slot position as usual. By accessing the main signal bus 34 at the time slot position, the desired time slot data (DSO data) can be extracted and inserted.

 Hereinafter, the operation of the DLC system 1 of the present embodiment configured as described above will be described.

(1) DS 1 channel card 2 3 _ i, 3 1— i Explanation of operation when mounting The master shelf 2 and the slave shelf 3 have DS 1 channel cards 23 1 i and 31 1 i, respectively. Once implemented, the first thing to be notified from the knock board 20 The slot address data # i is notified to the data link control circuit 23 3 of the master channel card 23-i (step S 1 in FIG. 5).

 The data link control circuit 2 3 3 converts the received slot address data #i into DS

Output to the one-in-first-off circuit 2 32 (step S 2 in FIG. 5). The DS1 interface circuit 2 32 inserts the slot address data # i input from the data link control circuit 2 32 into the data link signal and transmits the data to the DS 1 line 41 i (see FIG. 5). Step S3).

 On the other hand, the slave shelf 3 extracts the data link signal (slot address data # i) from the DS 1 frame 12 and outputs the data # i to the data link control. Output to circuit 3 13 (step S 4 in FIG. 5). The data link control circuit 3 1 3 receives the slot address data

— Even #i is output to the channel control circuit 3 1 4 (step S 5 in FIG. 5), and the channel control circuit 3 1 4 transmits the slot address data # i to the control channel 3 via the control bus 3 5. Output to 2 (Step S6 in FIG. 5).

 In the case of the shelf control card 32, the DS 1 switching judgment section 3 2 1 is applied to each slot address data # i transmitted by the data link signal from each of the above master channel cards 2 3—i received from the control bus 35. Based on the determination, the time slot allocation for each DS 1 line 4—i is determined, and the unit control circuit 3 2 2 generates the transparent time slot information according to the determination, and controls each slave channel via the control bus 35. The notification is made to the channel control circuit 3 14 of the card 3 1 —i (step S 7 in FIG. 6).

 Upon receiving the transparent time slot information, the channel control circuit 3 14 notifies the time slot position adjustment / extraction circuit 3 11 1 and the data link control circuit 3 13 of the instruction (step in FIG. 6). S8). As a result, the time slot position adjusting / extracting circuit 311 outputs the output of the upstream buffer circuit 312a by the bus arbitration signal 316 at the position (timing) indicated by the transparent time slot information. By controlling the conduction (transmission) state, setting is made so that the upstream DS0 data from the DS1 interface circuit 315 can be transmitted (step S9 in FIG. 6).

On the other hand, the data link control circuit 3 13 receives from the channel control circuit 3 14 The transmitted transparent time slot information is inserted into the data link signal and transmitted to the DS1 circuit 41i (step S10 in FIG. 6). This transparent time slot information is extracted by the DS1 interface circuit 232 of the channel card 23-i and passed through the data link control circuit 233 (step S11 in Fig. 6) to adjust the time slot position. · The extraction circuit 231 is notified.

 As a result, the time slot position adjusting / extracting circuit 231 controls the output of the upward buffer circuit 234a to be in a conductive state by the bus arbitration signal 235 at the time slot position indicated by the transparent time slot information. Thus, the own channel card 23-i is set to be able to transmit the upstream DS0 data sent from the DS1 interface circuit 232 (step S12 in FIG. 6).

 As described above, each of the channel cards 23 _ i, 31 1-i output the DS 0 data (DS 1 frame 1 2) transmitted on the DS 1 line 4-i respectively to the back board 24, the main signal bus 34 And a state in which transmission is possible.

 Here, FIGS. 7 (B) and 7 (C) show examples of time slot assignment on the backboard bus 24, and FIGS. 8 (B) and 8 (C) show examples of time slot assignment on the main signal bus 34. Are respectively shown. 7 (B) and 7 (C) show a case where the number of slots (corresponding to the above-mentioned N) of the main shelf 2 (backboard 20) is 4, and the backboard bus 24 is 2 Two buses (CCS1, CCS2) for the upward direction of the book (the channel card 23—i → backboard 20) and two downward directions (the backboard 20—master channel card 23—i) ) Data buses (XCCR1, XCCR2) for a total of four data buses. Similarly, FIGS. 8 (B) and 8 (C) show the main signal bus 34 as a main signal for two upstream directions (DS0 channel card 33—i—slave channel card 311i). A total of four main signal buses 34 (SXCCR1, SXCCR2) for the bus 34 (SCCS1, SCCS2) and two downstream (slave channel force 3 1—i → DS 0 channel card 33_i) This indicates that the data bus is provided.

As shown in Fig. 7 (B), the master shelf slot number (slotter) is placed on one of the backboard data buses (CCS1 / XCCR1) for the up / down direction. (Dress data) The time slot numbers “1” to “27” (for the mass channel card 23 1 1 and 23-3) for each of ① and ③ are assigned, as shown in Fig. 7 (C). On the other hand, the backboard data bus (CCS2 / XCCR2) for the up and down Z directions has the time slot number (for the master channel card 23-2 and 23-4) for each of the master shelf slot numbers ② and ④. "1" to "27" are assigned.

 Similarly, one of the main signal data buses (SCC1 / SXCCR1) for the up and down Z directions shown in FIG. 8 (B) has (slave channel card 3 1) for each of master shelf slot numbers ① and ③. — Time slots "1" to "27" (for 1 and 3 1 1 3) are assigned to the other main signal de-bus (SCC2 / SXCCR2) for the up and down directions shown in Fig. 8 (C). Are assigned time slots "1" to "27" (for slave channel cards 31-2 and 31-4) for master shelf slot numbers ④ and そ れ ぞ れ, respectively.

 In other words, the time slot position adjustment / extraction circuit 231 of the master channel card 23_i uses the backboard bus shown in FIG. 7 (B) if the slot address data notified from the backboard 20 is an odd slot number ① or ③. (CCS1 / XCCR1) timeslots “①1” to “①-27” and “③-1” to “③-27” are accessed. For even slot numbers ② and 図, Figure 7 (C) The access will be to the backboard bus (CCS2 / XCCR2) time slots "①-1" to "， -27" and "④-1" to "④-1 27" shown in (1).

 Similarly, the time slot position adjusting / extracting circuit 3 1-1 of the slave channel 3-i has the slot address data notified by the data link communication from the master channel card 23-i by the odd slot number ①, If it is ③, access the time slots “①—1” to “①—27” and “③_1” to “③-27” of the main signal bus (SCCS1 / SXCCR1) shown in FIG. For even slot numbers ② and ④, the time slots "© -1" to "②27", "11" to "④27" of the main signal bus (SCCS2 / SXCCR2) shown in Fig. 8 (C) Will be accessed.

However, in both the backboard bus 24 and the main signal bus 34, the time slot in which the DS0 data is actually inserted is as described above when N = 4. As described above, the maximum number of channels that can be accommodated in a DS0 data channel per IDS1 channel card is 24, so the time slot “25” for three channels out of the above time slots “1” to “27” ~ "27" is reserved.

 Note that the pulses 15M and 15S shown in FIGS. 7A and 8A are the master clocks (MCLK, SMCLK: 3.456 MHz) in the master shell 2 and slave shell 3, respectively. , Figures 7 (D) and 8 (D) are enlarged views of one time slot (bit arrangement), respectively, and Figures 7 (E) and 8 (E) are Figures 7 (A) and 8 (A), respectively. ) Show enlarged views of the master clocks 15M and 15S, respectively.

 Also, the pulse 17 M shown in Fig. 7 (F) is a back- board signal in the upstream and downstream directions—multi-frame pulse for evening bus [XMFPS / XMFPE; 1 clock = 3.456 MHz width, 3 ms (millimeters). Second period), the pulse 17S shown in Fig. 8 (F) is a multi-frame pulse for the main signal data bus in the upward direction Z and downward direction (SXMFPS / SXMFPR; 1 clock = 3.546) MHz width, 3 ms cycle), the pulse 18M shown in Fig. 7 (G) is a bus common frame pulse for the backboard bus 24 (SHR1 / 2; 125 S (microsecond) cycle), Fig. 8 (G) The pulse 18S shown in Fig. 8 represents a bus common frame pulse (SSHR1 / 2; 125s) for the main signal bus 34, respectively.

 In other words, within master shelf 2, XI (MCLK) for master clock, X1 for bus common frame pulse (SHR1 / 2), backboard data bus for upstream direction X2 (CCS1, CCS2), downstream There are a total of eight signal lines: a backboard bus for the direction (XCCRl, XCCR2), an XI for the up direction multi-frame pulse (XMFPS), and an X 1 for the down direction multi-frame pulse (XMFPR). .

 Similarly, in slave shelf 3, XI (MCLK) for master clock, X 1 for SSH common frame pulse (SSHR1 / 2), backboard data bus for upstream direction X 2 (SCCS1, SCCS2), There are a total of eight signal lines: a backboard data bus for the down direction (SXCCR1, SXCCR2), an XI for the up direction multi-frame pulse (SXMFPS), and an X 1 for the down direction multi-frame pulse (SXMFPR).

The above multi-frame pulse (XMFPS, XMFPR, SXMFPS, SXMFPR) Are used, for example, to detect the DS1 frame 12 in which the signaling bit (SIG) described above with reference to FIG. 4 is present. Also, Fig. 10 (A) to Fig. 10 (G), Fig. 11 (A) to Fig. 11 (G), Fig. 14 (A) to Fig. 14 (G), Fig. 1 The pulse and time slot assignment (arrangement) shown in Fig. 5 (A) to Fig. 15 (G) are the same as those described above.

 However, Figs. 10 (A) to 10 (G) and Figs. 14 (A) to 14 (G) show the side of the main shelf 2 and Figs. 11 (A) to 11 (G) and FIGS. 15 (A) to 15 (G) show pulse and time slot assignments on the slave shelf 3 side. That is, Figs. 10 (A) to 10 (G) and Figs. 14 (A) to 14 (G) correspond to Figs. 7 (A) to 7 (G), respectively. FIGS. 1 (A) to 11 (G) and FIGS. 15 (A) to 15 (G) correspond to FIGS. 8 (A) to 8 (G), respectively. Next, as described above, time slots are allocated according to the transparent time slot information from the shelf control unit 32, and line switching is performed when a certain DS1 line 41i is disconnected after communication is started. The operation will be described. In this case, for example, as shown in FIG. 4 to 3 are set as working (work) lines, and the remaining DS 1 lines 4 to 4 are set as protection (protection) lines.

 This setting is performed, for example, by transmitting the non-transparent time slot information from the shelf control unit 32 to the master channel 23-4 and the slave channel card 3 by data link communication in the same manner as the transparent time slot information described above. This is performed by notifying the time slot position adjustment 'extraction circuits 23 1 and 3 1 1 of 1-4. That is, the time slot position adjusting / extracting circuits 231 and 311 that have received the above-mentioned non-transparent time slot information do not access the specified time slot and do not transmit the DS 0 It sets the slot to an unused state.

For example, if the time slot allocation is performed as described above with reference to FIGS. 7 (B), 7 (C), 8 (B), and 8 (C), the above non-transparent time slot information The time slot position adjustment and extraction circuits 23 1 and 3 11 1 of the master one channel card 23-4 and slave channel card 31 4 As shown in FIG. 10 (B), FIG. 10 (C), FIG. 11 (B), and FIG. 11 (C), respectively, the time slot “④1” of the backboard bus 24 and the main signal bus 34 is used. It is set not to access "~" 網 -27 "(see the shaded area).

 In this state, for example, it is assumed that the DS 1 line 4-1 which is one of the working lines is disconnected as shown in FIG. Then, this state is detected in the DS1 interface circuit 2 32 of the mass communication channel card 23-1, and the DS1 interface circuit 2 3 2 2 By masking the output of 234a, data transmission to the backboard bus 24 is blocked (non-transparent) (step S13 in FIG. 13).

 As a result, for example, as shown in FIG.

Time board "一 ー 1" ~ "①"

No DS 0 data from the master channel 23-1 will be inserted into -27 ".

 On the other hand, at this time, even in the slave channel card 31-1, the DS1 interface circuit 315 detects the disconnection state of the DS1 line 411, and the DS1 interface circuit 315 issues an alarm. The message is sent to the channel control circuit 314 (step S14 in FIG. 13). Upon receiving this alarm message, the channel control circuit 314 masks the output of the downstream buffer circuit 312a as in the case of the master shelf 2 (step S15 in FIG. 13). Then, the transmission of data to the main signal bus 34 is closed.

 As a result, on the slave shelf 3 side as well, for example, as shown in FIG. 15 (B), the time slot “①1” on the main signal bus 34 (main signal data bus for the upward and downward directions) ~ "①-27" means that DS0 data from slave channel card 31-1 will not be imported. At this time, the above-mentioned channel control circuit 314 also sends the alarm message received from the DS1 interface circuit 315 to the shelf control card 32 via the control bus 35 (see FIG. 13 Step S 16).

Upon receiving the above-mentioned alarm message, the shelf control card 32 sends the data transmitted on the working line 4-1 to the protection line 4-4. It is determined that it is necessary to switch to the time slot “①—1” to “①−27” of the time slot “①—1” to “①−27” transmitted through the working line 4-1. — Generates transmission time slot information for transmission using “1” to “①1 2 7” and notifies the slave channel card 3 1—4 via the control bus 35 first. (Step S 17 in FIG. 13).

 In the slave channel card 3 1-4, when the channel control circuit 3 14 receives the above transparent time slot information, it notifies the time slot position adjusting / extracting circuit 3 1 1 of the transparent time slot information (FIG. 13). At the same time as step S18), the output of the buffer circuit 312a is set to the conductive state (data transmission start state) by the bus arbitration signal 316 (step S19 in Fig. 13).

 As a result, the time slot position adjustment / extraction circuit 311 of the slave channel card 3 1 _ 4 receives the time slot of the main signal bus 3 4 designated by the transparent time slot information received from the channel control circuit 3 1 4 [ Access to the short slots “①—1” to “①—27”] shown in Fig. 14 (B) is possible, and the DS0 data that has passed through the working line 4-1 before the alarm occurs Transmission is performed between the protection line 4-4 and the main signal bus 34 using time slots "-1" to "①-2 7".

 In other words, the time slots are exchanged between the channel cards 31-1 and 31-4, and the working line 411 and the protection line 414 are switched.

 On the other hand, the above-described transparent time slot information is also notified to the data link control circuit 23 of the mass channel card 23-4 through the data link control circuit 31 (see FIG. 1). The data link control circuit 2 3 3 notifies the received transparent time slot information to the time slot position adjustment and extraction circuit 2 3 1 (step S 2 1 in FIG. 13) (step S 2 1 in FIG. 13). The output of the upstream buffer circuit 234a is set to the data transmission start state by the bus arbitration signal 235 (step S22 in FIG. 13).

As a result, the time slot position adjustment / extraction circuit 2 3 1 of the master channel card 2 3 _ 4 is connected to the backboard bus specified by the transparent time slot information. Access to the time slot of time slot 24 [time slot "①—1" to "①1 27" shown in FIG. 15 (B)] becomes possible, and the DS0 data transmitted through the working line 4_1 is transmitted. Evening will be transmitted between backboard bus 24 and protection line 4-4 using time slots "の 間 -1" to "①-2 7".

 In other words, in Master Shelf 2, the channel card 2 3—1, 2

This means that the time slots have been switched between 3 and 4, and the working line 411 and the protection line 414 have been switched.

 As described above, between the master shelves 2 and the slave shelves 3, the DS 0 data transmitted on the working line 4 1 1 becomes transparent on the protection line 4 4 and the DS 1 line switching (time slot switching) is performed. Complete. In addition, other working lines 4-1-2

In the case where any one of 4-1 is disconnected, it is of course possible to switch the DS1 line to the spare line 414 in the same manner as described above. The access operation of each of the DS0 channel cards 33-j to the main signal bus 24 in the slave shelf 3 is as described above.

 As described above, according to the DLC system 1 of the present embodiment, the time slot assignment (replacement) of the DS 0 data for any DS 1 circuit 4 i is performed from the Shelf control card 32 to each DS 1 circuit 4. Since control is performed in common for one i (mass and one channel card 23_i and slave channel card 31-i), DS0 data should be transmitted without changing the basic architecture of the master shelf 2 Switching of DS 1 line 41-i can be realized.

 Further, in the present embodiment, the DS1 switching determination unit 321 of the shelf control card 32 provided on the slave shelf 3 side collectively collects all DS1 line information (time slot assignment of DS0 data). Therefore, it is not necessary to limit the number of DS 1 lines managed by the shelf control cards 32, so that the degree of freedom can be increased. In other words, an increase or decrease in the number of DS1 lines can be handled by changing the number of mounted master channel cards 23-i and slave channels 311-i, providing a highly scalable DLC system 1. be able to.

Further, as described above, the shelf control card 3 2 (DS 1 switching determination section 3 2 1) on the slave shelf 3 side collectively manages the DS 1 line switching operation. If the switching judgment condition (software) in the DS 1 switching judgment section 3 2 1 is changed, in addition to the N: 1 switching as described above, for example, as shown in FIG. A switching of 1: 1 between the lines 4 and 2 or, for example, as shown in FIG. 17, all DS 1 lines 41 i are used as working lines, and a predetermined number is assigned to each working line 4-i in advance. Priorities are set, and when a certain DS1 line 4-1i is turned off for the working line 4-1i (the working line 413 in FIG. 17), the lowest-order working line 4-1i (FIG. In FIG. 7, the working line 4—N) is used as the protection line (the transmission of the originally transmitted time slot DS 0 is stopped, and the working line 41 i which has been disconnected is transmitted instead. Various types of DS 1 line switching, such as prioritized DS 1 line switching. It can be. In other words, the degree of freedom in the DS 1 line switching mode can be increased.

 In addition, the shelf control card 3 2 (DS 1 switching judgment section 3 2 1) on the slave shelf 3 side controls each DS 1 channel card 4 _ i on the master switch shelf 2 side. Therefore, as shown in FIG. 18, for example, as shown in FIG. 18, the master shelf 2 does not need to be aware of the fact that a plurality of slave shelves 3 are connected.

 Note that FIG. 18 shows a case where the number of DS 1 lines between the master shelf 2 and each slave shelf 3 is N, respectively. Of course, each slave shelf 3 The number of DS 1 lines may be different. Even in such a case, the master shelf 2 does not need to perform processing conscious of the difference in the number of DS1 lines.

 Further, in this case, each slave shelf 3 only needs to manage DS 1 line switching of its own shelf 3 alone (that is, each shelf control card 3 2 has its own DS 3 channel card 3 1 (I) does not issue a transparent time slot instruction to the DS 1 channel card 3 1—i in other slave shelves 3), so the independence of the architecture between the slave shelves 3 increases, The configuration becomes simple.

Further, as described above, the master shelf 2 does not need to be aware of the existence of the slave shelf 3, and the channel card 2 for each DS 1 in the master shelf 1 3-i only needs to exchange the time slot on the backboard bus 24 between the slave shelf 3 side and the associated DS 1 channel card 31-i. For example, as shown in FIG. In addition, the service card other than the DS1 channel card 23_i (for example, the desired communication service device via the subscriber line 130-1 to 130-K (K is a natural number)) Existing DS 0 channel card for accommodating subscriber terminal 1 0 3—1 to 1 03—K] 1 1 3—1 to 1 1 3—K Even if it is accommodated, its service card 1 1 The access time slot position of 3—1 to 1 13 _K is not affected.

 In other words, the service card on the 2nd side of the cell 1 1 3— ;! ~ 1 1 3— Κ does not need to be aware of DS 1 line switching as described above. As a result, the channel 2 on the side of the mass-shelf 2 is for the DS1 channel card 23-i and other service capabilities 1 1 3— :! ~ 1 1 3-K can be mixed and accommodated, greatly improving the flexibility and versatility of the device configuration.

 Therefore, for example, a part of the DS0 channel cards 1 13 _1-1 to 113-N in the existing master shelf 102A shown in FIG. 21 is transferred to the DS1 channel cards 23_i. By exchanging the slave shelves 3 as shown in FIG. 19, it becomes possible to cover the subscriber settlement 6 that cannot be covered by the mass storage shelf 102A as a service target.

In other words, for example, as shown in FIG. 24, a plurality of subscriber terminals 6—that form a subscriber community (first subscriber terminal group) 6— :! ~ 6—M to accommodate these subscriber terminals 6— :! 6—At least one relay transmission device 3 for multiplexing and outputting signals from M, and a plurality of subscriber terminals constituting the relay transmission device 3 and the subscriber community (second subscriber terminal group) 103 1 03—1 to 103—K (K is a natural number that satisfies K <N) and these subscriber terminals 1 03— :! DLC system 1 is constructed, comprising a subscriber transmission device 2 (102 A) that multiplexes signals from 〜 103 to K and the relay transmission device 3 and outputs the multiplexed signal to the central office 101. . In the above-described embodiment, when a DS1 line failure occurs, all the DS0 data transmitted on the failed DS1 line 41 i are switched to the time slot on the same spare line 4-i. However, as described above, Since the switching of the nodes 32 can be controlled in units of time slots, that is, in units of DS 0, for example, DS 0 data may be distributed and assigned to empty time slots on different DS 1 circuits 41 i. . In this way, the switching destinations of the DS1 line at the time of occurrence of a failure are dispersed, so that it is possible to reduce the line capacity pressure of each DS1 line 4-i.

 Further, in the above-described embodiment, one time slot = 1 DS0 / night. However, the present invention is not limited to this. Even if a signal assigned to one time slot is a signal other than DS0 / night, The same operation and effect can be obtained.

 The present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the spirit of the present invention. Industrial applicability

 As described above, according to the present invention, the time slot allocation of the channel signal transmitted through the trunk line between the subscriber transmission device and the trunk transmission device is controlled from the trunk transmission device side to each trunk line in common. Therefore, it is possible to provide an extremely inexpensive subscriber-system transmission system that can support various trunk line connection modes and line switching modes without changing the basic architecture of the subscriber-system transmission device. It is possible.

 Therefore, for example, in an area with a vast land area such as North America, it is possible to cover another subscriber settlement without laying a new optical fiber and a subscriber transmission device. A system that can flexibly respond to line switching can be provided at low cost, and its usefulness is considered to be extremely high.

Claims

The scope of the claims

1. Subscriber transmission equipment (2),

 A relay transmission device (3) capable of accommodating a plurality of subscriber terminals (6-1 to 6-M), and interposed between the subscriber transmission device (2) and the relay transmission device (3) And multiple trunk lines (4-1 to 4-N)

 In the relay transmission device (3),

 A time slot management unit (3 2 3) that collectively manages information on the time slot allocation of the channel signal transmitted on each of the above trunk lines (4 i; i = l to N);

 A time slot common for controlling the time slot allocation to each of the above trunk lines (4-1i) in common to the trunk lines (4-1i) based on the information managed by the time slot management unit (32-3). And a control unit (324).

2. The subscriber transmission device (2)

 It has a plurality of channel units (23-i) for interfacing each of the above trunk lines (4-i),

 For each of the above channel units (2 3— i),

 An accommodation slot position information transmitting section (23 3) for transmitting information on the accommodation slot position to the relay transmission device (3) via the relay line (4-1i); and The time slot management unit (3 2 3) of 3)

 The invention is characterized in that the information on the accommodation slot position sent from the time slot information sending section (2 3 3) of each of the channel units (2 3 — i) is collectively managed. Subscriber transmissions described in Section 1 of the scope of:

3. The time slot common control unit (324)

The channel signal assigned to a certain time slot on a certain trunk line (4-i) is assigned to a time slot on another trunk line (4-i). 3. The subscriber transmission system according to claim 1 or 2, further comprising a time slot change unit (325) capable of changing slot assignment.

4. The relay transmission device (3)

 An alarm detector (3 15) for detecting alarm information on a certain trunk line (4-i) is provided.

 The time slot change unit (325)

 When the alarm information is detected by the alarm detection unit (3 15), the alarm information is stored in a vacant time slot other than the time slot on the trunk line (4-1i) where the alarm information is detected. 4. The method according to claim 3, wherein the time slot assignment is changed to assign a channel signal assigned to a time slot on the detected trunk line (4-1i). Subscriber transmission system.

5. The subscriber transmission system according to claim 1, wherein said relay transmission device (3) is connected to said subscriber transmission device (2) for a plurality of times.

6. The subscriber transmission apparatus (2) is characterized by accommodating a desired communication service apparatus (6 ') via a line (5') other than the trunk line (4-1i). Subscriber transmission described in claim 1 of the scope of the request:

7. While accommodating a plurality of subscriber terminals (6-1 to 6-M), it is accommodated in a subscriber transmission device (2) via a plurality of relay lines (4-1;! To 41-N). Relay transmission equipment (3)

 A time slot management unit (323) that collectively manages information on time slot assignment of channel signals transmitted through each of the above trunk lines (4-1);

A time slot common control unit for controlling the time slot allocation to each of the above trunk lines (4-i) in common to the trunk lines (4-i) based on the information managed by the time slot management unit (323) (324) and that A relay transmission device.

8. In a subscriber transmission device (2) that accommodates a relay transmission device (3) capable of accommodating a plurality of subscriber terminals (6-1 to 6_M) via a plurality of trunk lines (4-1i), A plurality of channel units (23-i) for interfacing each of the above trunk lines (4-1) are provided,

 For each of the above channel units (23-i),

 The relay transmission device (3) collects information on the storage slot position of its own channel unit (23-i) so that the relay transmission device (3) can collectively manage and control the time slot allocation to each of the relay lines (4-1). A subscriber transmission device, characterized by being provided with an accommodation slot position information transmission section (233) for transmitting to the relay transmission device (3) via the line (4_i).

9. It accommodates the first and second subscriber terminal groups, each consisting of a plurality of subscriber terminals (6-1 to 6-M, 103-1 to: L03-K), and the higher-level device (10

1) A subscriber transmission system (1) for distributing the multiplexed signal from the subscriber terminal to the subscriber terminal (6— :! to 6—M, 103—1 to: L 03—K),

 Accommodates a plurality of subscriber terminals (6-1 to 6_M) constituting the first subscriber terminal group, and multiplexes and outputs signals from the subscriber terminals (6-1 to 6_M). At least one relay transmission device (3);

 It is connected to the relay transmission device (3) and a plurality of subscriber terminals (103-:!-103_K) constituting the second subscriber terminal group, and is connected to the subscriber terminals (103-3-1-1-). 103-3) and a subscriber transmission device (2) that multiplexes the signal from the relay transmission device (3) and outputs the multiplexed signal to the higher-level device (101). Subscriber transmission system.