WO2001082541A2 - Signal generating method and apparatus using sequential memory banks - Google Patents

Abstract

Waveform generator (40) is capable of generating an arbitrary waveform in quadrature format. Each of the I and Q components of the waveform is generated by addressing data in a plurality of non-volatile storage blocks (e.g. A-F for the I component) and demultiplexing (via unit 44 for the I channel) the retrieved data into a sequence forming the component which can then be combined with the other component in the analogue domain to produce the desired waveform.

Description

SIGNAL GENERATING METHODS AND APPARATUS

The invention relates to methods and apparatus for generating signals.

Signal generators commonly use IQ modulators and arbitrary waveform generators to generate complex modulation signals.

IQ modulators can be used to generate the complex modulated signals which are used in modern communication systems (IS95, cdmaOne, GSM, UMTS, IS 136). An IQ modulator is capable of generating, in principle, a signal with any phase and amplitude by applying two signals to it. These two signals, the I and Q signals, each control one aspect of the modulator output signal, as shown in Figure 2. The I signal which can have a positive or negative amplitude, controls the In phase component and the Q signal controls the Quadrature phase signal. The resulting signal is typically represented on an IQ constellation diagram (Figure 3) where the positive I axis represents signals with no phase shift, the negative I axis represents signals 180° out of phase. The positive Q axis represents signals 90° out of phase and the negative Q axis represents signals 270° (-90°) out of phase. The distance from the origin of the IQ diagram to any point represents the signal's amplitude, while the angle relative to the positive I axis represents its phase.

To generate an output, the modulator requires two signals, one representative of the I component and one representative of the Q component.

It is known in the art that an arbitrary waveform generator (commonly referred to as an ARB) can be used to generate the I and Q inputs to a vector modulator.

A conventional ARB, as shown in simplified form in Figure 4, typically has a non-volatile file storage system 10, which is loaded with data on how the required I and Q signals vary with time. To generate the required signal, the file is first transferred from the non-volatile store 10 to a fast, RAM-based storage system 12 in the ARB. The RAM is used because typically an ARB needs to operate at speeds considerably faster than non-volatile memory can operate at. The information in the RAM is then read out by clocking an address generator 14 which sequentially increases the RAM address that is read out of the RAM 12. The outputs of the RAM 12 are passed on to digital to analogue converters 16 and 18 (which may also require a clock) to generate analogue output signals.

When used to simulate an air interface in telecommunications, the data in the ARB file needs to be sampled at a rate higher than the data rate of the air interface being simulated. Information theory requires the sample rate to be at least twice the chip or symbol rate of the air interface, usually referred to as the over-sampling rate. In practice the sampling process also generates spurious signals at its output at harmonics of the sampling rate as shown in Figure 5. In order to remove these spurious signals, the ARB typically uses a hardware filter to suppress them. In order to give spectral room to filter the signal, this means that, in reality, signals have to be over-sampled at least 4 times the chip or symbol rate of the air interface. The hardware filtering can be made easier by substantially increasing the over-sampling rate. However, this causes the file size required to generate a particular waveform to double each time the over-sampling rate is doubled. This can add significant expense to the cost of the ARB as well as increasing the amount of time it takes to download from the non- volatile memory 10 to the ARB RAM 12.

Using only a 4 times over-sampling rate (to minimise file size) also means that a great number of hardware filters are required if the ARB performance is being optimised for a large variety of signal bandwidths since the clock frequency, and hence the cut off frequency of the filter, have to be changed with signal bandwidth. In a typical ARB system, a number of switched filters have to be used to minimise the over-sampling ratio and suppress unwanted signals. These are indicated by filter banks 20 and 22 in the conventional ARB of Figure 4.

The hardware filters used to suppress the spurious signals also introduce frequency and phase response errors to the I and Q signals. In order to minimise these errors, the filter characteristics have to be carefully controlled, and the user may have to take into account the errors they introduce when generating the ARB files. The lower the over-sampling rates used, the greater the error since the filter needs to attenuate signals more closely spaced (spectrally) to the wanted signals. Another source of error is that when modulation systems are described in the relevant standards, the modulation characteristics of the air interface are generally described in terms of their impulse response. ARB generators, however, inherently generate sampled data. This causes the ARB to generate a signal, which is not quite correct - the error being a sinx/x function (see Figure 7 sampled data response compared to Figure 6 impulse response). The lower the over-sampling rate, the greater the effect this source of error has on the waveform generated. The error can be corrected since it can be precisely mathematically described, but the correction factors to be applied are dependent on the over-sampling factor (the lower the over-sampling factor, the greater the correction).

It can be seen that although ARBs are useful for generating IQ signals there are many compromises involving the over-sampling ratio, file size, memory download times, hardware filters and correcting for mathematical and analogue defects. It is an object of the invention to provide signal generating methods and apparatus which ameliorate at least some of these drawbacks.

According to one aspect, the invention provides a method of generating a signal, comprising addressing values in each of a plurality of storage blocks, making said values available for use outside their blocks and transferring said values into a sequence forming said signal, wherein a value made available by a block is transferred into said sequence whilst another block is making an addressed value available.

The invention also consists in apparatus for generating a signal, comprising a plurality of storage blocks containing values, means for addressing values in each of said blocks to cause the addressed values to be made available for use outside their blocks and transfer means for transferring the values made available into a sequence forming said signal, wherein the transfer means is arranged to transfer a value made available by a block into said sequence whilst another block is in the process of making an addressed value available.

Thus, the invention provides for the faster supply of values constituting a signal. The need for an intermediate fast-access memory may be eliminated. In one embodiment, the values made available by the blocks are read sequentially from the blocks to form a signal. The values are read sequentially whilst newly addressed values are in the process of being made available in the blocks for reading. After the output of a block has been read, a new value may be addressed in that block and, whilst the newly addressed value is being made available by the block, the outputs of other blocks are read. In this way, the outputs of all the blocks may be updated and re-read.

In another embodiment, the values made available by the blocks are read into a plurality of latches from which they are transferred sequentially into the signal.

Preferably, additional values are interpolated between the values supplied in the sequence. Advantages conferred by interpolation will be understood from the following description.

According to another aspect, the invention provides a method of generating a signal, comprising reading values from a storage means into a sequence to form the signal and interpolating additional values for the sequence from the values read.

The invention also consists in apparatus for generating a signal, comprising a storage means storing values, means for reading values from the storage means into a sequence forming said signal and interpolating means for interpolating additional values for the sequence from values obtained from the storage means.

Hence, the invention provides a method of producing a highly sampled signal from relatively few data values, which means that the frequency of reading from the memory is relatively low. This may lead, in turn, to the viability of slow-access memory for storing the data. The fast-access, intermediate memory of the conventional ARB described with reference to Figure 4 could then be omitted.

In a preferred embodiment, the signal is converted to the analogue domain. The analogue signal may then be filtered. The signal may be precorrected before the filtering operation to counteract distortion caused by the filtering process itself. Where additional values are interpolated into the signal, the interpolation process can be arranged to provide the signal with an optimum sampling frequency for the digital to analogue conversion process, such that subsequent filtering to remove unwanted signals from the digital to analogue conversion process can be performed by a single filter rather than a bank of filters as in the prior art.

In a preferred embodiment, the signal generated is used to drive an input of a modulator. For example, the modulator may be an IQ vector modulator and another signal generated by a similar process may be used to drive the other input of the modulator.

In one embodiment, the values used to form the sequence representing the generated signal are stored in non- volatile memory.

By way of example only, certain embodiments of the invention will now be described with reference to accompanying figures, in which:

Figure 1 illustrates schematically an arbitrary waveform generator according to the invention;

Figure 2 illustrates schematically an IQ modulator;

Figure 3 illustrates a constellation diagram for a quadrature format signal;

Figure 4 illustrates schematically a conventional arbitrary waveform generator;

Figure 5 is a plot illustrating spurious signal generation;

Figure 6 illustrates an impulse response;

Figure 7 illustrates a response of a sampled data system; and

Figure 8 illustrates another arbitrary waveform generator using a programmable interpolator. Figure 1 shows a block diagram of an ARB 40. For clarity only one channel (I) is shown. The Q waveform is generated by an equivalent system.

An ARB file is loaded into a non-volatile memory 42. Instead of being loaded in a conventional serial manner, the file information is split between separate blocks of memory A-F. ARB file values are loaded in sequence between the memory blocks. As an example, if the first value is loaded into block A, the second value is loaded into block B and so forth. Once a value has been written into each memory block, the next value is loaded into the next available location in block A.

The non-volatile memory 42 is read under the control of timing generator 46. In a given read operation, each of the blocks A-F delivers to its output the data item specified by the value of the address generator 48. The de-mulitplexer 44 then proceeds to read the outputs of blocks A-F sequentially, and provides the data items as a serial stream of I-component values in the time sequence order. After the output of block A has been read, the address generator increments to the next address of that block to be read while the demultiplexer moves to the outputs of blocks B, C, D, E and F in turn to read their outputs. Whilst these blocks are being read the output from block A has time to settle. The same principle is applied to each of the blocks, so immediately after it has been read its address is incremented and its output allowed to settle while the other blocks are being read.

The effect of loading and de-multiplexing information in this way should be apparent to those skilled in the art. Non-volatile memory takes a relatively long time, typically 90 ns, to read compared to the speeds usually required for an ARB. However, in the above arrangement, if the non volatile memory has a read time of 90 ns and there are six blocks of memory, the output from the de-multiplexer can be updated every 15 ns without exceeding the read time specification of each memory block. Each block of memory is only read after the de-multiplexer 44 has been clocked 6 times. This allows the ARB to run without an intermediate RAM device and with no speed penalty on the circuits. The output from the de-multiplexer 44 is supplied to a programmable interpolator 50. The interpolator 50 increases the sampling rate of the ARB. The interpolator 50 examines the digital data stream from the de-multiplexer 44 and, from the values before and after a specified instant in time, calculates an approximation of what the value would have been if it had been sampled at that instant.

In general, an interpolator works out intermediate values at sufficient additional points in time to multiply the number of values in the data stream by factors of 2, 3, 4, 6, 8, 12, 16 and 32 or greater than the sampling rate of the ARB file. The interpolator 50 is programmable in that it can be controlled to select for use an appropriate interpolation factor and/or an appropriate signal correction characteristic.

Methods of performing interpolation are known in the art. The simplest case is a linear interpolator in which the intermediate sample is constructed by assuming the data changes linearly from one sample to another. This type of interpolation is not suitable for ARB signals with low over-sampling values since it is likely to introduce errors. A more accurate estimation can be obtained by taking into account more samples either side of the wanted instant and performing a more complex calculation with higher order terms in the interpolation calculation.

The D-A converter clock rate can be confined to a range of 2:1 by using interpolation factors which are multiples of two. The minimum clock rate is then half the maximum clock rate. The minimum clock rate can be increased by using interpolation factors which are multiples of three as well, the higher clock rate resulting in an improved performance for the ARB. As an example, if the maximum sample rate of the converter were 60 MHz, factors of two in interpolation values would fix the clock frequency range of the D-A converter rate to 30 MHz to 60 MHz. So an interpolation factor of two would need an interpolator input of 15 MHz to 30 MHz. However, the availability of a factor of 3 interpolation factor can be used to lift the D-A converter rate of a 15 MHz input to the interpolator to 45 MHz instead of 30 MHz. Only when the interpolator input rate reaches 20 MHz does a factor of three interpolation need to be decreased to a factor 2, so the clock frequency range of the converter in this example can be constrained to 40 MHz to 60 MHz. The output from the interpolator 50 is at a sampling rate higher than the ARB file sample rate. This data stream is then passed into the digital to analogue converter 52 whose output is filtered by filter 54 to reduce the amplitude of the harmonic signals therein. The programmable interpolator 50 could be employed in other types of signal generator, and Figure 8 illustrates the use of such a programmable interpolator in the generator of Figure 4. In Figure 8, a programmable interpolator 51 is used for the I+Q branches to reduce the size of the size of the file in the RAM used to generate a given signal and also to optimise the clock rate of the D-A converters following the interpolator 51.

Returning to Figure 1, the clock signals for the digital circuits are generated by the clock and timing generator 46. The clock inputs to non-volatile memory 42 need to be timed such that each store is sampled in turn by the de-multiplexer 44. The clock signal to the de-multiplexer 44 needs to operate at a rate equal to the clock frequency to the non- volatile store multiplied by the number of memory blocks used. This rate is equal to the sampling rate of the source data for the ARB. The interpolator clock operates at a rate determined by the interpolation factor being used (in the example above factors 2, 3, 4, 6, 8, 12, 16 and 32 greater than the de-multiplexer rate).

The digital circuits required in the clock and timing generator and the interpolator can be implemented in Field Programmable Logic Arrays (FPGA) or similar devices to minimise manufacturing complexity and printed circuit board area.

This circuit arrangement allows the sample rate of the source ARB file (the de-multiplexer rate) to be lower than sample rate of the digital to analogue converters. The user of the waveform generator may have no prior knowledge of the interpolation rate factor that will be used. In order for the ARB to be used the user must specify the sample rate at which the data is generated. The user does not apply the sinx/x correction to the data stream to account for the difference between signals reconstructed as sampled data and impulse response. When the data file is initially generated by the user, a software programme can be provided which takes the input data sampling rate and selects the best interpolation factor for the ARB. The information on the data sample rate and the interpolation to be used is defined in the data file as "header" information. When the waveform is selected to be run by the ARB the information is checked and is used to set up the clock signals used. In addition, the ARB is arranged to correct for the sinx/x (e.g. this can be done in a FPGA). This means that the user does not have the added complexity of correcting for this error.

The need to have different hardware filters for different signal bandwidths is removed by the programmable interpolator 50 which can be implemented in a FPGA (or other such reconfigurable module), and is easier to re-programme than a hardware filter. The FPGA can be programmed and reprogrammed as necessary to switch between various processing configurations, each of which implements an interpolator with a different interpolation factor and/or signal error correction characteristic (e.g. for the sinx/x error).

In a typical implementation, the non-volatile memory is arranged so that it contains a number of files representing different waveforms that are to be generated. Rapid changeover between files is facilitated by not having to download files into RAM as in the conventional RAM of Figure 4. The position of files in the memory is controlled so that the user can select which waveform is required. The use of the interpolation scheme ensures that the file size is minimised, therefore maximising the amount of useful data that can be stored. When high interpolation factors are used the storage system can be reconfigured to not use the de-multiplexer. In the example given above where the memory speed is 90 ns and the required digital to analogue converter rate is 15 ns, then if the interpolator operates at a factor of 6 or more one memory block can be used. This gives more flexibility in data file management, particularly since non-volatile flash memory stores are internally configured in blocks.

The above description has described the invention for one waveform to drive the IQ modulator. In a typical application, a second waveform is required and is generated by an identical system. The memory arrangement for this second channel can be integrated into the memory for the first channel.

Claims

1. A method of generating a signal, comprising addressing values in each of a plurality of storage blocks, making said values available for use outside their blocks and transferring said values into a sequence forming said signal, wherein a value made available by a block is transferred into said sequence whilst another block is making an addressed value available.

2. A method according to claim 1, wherein transferring values into said sequence comprises reading values from their blocks into the sequence.

3. A method according to claim 1, wherein the values made available by the blocks are read into a storage means and values are transferred into the sequence by reading them from the storage means.

4. A method according to claim 1, 2 or 3, wherein the values in the blocks comprise sets each forming a respective signal and the method further comprises selecting one of the sets such that the values for the sequence are obtained from the selected set.

5. A method according to any preceding claim, further comprising interpolating additional values for the sequence from the values obtained from the blocks.

6. A method of generating a signal, comprising reading values from a storage means into a sequence to form the signal and interpolating additional values for the sequence from the values read.

7. A method according to claim 5 or 6, wherein the interpolation factor of the interpolation process is adjustable.

8. A method according to claim 5, 6 or 7, wherein the interpolation is arranged to give the signal a frequency of values which facilitates the removal of errors created by converting the signal to the analogue domain.

9. A method according to any preceding claim, further comprising converting the sequence to the analogue domain.

10. A method of generating a modulated signal, comprising modulating a signal with a modulation signal generated using the method of any one of claims 1 to 9.

11. A method of generating a modulated signal, comprising quadrature modulating a signal using an in-phase signal and a quadrature signal, wherein at least one of the in-phase and quadrature signals is generated using the method of any one of claims 1 to 9.

12. Apparatus for generating a signal, comprising a plurality of storage blocks containing values, means for addressing values in each of said blocks to cause the addressed values to be made available for use outside their blocks and transfer means for transferring the values made available into a sequence forming said signal, wherein the transfer means is arranged to transfer a value made available by a block into said sequence whilst another block is in the process of making an addressed value available.

13. Apparatus according to claim 13, wherein the transfer means is arranged to read values from their blocks into the sequence.

14. Apparatus according to claim 12, further comprising a storage means into which values made available by the blocks are read and wherein the transfer means is arranged to read values from the storage means into the sequence.

15. Apparatus according to claim 12, 13 or 14, wherein the values in the blocks comprise sets each forming a respective signal and the addressing and transfer means are arranged to respond to the selection of a set by obtaining the values for the sequence from the selected set.

16. Apparatus according to any one of claims 12 to 15, further comprising interpolating means for interpolating additional values for the sequence from the values obtained from the blocks.

17. Apparatus for generating a signal, comprising a storage means storing values, means for reading values from the storage means into a sequence forming said signal and interpolating means for interpolating additional values for the sequence from values obtained from the storage means.

18. Apparatus according to claim 16 or 17, wherein the interpolation factor of the interpolating means is adjustable.

19. Apparatus according to claim 18, wherein the interpolating means is reconfigurable to change the interpolation factor.

20. Apparatus according to any one of claims 16 to 19, wherein the interpolating means is arranged to give the signal a frequency of values which facilitates the removal of errors created by converting the signal to the analogue domain.

21. Apparatus according to any one of claims 12 to 20, further comprising means for converting the sequence into an analogue signal.

22. Apparatus for generating a modulated signal, comprising means for modulating a signal with a modulation signal to produce the modulated signal and apparatus according to any one of claims 12 to 21 for generating a signal to be the modulation signal.

23. Apparatus for generating a modulated signal, comprising means for quadrature modulating a signal with in-phase and quadrature signals to produce the modulated signal and further comprising apparatus according to any one of claims 12 to 21 to generate at least one of the in-phase and quadrature components.