WO2001078297A3 - Method and apparatus for synchronizing data transmission and reception over a network - Google Patents

Method and apparatus for synchronizing data transmission and reception over a network Download PDF

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Publication number
WO2001078297A3
WO2001078297A3 PCT/US2001/010500 US0110500W WO0178297A3 WO 2001078297 A3 WO2001078297 A3 WO 2001078297A3 US 0110500 W US0110500 W US 0110500W WO 0178297 A3 WO0178297 A3 WO 0178297A3
Authority
WO
WIPO (PCT)
Prior art keywords
communication network
digital samples
digital
network
encoding
Prior art date
Application number
PCT/US2001/010500
Other languages
French (fr)
Other versions
WO2001078297A2 (en
Inventor
Thomas Harnett
Original Assignee
Comrex Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/545,375 external-priority patent/US6754295B1/en
Application filed by Comrex Corp filed Critical Comrex Corp
Priority to AU2001251204A priority Critical patent/AU2001251204A1/en
Publication of WO2001078297A2 publication Critical patent/WO2001078297A2/en
Publication of WO2001078297A3 publication Critical patent/WO2001078297A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers

Abstract

In one embodiment, the invention is directed to methods and system for converting an analog signal to digital samples for transmission over a communication network, and for converting digital samples received over a communication network to an analog signal. According to one feature, the system of the invention generates encoding and decoding master clocks from local oscillators, thus enabling the system of the invention to operate in environments where reliable timing signals are not available from the communication network. According to another feature, the system of the invention adjusts the frequencies of the encoding and decoding master clocks based on a connect rate to the communication network. In a further feature, the system of the invention employs encoding and decoding buffers for buffering the digital samples between a modem or a digital network access device, and signal converters to maintain a defined time relationship between digital samples being transferred between the modem or the digital network access device and the signal converters.
PCT/US2001/010500 2000-04-07 2001-04-02 Method and apparatus for synchronizing data transmission and reception over a network WO2001078297A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001251204A AU2001251204A1 (en) 2000-04-07 2001-04-02 Method and apparatus for synchronizing data transmission and reception over a network

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/545,375 2000-04-07
US09/545,375 US6754295B1 (en) 2000-04-07 2000-04-07 Method and apparatus for synchronizing data transmission and reception over a network
US66349300A 2000-09-18 2000-09-18
US09/663,493 2000-09-18

Publications (2)

Publication Number Publication Date
WO2001078297A2 WO2001078297A2 (en) 2001-10-18
WO2001078297A3 true WO2001078297A3 (en) 2003-02-27

Family

ID=27067915

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/010500 WO2001078297A2 (en) 2000-04-07 2001-04-02 Method and apparatus for synchronizing data transmission and reception over a network

Country Status (2)

Country Link
AU (1) AU2001251204A1 (en)
WO (1) WO2001078297A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7260090B2 (en) 2002-04-26 2007-08-21 Ontash & Ermac, Inc. Analog gateway
GB2388501A (en) * 2002-05-09 2003-11-12 Sony Uk Ltd Data packet and clock signal transmission via different paths
DE102013014876B3 (en) * 2013-09-06 2014-12-11 Hottinger Baldwin Messtechnik Gmbh Measuring amplifier with background adjustment and method for it

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3754098A (en) * 1971-10-08 1973-08-21 Adaptive Tech Asynchronous sampling and reconstruction for asynchronous sample data communication system
EP0718995A1 (en) * 1994-12-20 1996-06-26 International Business Machines Corporation Apparatus and method for synchronizing clock signals for digital links in a packet switching mode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3754098A (en) * 1971-10-08 1973-08-21 Adaptive Tech Asynchronous sampling and reconstruction for asynchronous sample data communication system
EP0718995A1 (en) * 1994-12-20 1996-06-26 International Business Machines Corporation Apparatus and method for synchronizing clock signals for digital links in a packet switching mode

Also Published As

Publication number Publication date
AU2001251204A1 (en) 2001-10-23
WO2001078297A2 (en) 2001-10-18

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