WO2001078126A2 - A method of passivating a metal line on a wafer - Google Patents

A method of passivating a metal line on a wafer Download PDF

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Publication number
WO2001078126A2
WO2001078126A2 PCT/US2001/010552 US0110552W WO0178126A2 WO 2001078126 A2 WO2001078126 A2 WO 2001078126A2 US 0110552 W US0110552 W US 0110552W WO 0178126 A2 WO0178126 A2 WO 0178126A2
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WO
WIPO (PCT)
Prior art keywords
wafer
metal line
protective layer
present
temperature
Prior art date
Application number
PCT/US2001/010552
Other languages
French (fr)
Other versions
WO2001078126A3 (en
Inventor
Rao Venkateswara Annapragada
Original Assignee
Philips Semiconductors, Inc.
Koninklijke Philips Electronics N.V.
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Application filed by Philips Semiconductors, Inc., Koninklijke Philips Electronics N.V. filed Critical Philips Semiconductors, Inc.
Publication of WO2001078126A2 publication Critical patent/WO2001078126A2/en
Publication of WO2001078126A3 publication Critical patent/WO2001078126A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Definitions

  • the field of the present invention pertains to semiconductor fabrication processes. More particularly, the present invention relates to the field of passivating metal lines located on a wafer without generating cracks.
  • IC integrated circuit
  • More and more components are continually being integrated into the underlying chip, or Integrated Circuit (IC).
  • IC Integrated Circuit
  • the starting material for typical ICs is high purity silicon. The material is grown as a single crystal and takes the shape of a solid cylinder. This crystal is then sawed (like a slice of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick.
  • the geometry of the features of the IC components are commonly defined photographically through a process known as photolithography. Very fine surface geometry can be accurately reproduced by this technique.
  • the photolithography process is used to define component regions and build up components one layer on top of another. Complex ICs can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer. The resulting topography of these complex ICs often resemble familiar terrestrial "mountain ranges,” with many "hills” and “valleys” as the IC components are built up on the underlying surface of the silicon wafer.
  • Metal lines create excellent conductors.
  • the typical metals utilized for the lines and vias are subject to corrosion and reaction to other chemicals and environments utilized for creating the IC. Consequently, a need exists to protect these metal lines from corrosion and reaction after the metal lines have been formed on the wafer.
  • a conventional protective layer covering a metal line on a wafer is shown.
  • Metal line 104 shown in a side view, is deposited on a wafer 102, and can extend in the Y-direction, or other directions.
  • the conventional protective layer 106 covers metal line 104.
  • the conventional protective layer process generates an undesirable corner crack 108a in protective layer 106. ⁇ This crack can compromise the integrity of the protective layer on the metal line, and thus increase the risk of corrosion and chemical reaction on metal line 104. The increased risk may ultimately cause a failure in the devices coupled to metal line 104 or in the IC containing the metal line. Consequently, a need arises to prevent corner cracks from occurring in the protective layer covering the metal line.
  • a need arises to protect metal lines from corrosion and reaction after the metal lines have been formed on the wafer. Furthermore, a need arises to prevent corner cracks from occurring in the protective layer covering the metal line. Finally, a need arises to prevent top cracks from occurring in the protective layer covering the metal line.
  • the present invention provides a method to protect metal lines from corrosion and reaction after the metal lines have been formed on the wafer. Furthermore, the present invention provides a method of protecting metal lines from corrosion and reaction with a protective layer that does not suffer from corner cracks. Additionally, the present invention provides a method of protecting metal lines from corrosion and reaction with a protective layer that does not suffer from top cracks.
  • one embodiment of the present invention includes a method of passivating a metal line without gen rating cracks in the protective layer covering the metal line.
  • the method comprises several steps.
  • the first step is to receive a wafer, with a metal line formed thereon, into a deposition chamber.
  • the wafer temperature is increased and maintained at a deposition temperature.
  • the deposition temperature is not more than approximately 400 degrees Celsius in the present embodiment.
  • the metal line is passivated by depositing a protective layer on the metal line.
  • the protective layer is a high density heat plasma chemical vapor deposition (HDP CVD) silicon dioxide, SiO 2 .
  • HDP CVD high density heat plasma chemical vapor deposition
  • the present invention avoids the generation of cracks in the protective layer.
  • the present invention provides a subsequent deposition of an additional protective layer, such as nitride, for added protection on the metal line.
  • Another embodiment of the present invention implements the method of providing a crack-free protective layer over a metal line using a processor and memory.
  • the steps provided in the previous paragraph are implemented as data and instructions of the memory to be executed by the processor.
  • FIGURE 1 is a side view of a conventional protective layer, with cracks, that cover a metal line on a wafer.
  • FIGURE 2 is a block diagram of a deposition chamber, in accordance with one embodiment of the present invention.
  • FIGURE 3 is a side view of a crack-free protective layer covering a metal line on a wafer, in accordance with one embodiment of the present invention.
  • FIGURE 4 is a flowchart of the steps performed to obtain a crack-free protective layer covering a metal line on a wafer, in accordance with one embodiment of the present invention.
  • the data is represented as physical (electronic) quantities within the registers and memories of the device, and is transformed into other data sirrrtlarly represented as physical quantities within the j device components, or computer system memories or registers, or other such information storage, transmission or display devices.
  • Deposition chamber 202 includes a wafer temperature controller 206, a processor 208, and a memory 210.
  • the deposition chamber is adapted to accept a wafer 204 therein, for subsequent deposition operations.
  • Processor 208 is coupled to memory 210 and to wafer temperature controller 206.
  • Memory 210 is capable of storing data and instructions that can be executed by processor 208.
  • Processor instructs other devices coupled to it, such as wafer temperature controller 206, to perform the appropriate instructions with the appropriate data, as supplied by memory 210.
  • Wafer temperature controller 206 of Figure 2 can be a controller that regulates the temperature of a back side of wafer 204, as shown in Figure 2. More specifically, wafer temperature controller 206 controls a cooling medium applied to wafer 204 such that a desired temperature range can accurately be reached and maintained. While the present embodiment utilizes helium as a cooling medium, e.g. a heat sink, the present invention is well-suited to using a wide variety of cooling mediums and a wide variety of methods to control temperature of wafer 204.
  • Memory 210 used in deposition chamber 202 can either be permanent memory, such as read only memory (ROM), or temporary memory sych as random access memory (RAM).
  • Memory 210 can also be any other type of memory storage, capable of containing program instructions, such as a hard drive, a CD ROM, or flash memory.
  • processor 208 can either be a dedicated controller, an existing system processor, a microprocessor, or some form of a state machine.
  • Metal line 304 shown in a side view, is formed on a wafer substrate 302 of wafer 204, and can extend in the Y-direction, or other directions.
  • the first protective layer 306 covers metal line 304.
  • Metal line 304 has a height 312 and a width 310. In one embodiment, metal line has a relatively large height 312 and
  • width 310 dimensions of 2 micrometers ( ⁇ m). These dimensions, representing
  • First protective layer 306 has a thickness, T 314.
  • thickness T 314 is approximately 8,000 angstroms (A) thick.
  • first protective layer of the present invention is essentially free of cracks, e.g. free of top cracks 108b and comer cracks 108a such as those shown in prior art Figure 1. Because the present invention generates a crack-free first protective layer, e.g. layer 306, metal line 304 is essentially becoming corrosion and reactive resistant.
  • first protective layer 306 is an oxide layer. More specifically, oxide layer 306 is a High Density Pfasma (HDP) oxide layer in one embodiment.
  • the present embodiment utilizes a deposition chamber to deposit the oxide layer, e.g. SiO 2 , onto metal line 304. More specifically, the deposition chamber is a High Density Plasma Chemical Vapor Deposition Chamber (HDPCVDC) in one embodiment.
  • HDPCVDC High Density Plasma Chemical Vapor Deposition Chamber
  • Second protective layer 307 shown in Figure 2, is a nitride layer in one embodiment. However, the present invention is well-suited to having a second protective layer of a wide variety of materials. In an alternative embodiment, metal line is passivated with only first protective layer 306 and not with second protective layer 307. Second protective layer 307 can have a wide range of thicknesses, similar to those described for first protective layer 306.
  • first protective layer 306 is a material, other than an oxide, that is deposited using a HDP.
  • second protective layer 307 can be a material other than nitride.
  • no second protective layer 307 is utilized over first protective layer 306.
  • the deposition chamber utilized to deposit second protective layer 307 can be a chamber other than the HDPCVDC, especially if second protective layer deposited is a material other than a HDP oxide layer. While the present invention is applied to a metal line on a wafer, the present invention is well-suited to providing an oxide coating a line of any metallic composition on any type of platform.
  • Additional alternatives to the embodiments presented for Figure 3 include a metal line 304 having any value of height 312 and width 310. Additionally, the present invention is well-suited to creating a wide range of thickness, T 314 for first protective layer 306. In one embodiment, thickness T 314 is approximately 6,000 to 10,000 angstroms (A) thick. Furthermore, thickness T 314 can vary between the thickness at the top of the metal line and on the sides of the metal line.
  • a benefit of the crack-free protective layer shown in Figure 3 is the improved corrosion protection offered to metal line 304. The improved corrosion protection, in turn, helps prevent failures in the devices arising from corrosion of metal lines. Consequently the yield of producing an IC increases, along with a corresponding unit cost decrease. Furthermore, reliability and performance of the final product is enhanced.
  • FIG. 4 a flowchart 4000 of the steps performed to obtain a crack-free protective layer covering a metal line on a wafer is shown, in accordance with one embodiment of the present invention.
  • a more corrosion-resistant protective layer can be provided over a metal line. Consequently, the present invention provides improved yield and performance of an Integrated Circuit (IC) device with metal lines.
  • IC Integrated Circuit
  • the present embodiment implements flowchart 4000 in a deposition chamber, the present invention can be implemented in other types of devices.
  • Step 4002 of the present embodiment a wafer with a metal line is received.
  • Step 4002 is implemented, in one embodiment, by the deposition chamber device shown in Figure 2.
  • deposition chamber 202 can receive wafer 204 in an appropriate stage, not shown, that will securely retain wafer 204.
  • Wafer 204 can be of the configuration shown in Figure 3, where wafer 204 has a metal line 304 formed on a wafer substrate 302.
  • the present invention is well-suited to forming the metal line on the wafer, or other substrate, while in the deposition chamber.
  • the present invention is well-suited to performing the process on any quantity of lines on a wafer.
  • flowchart 4000 proceeds to step 4004.
  • step 4004 of the present embodiment the wafer temperature is increased.
  • Step 4002 is implemented, in one embodiment, by the deposition chamber device shown in Figure 2.
  • HDP ion bombardment of a wafer intrinsically provides sufficient energy to heat wafer 204 to a desired temperature, and beyond.
  • the present invention is well-suited to supplementing the ion bombardment heating of the wafer in another embodiment.
  • flowchart 4000 proceeds to step 4006.
  • an inquiry determines whether the wafer temperature is at the deposition temperature.
  • the deposition temperature is between the> range of approximately 350 - 390 degrees Celsius. In another embodiment, the deposition temperature is approximately 370 degrees Celsius.
  • the temperature inquiry of step 4006 can be accomplished by heat sensing devices, known in the art, and by using an analog circuit or digital circuit such as memory 210 and process 208 of Figure 2. That is, memory 210 can be programmed with the desired deposition temperature, within the range specified above, as appropriate for a given material to be deposited, and a given material to be protected. If the wafer temperature is at the deposition temperature, then flowchart 4000 proceeds to step 4008. However, if the wafer temperature is not at the deposition temperature, then flowchart 4000 returns to step 4004.
  • Step 4008 arises if the wafer temperature is at the deposition temperature, per the inquiry of step 4006.
  • the wafer temperature is maintained at the deposition temperature.
  • the deposition temperature is within the temperature range specified for step 4006.
  • the present invention implements the step of maintaining the deposition temperature as previously described in the Figure 2 embodiment for step 4006.
  • a feedback system for controlling temperature is exists with the components shown in Figure 2.
  • wafer temperature controller 206 helps to accurately maintain the temperature of the wafer to create a crack-free protective layer.
  • step 4008 controls the desired temperature range of the wafer using wafer temperature controller 206, memory 210, and processor 208 of deposition chamber 202 as shown in Figure 2.
  • the present embodiment maintains the desired temperature range by moderating the intrinsic wafer heating from HDP ion bombardment with a controlled flow of a cooling medium to wafer 204.
  • the cooling medium is a helium gas.
  • the present invention is well-suited to using a wide range of cooling mediums and a wide range of methods to achieve the desired temperature range used for depositing the first protective layer.
  • step 4008 implements step 4008 with digital circuitry, the present invention is well-suited to using analog apparatus. Following step 4008, flowchart 4000 proceeds to step 4010.
  • a first protective layer is deposited on metal line.
  • the first protective layer is an oxide layer.
  • the oxide layer can more specifically be chosen as a High Density Plasma (HDP) oxide layer.
  • Step 4010 is implemented, in one embodiment, to produce the product shown in Figure 3, where first protective layer 306 is created on top of metal line 304.
  • the present invention produces a protective layer without cracks. Consequently, the present invention provides a robust protective layer over the metal line that prevents corrosion and reaction on the metal line. While the present embodiment describes the first protective layer as a specific material and configuration, the present invention is well-suited to the alternatives described for first protective layer 306 of Figure 2. Following step 4010, flowchart 4000 proceeds to step 4012.
  • step 4012 of the present embodiment an inquiry determines whether the first protective layer is at the desired thickness.
  • the first protective layer has a thickness of approximately 6,000 to 10,000 angstroms (A).
  • first protective layer has a thickness of approximately 8,000 angstroms (A).
  • the present invention is well-suited to a wide-range of thickness for first protective layer.
  • Step 4012 is implemented, in one embodiment, to produce the product shown in Figure 3, where first protective layer 306 has a thickness of T 314.
  • the thickness of the first protective layer can be varied according to the specific application and corrosion resistance desired. While the present embodiment describes the first protective layer with a specific thickness and configuration, the present invention is well-suited to the alternatives thickness properties described for first protective layer 306 of Figure 2. If the first protective layer is at the desired thickness, then flowchart 4000 proceeds to step 4014. However, if the first protective layer is not at the desired thickness, then flowchart 4000 returns to step 4010.
  • Step 4014 arises if the first protective layer is at the desired thickness, per the inquiry of step 4012.
  • a second protective layer is deposited onto the first protective layer.
  • the second protective layer is a nitride layer.
  • the nitride layer can be deposited to a wide range of thicknesses and applied over a wide range of temperatures.
  • the absence of cracks in the first protective layer provides a stable and homogeneous layer upon which the second protective layer can be placed. Hence, the integrity of the first protective layer can actually increase the robustness of the operating tolerances used to apply the second protective layer.
  • the present invention implements the application of a second protective layer using a deposition chamber, similar to the one shown in the Figure 2.
  • deposition chamber 202 of Figure 2 is a Plasma Enhanced (PE) Chemical Vapor Deposition Chamber (CVDC) for depositing nitride.
  • PE Plasma Enhanced
  • CVDC Chemical Vapor Deposition Chamber
  • step 4016 of the present embodiment the wafer is cooled to room temperature.
  • Step 4016 is implemented, in one embodiment, by the deposition chamber 202 shown in Figure 2.
  • cooling is achieved in the present embodiment by flowing a helium gas cooling medium to wafer 204, as controlled by wafer temperature controller 206.
  • the wafer may be cooled by convection or conduction.
  • wafer 204 may be removed from deposition chamber 202 to be cooled in another area by another device.
  • the wafer may be transferred to another machine for subsequent operation, e.g. additional deposition of semiconductor material or photoresist layers, without having a cooling step.
  • flowchart 4000 ends. Additional steps used for vapor deposition and wafer handling operations, such as evacuation of the vapor deposition chamber, are well-known in the art. These steps have been omitted herein so as not to obstruct the salient features o
  • flowchart 4000 of the present embodiment shows a specific sequence and quantity of steps
  • the present invention is suitable to alternative embodiments. For example, not all the steps provided for flowchart 4000 are required for the present invention.
  • an alternative embodiment of flowchart 4000 can omit steps 4014 and 4016 if a second protective layer is not desired or required for the metal line.
  • additional steps may be added to the steps presented in the present embodiment.
  • the sequence of the steps can be modified depending upon the application. While flowchart 4000 is shown as a single serial process, it can also be implemented as a continuous or parallel process.
  • the memory storage 210 for the present embodiment can either be permanent, such as read only memory (ROM), or temporary memory such as random access memory (RAM).
  • ROM read only memory
  • RAM random access memory
  • Memory 210 can also be any other type of memory storage, capable of containing program instructions, such as a hard drive, a CD ROM, or flash memory.
  • processor 208 can either be a dedicated controller, an existing system processor, or it can be a dedicated digital signal processing (DSP) processor.
  • DSP digital signal processing
  • the instructions may be implemented using some form of a state machine.
  • the present invention provides a method Jo protect metal lines from corrosion and reaction after they have been formed on the wafer. Furthermore, the present invention provides a method of protecting metal lines, from corrosion and reaction, with a protective layer that does not suffer from comer cracks. Additionally, the present invention provides a method of protecting metal lines, from corrosion and reaction, with a protective layer that does not suffer from top cracks. Consequently, the present invention increases production yield and the field performance of the metal lines and the IC in which they are implemented, and ultimately increases the performance of the product.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A method of passivating a metal line without generating cracks. In one embodiment, the method comprises several steps. The first step is to receive a wafer with a metal line formed thereon. Next, the wafer temperature is increased and maintained to a deposition temperature. The deposition temperature is not more than approximately 400 degrees Celsius in the present embodiment. While at the deposition temperature, the metal line is passivated with a layer of oxide. Finally, the wafer is cooled to room temperature.

Description

A METHOD OF PASSIVATING A METAL LINE ON A WAFER
TECHNICAL FIELD
The field of the present invention pertains to semiconductor fabrication processes. More particularly, the present invention relates to the field of passivating metal lines located on a wafer without generating cracks.
BACKGROUND ART
The power and usefulness of today's digital integrated circuit (IC) devices is largely attributed to the increasing levels of integration. More and more components (resistors, diodes, transistors, and the like) are continually being integrated into the underlying chip, or Integrated Circuit (IC). The starting material for typical ICs is high purity silicon. The material is grown as a single crystal and takes the shape of a solid cylinder. This crystal is then sawed (like a slice of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick.
The geometry of the features of the IC components are commonly defined photographically through a process known as photolithography. Very fine surface geometry can be accurately reproduced by this technique. The photolithography process is used to define component regions and build up components one layer on top of another. Complex ICs can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer. The resulting topography of these complex ICs often resemble familiar terrestrial "mountain ranges," with many "hills" and "valleys" as the IC components are built up on the underlying surface of the silicon wafer.
A frequent component in an IC, produced on a wafer, is metal lines that couple the various other conducting and semi-conducting devices in the IC. Metal lines create excellent conductors. However, the typical metals utilized for the lines and vias are subject to corrosion and reaction to other chemicals and environments utilized for creating the IC. Consequently, a need exists to protect these metal lines from corrosion and reaction after the metal lines have been formed on the wafer.
Referring now to prior art Figure 1 , a conventional protective layer covering a metal line on a wafer is shown. Metal line 104, shown in a side view, is deposited on a wafer 102, and can extend in the Y-direction, or other directions. The conventional protective layer 106 covers metal line 104. Notably, the conventional protective layer process generates an undesirable corner crack 108a in protective layer 106. ^ This crack can compromise the integrity of the protective layer on the metal line, and thus increase the risk of corrosion and chemical reaction on metal line 104. The increased risk may ultimately cause a failure in the devices coupled to metal line 104 or in the IC containing the metal line. Consequently, a need arises to prevent corner cracks from occurring in the protective layer covering the metal line. One prior art solution to corner cracks, e.g. comer crack 108a, increased the thickness of the protective layer. However, this prior art solution had the effect of simply transferring the location" of the crack. Thus, instead of generating a corner crack, e.g. corner crack 108a, the prior art solution generated a crack on the top face of the protective layer, e.g. top crack 108b. The top crack is thought to be caused by the increased stresses on the protective coating from the metal line. In view of this problem, a need arises to prevent top cracks from occurring in the protective layer covering the metal line.
In summary, a need arises to protect metal lines from corrosion and reaction after the metal lines have been formed on the wafer. Furthermore, a need arises to prevent corner cracks from occurring in the protective layer covering the metal line. Finally, a need arises to prevent top cracks from occurring in the protective layer covering the metal line.
DISCLOSURE OF THE INVENTION
The present invention provides a method to protect metal lines from corrosion and reaction after the metal lines have been formed on the wafer. Furthermore, the present invention provides a method of protecting metal lines from corrosion and reaction with a protective layer that does not suffer from corner cracks. Additionally, the present invention provides a method of protecting metal lines from corrosion and reaction with a protective layer that does not suffer from top cracks.
Specifically, one embodiment of the present invention includes a method of passivating a metal line without gen rating cracks in the protective layer covering the metal line. In one embodiment, the method comprises several steps. The first step is to receive a wafer, with a metal line formed thereon, into a deposition chamber. Next, the wafer temperature is increased and maintained at a deposition temperature. The deposition temperature is not more than approximately 400 degrees Celsius in the present embodiment. While at the deposition temperature, the metal line is passivated by depositing a protective layer on the metal line. In the present embodiment, the protective layer is a high density heat plasma chemical vapor deposition (HDP CVD) silicon dioxide, SiO2. Finally, the wafer is cooled to room temperature. By controlling the wafer temperature at which the protective HDP CVD SiO2 layer is deposited on the metal line, the present invention avoids the generation of cracks in the protective layer. Following the deposition of the protective layer, the present invention provides a subsequent deposition of an additional protective layer, such as nitride, for added protection on the metal line.
Another embodiment of the present invention implements the method of providing a crack-free protective layer over a metal line using a processor and memory. The steps provided in the previous paragraph are implemented as data and instructions of the memory to be executed by the processor.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in, and form a part of, this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:
PRIOR ART FIGURE 1 is a side view of a conventional protective layer, with cracks, that cover a metal line on a wafer.
FIGURE 2 is a block diagram of a deposition chamber, in accordance with one embodiment of the present invention.
FIGURE 3 is a side view of a crack-free protective layer covering a metal line on a wafer, in accordance with one embodiment of the present invention.
FIGURE 4 is a flowchart of the steps performed to obtain a crack-free protective layer covering a metal line on a wafer, in accordance with one embodiment of the present invention.
The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted. BEST MODE FOR CARRYING OUT THE INVENTION
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary, skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions which follow, e.g. the processes, are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations, on data bits within a computer or digital system memory. These descriptions and representations are the means used by those skilled in the arts to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is herein, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these physical manipulations take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a processor. For reasons of convenience, and with reference to common usage, these signals are referred to as bits, values, elements, symbols, characters, terms, numbers, or the like with reference to the present invention.
It should be borne in mind, however, that all of these terms are to be interpreted as referencing physical manipulations and quantities and are merely convenient labels to be interpreted further in view of terms commonly used in the art. Unless specifically stated otherwise as apparent from the following discussions, it is understood that throughout discussions of the present invention, terms such as "receiving," "increasing," "maintaining," "passivating," "cooling," or the like, refer to the action and processes that can be implemented by an electronic computing device, that manipulates and transforms data. The data is represented as physical (electronic) quantities within the registers and memories of the device, and is transformed into other data sirrrtlarly represented as physical quantities within thejdevice components, or computer system memories or registers, or other such information storage, transmission or display devices.
Referring now to Figure 2, a block diagram of a deposition chamber 202 is shown, in accordance with one embodiment of the present invention. Deposition chamber 202 includes a wafer temperature controller 206, a processor 208, and a memory 210. The deposition chamber is adapted to accept a wafer 204 therein, for subsequent deposition operations. Processor 208 is coupled to memory 210 and to wafer temperature controller 206. Memory 210 is capable of storing data and instructions that can be executed by processor 208. Processor instructs other devices coupled to it, such as wafer temperature controller 206, to perform the appropriate instructions with the appropriate data, as supplied by memory 210.
Wafer temperature controller 206 of Figure 2 can be a controller that regulates the temperature of a back side of wafer 204, as shown in Figure 2. More specifically, wafer temperature controller 206 controls a cooling medium applied to wafer 204 such that a desired temperature range can accurately be reached and maintained. While the present embodiment utilizes helium as a cooling medium, e.g. a heat sink, the present invention is well-suited to using a wide variety of cooling mediums and a wide variety of methods to control temperature of wafer 204.
Memory 210 used in deposition chamber 202, for the present invention, can either be permanent memory, such as read only memory (ROM), or temporary memory sych as random access memory (RAM). Memory 210 can also be any other type of memory storage, capable of containing program instructions, such as a hard drive, a CD ROM, or flash memory. Furthermore, processor 208 can either be a dedicated controller, an existing system processor, a microprocessor, or some form of a state machine.
Referring now to Figure 3, a crack-free protective layer that covers a metal line on a wafer is shown, in accordance with one embodiment of the present invention. Metal line 304, shown in a side view, is formed on a wafer substrate 302 of wafer 204, and can extend in the Y-direction, or other directions. The first protective layer 306 covers metal line 304. Metal line 304 has a height 312 and a width 310. In one embodiment, metal line has a relatively large height 312 and
width 310 dimensions of 2 micrometers (μm). These dimensions, representing
conventional line dimensions, are difficult to cover with a protective layer using conventional deposition processes. First protective layer 306 has a thickness, T 314. In one embodiment, thickness T 314 is approximately 8,000 angstroms (A) thick.
Notably, the first protective layer of the present invention, as shown in Figure 3, is essentially free of cracks, e.g. free of top cracks 108b and comer cracks 108a such as those shown in prior art Figure 1. Because the present invention generates a crack-free first protective layer, e.g. layer 306, metal line 304 is essentially becoming corrosion and reactive resistant. In one embodiment, first protective layer 306 is an oxide layer. More specifically, oxide layer 306 is a High Density Pfasma (HDP) oxide layer in one embodiment. The present embodiment utilizes a deposition chamber to deposit the oxide layer, e.g. SiO2, onto metal line 304. More specifically, the deposition chamber is a High Density Plasma Chemical Vapor Deposition Chamber (HDPCVDC) in one embodiment.
Second protective layer 307, shown in Figure 2, is a nitride layer in one embodiment. However, the present invention is well-suited to having a second protective layer of a wide variety of materials. In an alternative embodiment, metal line is passivated with only first protective layer 306 and not with second protective layer 307. Second protective layer 307 can have a wide range of thicknesses, similar to those described for first protective layer 306.
While specific embodiments were described for Figure 3, the present invention is well-suited to using alternative embodiments. In one embodiment, first protective layer 306 is a material, other than an oxide, that is deposited using a HDP. In another embodiment, second protective layer 307 can be a material other than nitride. In yet another embodiment, no second protective layer 307 is utilized over first protective layer 306. Additionally, the deposition chamber utilized to deposit second protective layer 307 can be a chamber other than the HDPCVDC, especially if second protective layer deposited is a material other than a HDP oxide layer. While the present invention is applied to a metal line on a wafer, the present invention is well-suited to providing an oxide coating a line of any metallic composition on any type of platform.
Additional alternatives to the embodiments presented for Figure 3 include a metal line 304 having any value of height 312 and width 310. Additionally, the present invention is well-suited to creating a wide range of thickness, T 314 for first protective layer 306. In one embodiment, thickness T 314 is approximately 6,000 to 10,000 angstroms (A) thick. Furthermore, thickness T 314 can vary between the thickness at the top of the metal line and on the sides of the metal line. A benefit of the crack-free protective layer shown in Figure 3, is the improved corrosion protection offered to metal line 304. The improved corrosion protection, in turn, helps prevent failures in the devices arising from corrosion of metal lines. Consequently the yield of producing an IC increases, along with a corresponding unit cost decrease. Furthermore, reliability and performance of the final product is enhanced.
Referring now to Figure 4, a flowchart 4000 of the steps performed to obtain a crack-free protective layer covering a metal line on a wafer is shown, in accordance with one embodiment of the present invention. By using the flowchart 4000 embodiment of the present invention, a more corrosion-resistant protective layer can be provided over a metal line. Consequently, the present invention provides improved yield and performance of an Integrated Circuit (IC) device with metal lines. While the present embodiment implements flowchart 4000 in a deposition chamber, the present invention can be implemented in other types of devices.
Flowchart 4000 begins with step 4002. In step 4002 of the present embodiment, a wafer with a metal line is received. Step 4002 is implemented, in one embodiment, by the deposition chamber device shown in Figure 2.
Specifically, deposition chamber 202 can receive wafer 204 in an appropriate stage, not shown, that will securely retain wafer 204. Wafer 204 can be of the configuration shown in Figure 3, where wafer 204 has a metal line 304 formed on a wafer substrate 302. Alternatively, the present invention is well-suited to forming the metal line on the wafer, or other substrate, while in the deposition chamber. Furthermore, the present invention is well-suited to performing the process on any quantity of lines on a wafer. Following step 4002, flowchart 4000 proceeds to step 4004.
In step 4004 of the present embodiment, the wafer temperature is increased. Step 4002 is implemented, in one embodiment, by the deposition chamber device shown in Figure 2. Specifically, HDP ion bombardment of a wafer intrinsically provides sufficient energy to heat wafer 204 to a desired temperature, and beyond. However, the present invention is well-suited to supplementing the ion bombardment heating of the wafer in another embodiment. Following step 4004, flowchart 4000 proceeds to step 4006.
In step 4006 of the present embodiment, an inquiry determines whether the wafer temperature is at the deposition temperature. In one embodiment, the deposition temperature is between the> range of approximately 350 - 390 degrees Celsius. In another embodiment, the deposition temperature is approximately 370 degrees Celsius. The temperature inquiry of step 4006 can be accomplished by heat sensing devices, known in the art, and by using an analog circuit or digital circuit such as memory 210 and process 208 of Figure 2. That is, memory 210 can be programmed with the desired deposition temperature, within the range specified above, as appropriate for a given material to be deposited, and a given material to be protected. If the wafer temperature is at the deposition temperature, then flowchart 4000 proceeds to step 4008. However, if the wafer temperature is not at the deposition temperature, then flowchart 4000 returns to step 4004.
Step 4008 arises if the wafer temperature is at the deposition temperature, per the inquiry of step 4006. In step 4008 of the present embodiment, the wafer temperature is maintained at the deposition temperature. The deposition temperature is within the temperature range specified for step 4006. The present invention implements the step of maintaining the deposition temperature as previously described in the Figure 2 embodiment for step 4006. A feedback system for controlling temperature is exists with the components shown in Figure 2. In one embodiment, wafer temperature controller 206 helps to accurately maintain the temperature of the wafer to create a crack-free protective layer.
More specifically, one embodiment of implementing step 4008 controls the desired temperature range of the wafer using wafer temperature controller 206, memory 210, and processor 208 of deposition chamber 202 as shown in Figure 2. The present embodiment maintains the desired temperature range by moderating the intrinsic wafer heating from HDP ion bombardment with a controlled flow of a cooling medium to wafer 204. In the present embodiment, the cooling medium is a helium gas. However, the present invention is well-suited to using a wide range of cooling mediums and a wide range of methods to achieve the desired temperature range used for depositing the first protective layer. Furthermore, while the present embodiment implements step 4008 with digital circuitry, the present invention is well-suited to using analog apparatus. Following step 4008, flowchart 4000 proceeds to step 4010.
In step 4010 of the present embodiment, a first protective layer is deposited on metal line. In one embodiment, the first protective layer is an oxide layer. In another embodiment, the oxide layer can more specifically be chosen as a High Density Plasma (HDP) oxide layer. Step 4010 is implemented, in one embodiment, to produce the product shown in Figure 3, where first protective layer 306 is created on top of metal line 304. By using the temperature ranges specified in steps 4004 - 4008 of the present embodiment , the present invention produces a protective layer without cracks. Consequently, the present invention provides a robust protective layer over the metal line that prevents corrosion and reaction on the metal line. While the present embodiment describes the first protective layer as a specific material and configuration, the present invention is well-suited to the alternatives described for first protective layer 306 of Figure 2. Following step 4010, flowchart 4000 proceeds to step 4012.
In step 4012 of the present embodiment, an inquiry determines whether the first protective layer is at the desired thickness. In one embodiment, the first protective layer has a thickness of approximately 6,000 to 10,000 angstroms (A). In another embodiment, first protective layer has a thickness of approximately 8,000 angstroms (A). However, the present invention is well-suited to a wide-range of thickness for first protective layer. Step 4012 is implemented, in one embodiment, to produce the product shown in Figure 3, where first protective layer 306 has a thickness of T 314. The thickness of the first protective layer can be varied according to the specific application and corrosion resistance desired. While the present embodiment describes the first protective layer with a specific thickness and configuration, the present invention is well-suited to the alternatives thickness properties described for first protective layer 306 of Figure 2. If the first protective layer is at the desired thickness, then flowchart 4000 proceeds to step 4014. However, if the first protective layer is not at the desired thickness, then flowchart 4000 returns to step 4010.
Step 4014 arises if the first protective layer is at the desired thickness, per the inquiry of step 4012. In step 4014 of the present embodiment, a second protective layer is deposited onto the first protective layer. In one embodiment, the second protective layer is a nitride layer. In this embodiment, the nitride layer can be deposited to a wide range of thicknesses and applied over a wide range of temperatures. The absence of cracks in the first protective layer provides a stable and homogeneous layer upon which the second protective layer can be placed. Hence, the integrity of the first protective layer can actually increase the robustness of the operating tolerances used to apply the second protective layer. The present invention implements the application of a second protective layer using a deposition chamber, similar to the one shown in the Figure 2. In one embodiment for step 4014, deposition chamber 202 of Figure 2 is a Plasma Enhanced (PE) Chemical Vapor Deposition Chamber (CVDC) for depositing nitride. In one embodiment, an inquiry similar to steps 4004-4012 can be utilized for controlling the deposition of the second protective layer. However, these steps have been omitted from the present embodiment of the flowchart for purposes of clarity. Following step 4014, flowchart 4000 proceeds to step 4016.
In step 4016 of the present embodiment, the wafer is cooled to room temperature. Step 4016 is implemented, in one embodiment, by the deposition chamber 202 shown in Figure 2. In particular, cooling is achieved in the present embodiment by flowing a helium gas cooling medium to wafer 204, as controlled by wafer temperature controller 206. In another embodiment, the wafer may be cooled by convection or conduction. In another embodiment, wafer 204 may be removed from deposition chamber 202 to be cooled in another area by another device. In an alternative embodiment, the wafer may be transferred to another machine for subsequent operation, e.g. additional deposition of semiconductor material or photoresist layers, without having a cooling step. Following step 4016 flowchart 4000 ends. Additional steps used for vapor deposition and wafer handling operations, such as evacuation of the vapor deposition chamber, are well-known in the art. These steps have been omitted herein so as not to obstruct the salient features o| the present invention.
While flowchart 4000 of the present embodiment shows a specific sequence and quantity of steps, the present invention is suitable to alternative embodiments. For example, not all the steps provided for flowchart 4000 are required for the present invention. For example, an alternative embodiment of flowchart 4000 can omit steps 4014 and 4016 if a second protective layer is not desired or required for the metal line. Furthermore, additional steps may be added to the steps presented in the present embodiment. Likewise, the sequence of the steps can be modified depending upon the application. While flowchart 4000 is shown as a single serial process, it can also be implemented as a continuous or parallel process.
Many of the instructions for the steps, and the data input and output from the steps, of flowchart 4000 utilize memory 210 and utilize processor 208. The memory storage 210 for the present embodiment can either be permanent, such as read only memory (ROM), or temporary memory such as random access memory (RAM). Memory 210 can also be any other type of memory storage, capable of containing program instructions, such as a hard drive, a CD ROM, or flash memory.
Furthermore, processor 208 can either be a dedicated controller, an existing system processor, or it can be a dedicated digital signal processing (DSP) processor. Alternatively, the instructions may be implemented using some form of a state machine.
In view of the embodiments presented herein, the present invention provides a method Jo protect metal lines from corrosion and reaction after they have been formed on the wafer. Furthermore, the present invention provides a method of protecting metal lines, from corrosion and reaction, with a protective layer that does not suffer from comer cracks. Additionally, the present invention provides a method of protecting metal lines, from corrosion and reaction, with a protective layer that does not suffer from top cracks. Consequently, the present invention increases production yield and the field performance of the metal lines and the IC in which they are implemented, and ultimately increases the performance of the product. The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims

CLAIMSWhat is claimed is:
1. A method of passivating a metal line on a wafer in a deposition chamber, said method comprising the steps of: a) receiving said wafer in said deposition chamber, said wafer having said metal line formed thereon; b) increasing a wafer temperature around said wafer to a deposition temperature; c) maintaining said wafer temperature at said deposition temperature, said deposition temperature being greater than room temperature; d) passivating said metal line, on said wafer; and e) cooling said wafer to room temperature.
2. The method recited in Claim 1 wherein said deposition temperature is not more than approximately 400 degrees Celsius.
3. The method recited in Claim I or 2 wherein said step of passivating said metal line is accomplished by depositing an oxide layer on said metal line.
4. The method recited in Claim 3 wherein said oxide layer is a High Density Plasma (HDP) oxide layer.
5. The method recited in any one of Claims 2-4 wherein said deposition temperature is approximately 350 - 390 degrees Celsius.
6. The method recited in Claim 5 wherein said deposition temperature is approximately 370 degrees Celsius.
7. The method recited in any one of the preceding claims wherein said deposition temperature is maintained by applying a cooling medium to said wafer.
8. The method recited in Claim 7 wherein said cooling medium is a helium gas.
9. The method recited in any one of the preceding claims wherein said deposition chamber is a HDP Chemical Vapor Deposition (CVD) chamber.
10. The method recited in any one of Claims 3-9 wherein said oxide layer is approximately 6,000 to 10,000 angstroms (A) thick.
11. The method recited in Claim 10 wherein said oxide layer is approximately 8,000 angstroms (A) thick.
12. The method recited in any one of the preceding claims further comprising the step of: f) depositing a nitride layer onto said oxide layer.
13. The method recited in Claim 12 wherein said nitride layer is deposited with a Plasma Enhanced (PE) CVD chamber.
14. A deposition chamber for passivating a metal line on a wafer, said deposition chamber comprising: a processor; and a computer readable memory, said computer readable memory coupled to said processor, said computer readable memory containing program instructions stored therein that when executed over said processor implement a method for passivating a metal line on a wafer according to any one of the preceding claims.
PCT/US2001/010552 2000-04-07 2001-03-29 A method of passivating a metal line on a wafer WO2001078126A2 (en)

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Citations (3)

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Publication number Priority date Publication date Assignee Title
EP0310839A1 (en) * 1987-10-09 1989-04-12 STMicroelectronics S.r.l. A method of manufacturing monolithic integrated circuits
EP0884401A1 (en) * 1997-06-11 1998-12-16 Applied Materials, Inc. Method and system for coating the inside of a processing chamber
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EP0310839A1 (en) * 1987-10-09 1989-04-12 STMicroelectronics S.r.l. A method of manufacturing monolithic integrated circuits
EP0884401A1 (en) * 1997-06-11 1998-12-16 Applied Materials, Inc. Method and system for coating the inside of a processing chamber
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