WO2001071998A1

WO2001071998A1 - Clockless demodulation and word recognition system

Info

Publication number: WO2001071998A1
Application number: PCT/AU2001/000290
Authority: WO
Inventors: Christopher Devitt
Original assignee: Transcorp System Pty. Ltd.
Priority date: 2000-03-17
Filing date: 2001-03-15
Publication date: 2001-09-27
Also published as: AUPQ635800A0

Abstract

A clockless demodulation and word recognition system is disclosed. The system compares a delayed and undelayed digital data stream employing an XOR gate and a monostable flip-flop to provide an output indicative of the comparison to allow demodulation and word recognition.

Description

CLOCKLESS DEMODULATION AND WORD RECOGNITION

SYSTEM

This invention relates to a clockless demodulation and word recognition system.

The invention will be described in relation to data transmission systems. It should be appreciated that this is by way of example only and that the invention may be used for demodulation and word recognition in systems other than data transmission systems.

BACKGROUND ART

The extraction of information from a stream of digital data or digital line codes is required to allow processing of transmitted information. This process has required the extraction of the system clock frequency from the input data stream with the use of differentiation circuits and phase locked loop (PLL) circuitry. These types of circuits require a narrow range of input frequencies and a line code rich in transitions to stabilise the PLL. This also leaves the circuits prone to network jitter and slip which, if pronounced enough, cause errors in the clock recovery process. The clock errors translated into demodulation errors and as a consequence error in recovered data.

In communication system that employ main and redundant or protection bearers for the transmission of data it is usual for a variety of signals to be transmitted in addition to the digital data or to be indicated on the bearer. These signals include a loss of signal (LOS) data signal, an alarm insertion signal (AIS) data signal and a pilot signal. The LOS signal typically occurs when the bearer is open circuited and appears as no signal at the receive end of the bearer. The AIS signal is generated by line terminal equipment and typically is represented by a digital word consisting of a series of high logic levels. Data on the bearer appears as a sequence of low and high logic levels. A pilot signal on the bearer typically appears as an alternating sequence of high and low logic levels. SUMMARY OF INVENTION

It is an object of the invention to provide a clockless demodulation and word recognition system for a demodulating system. The system of the invention is particularly useful for recognition of continuously transmitted short duration data words which have been line coded during transmission.

According to one aspect, the invention provides a clockless demodulation and word recognition system including a first and a second buffer each for receiving a data stream, a first delay line coupled to an output of the first buffer, the delay line delaying the data stream by a time equal to the duration of one of the bits in the data stream, a first exclusive OR gate (XOR) receiving as its inputs the output from the first delay line and the output from the second buffer, a first monostable flip-flop receiving at its clock input the output from the first XOR gate and a timing network coupled to a timing input of the first monostable flip-flop for resetting the first flip-flop if a time period provided by the timing network is exceeded.

The system of the invention may distinguish between data signals (or a pilot signal) and an AIS signal. The system as described above may provide this distinction for a unipolar data stream.

Where the data stream is bipolar the system of the invention may still be used but first the bipolar data stream must be converted into a unipolar data stream. To achieve this, the bipolar data may be coupled to an input buffer amplifier and the output from the amplifier may be applied to inputs of a comparator via a first rectifier with its anode connected to the input buffer output and its cathode connected to a first input of the comparator and a second rectifier with its cathode coupled to the output of the input buffer and its anode coupled to a second input of the comparator. The output of the comparator will be unipolar pulses which may then be coupled to the first and second buffer of the system of the invention.

Preferably the system of the invention includes a second delay line in series with the first delay line which delays pulses applied to it by a time equal to the duration of one of the bits in the data stream.

The delay line/s may either be analogue or digital delay lines.

A second exclusive OR gate (XOR) may receive as its inputs the output from the second delay line and the output from the second buffer. A second monostable flip-flop has its clock input coupled to the output of the second XOR gate. This second flip-flop has a timing network coupled to a timing input to allow the flip-flop to reset if the period of the timing network is exceeded. The outputs available at the second flip-flop, outputs Q and its complementary output, allow AIS signals and PILOT signals to be distinguished from data signals.

The use of two delay lines, two flip-flops and two XOR gates allow four outputs to be obtained from which signals such as AIS, LOS, PILOT and data signals may be distinguished from one another.

BRIEF DESCRIPTION OF THE DRAWINGS

A particular preferred embodiment of the invention will now be described by way of example with reference to the drawings in which:

Figure 1 is a block diagram of a clockless demodulation and word recognition system of a preferred embodiment of the invention; and, Figure 2 is a view of a logic diagram useful in understanding the operation of the system of Figure 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Figure 1 shows a block diagram of the clockless demodulation and word recognition system of a preferred embodiment of the invention. A bi-polar line code is applied as an input to the inputs to buffer amplifier D1. Amplifier D1 has a fixed gain of 10 dB and a bandwidth of 200 MHz. The output of this fixed gain amplifier D1 is split and rectified by diodes D9 and D10. The diodes are coupled to inputs of a high speed differential comparator D2. The output from the comparator O2 are unipolar pulses.

Thus, the circuitry from amplifier D1 through to comparator D2 is effective in converting bi-polar pulses into unipolar pulses. The output from the high speed differential comparator D2 is applied to two unity gain buffers D3 and D4. The buffers D3 and D4 act as a delay equalizer between the comparator D2 and the remainder of the circuit illustrated in the figure. The output from buffer D3 is applied as an input to a digital delay line T1. The delay line T1 delays the data stream applied to it by a time equal to the duration of one of the bits in the data stream. The output from digital delay line T1 and the output from buffer D4 are applied as inputs to exclusive OR gate (XOR) 06. Monostable flip-flop D8 receives at its clock input, the output from XOR gate D6. A timing network TN is coupled to a timing input of flip-flop D8.

XOR gate D6 carries out a bit by bit comparison of the data from the digital delay line T1 and the data from buffer D4. If the two data streams are equal then the resultant output from XOR gate D6 will be a logic level "0". This is illustrated in Figure 2 at D in the D6 output trace. This signal, when applied to the clock input of flip-flop D8 will allow the flip-flop to reset if the period "D" exceeds the window period determined by the timing network TN. If the two data streams are not identical, that is to say, if successive bits are not the same value then the output at the XOR gate D6 will be a logic "1". This is illustrated in Figure 2 at F. This ensures that the monostable flip-flop D8 remains triggered and the level at "output 2" will be a logic "0".

The one bit delayed signal at the output of digital delay line T1 is applied to a second digital delay line T2 and delayed by one further bit time. The output from digital delay line T2 and the buffered undelayed signal at the output from buffer D4 are applied as inputs to a second exclusive OR gate (XOR) D5. XOR gate D5 undertakes a bit by bit comparison of the data from the digital delay line T2 and the data at the output of buffer D4. If these two streams are equal then the resultant output from XOR gage D5 is a logic "0". This is illustrated in Figure 2 at "E" and "G". The output available from XOR gate D5 when applied to monostable flip-flop D7 will allow the flip-flop to reset if the periods "E" or "G" exceed the window period determined by the timing network TN shown in Figure 1. If the data streams are not identical, that is to say, if successive bits are not the same value then XOR gate D5 will output a logic "1". This is illustrated in Figure 2 at "J". This ensures that the monostable flip-flop D7 remains triggered and the level at "output 1" in Figure 1 will be a logic "0". By the use of combinations of "output 1", "output 2", "output 3" and "output 4" in logic gates it is possible to demodulate and recognise the reception of certain repetitive digital words. If the timing networks TN are set to be equivalent of three bit times and "output 1" is logically ANDED with "output 2" the circuit recognises the sequence W1 shown in figure 2. If "output 2" and "output 3" are logically ANDED, the circuit demodulates and recognises digital word W2 shown in Figure 2.

From the description of the circuit shown in Figure 1, it will be seen that clock extraction is not required for the demodulation and recognition of cyclically transmitted digital words. Since there is no internal clock, there is no requirement for synchronisation of system and internal clocks. In addition, since the circuit splits the data stream and compares successive bits, network jitter and slip introduced during transmission of data has no effect on the demodulation process of the system of the invention.

The circuit is able to demodulate any constant bit rate signal by setting the delay of the digital delay lines T1 and T2 to the required bit times. The addition of more delay elements, XOR gates and monostable flip-flops allows the circuit to recognise longer and more complex words than those shown by way of example as digital words W1 , W2 and W3 in Figure 2 of the drawings. The delay lines may be analogue or digital delay lines. The system of the invention may be implemented using discrete integrated circuits and components. Alternatively, the system may be realised employing a programmable logic circuit or a programmable gate array.

Claims

1. A clockless demodulation and word recognition system including a first and a second buffer each for receiving a data stream, a first delay line coupled to an input of the first buffer, the delay line delaying the data stream by a time equal to the duration of one of the bits in the data stream, a first exclusive OR gate (XOR) receiving as its inputs the output from the first delay line and the output from the second buffer, a first monostable flip-flop receiving as its clock input the output from the first XOR gate and having a timing network coupled to a timing input of the first monostable flip-flop for resetting the first flip-flop if a time period provided by the timing network is exceeded.

2. The system of claim 1 including converting means coupled to the first and second buffers for converting a bi-polar data stream into a unipolar data stream and for applying the unipolar data stream to inputs of the buffers.

3. The system of claim 2 wherein the converting means includes an amplifier, reverse connected rectifiers coupled to the output of the amplifier and a comparator having inputs connected to the rectifiers and providing a unipolar output for connection to the first and second buffers.

4. The system of claim 3 wherein the amplifier has a gain of 10dB and a bandwidth of 200 MHz.

5. The system of claim 3 or 4 wherein the comparator is a high speed differential comparator.

6. The system of claim 1 including a second delay line for delaying a data stream by a time period equal to the duration of one of the bits in the data stream, the second delay line being in series with the first delay line, a second XOR gate receiving as its inputs the output from the second delay line and the buffered output from the second buffer and a second monostable flip- flop having a timing network coupled to a timing input and having the output of the second XOR gate coupled to its clock input.

7. The system of claim 1 implemented using discrete integrated circuits and discrete components.

8. The system of claim 1 implemented employing a programmable logic circuit.

9. The system of claim 1 implemented employing a programmable gate array.