WO2001061700A1

WO2001061700A1 - Information reproducing device

Info

Publication number: WO2001061700A1
Application number: PCT/JP2000/000890
Authority: WO
Inventors: Hiroshi Ide; Hideki Shimizu; Takashi Nara
Original assignee: Hitachi, Ltd
Priority date: 2000-02-17
Filing date: 2000-02-17
Publication date: 2001-08-23
Also published as: JP3841683B2

Abstract

When, from an information signal (26) including alternating pulses of positive and negative polarities and of multiple kinds of pulse spacing, channel data (28) on a bit stream corresponding to the pulse spacings is reproduced, a detecting gate (19) and a decoder (20) detect the ideal waveform most approximate to the pulse waveform or pulse spacing of the information signal based on the difference between the quantized data quantized by an ADC (18) and ideal waveform information with respect to the positive- and negative-polarity pulses. That is, the pulse spacings of the alternating pulses in the information signal are detected by selecting the ideal waveform most approximate to the waveform of the information signal. Bit streams conforming to the detected ideal waveform are sequentially converted into a predetermined format and outputted as channel data. Therefore, detecting the peak of the information signal is not required. Further no PLL circuit for reproducing a synchronizing clock from the information signal (26) is required. Thus, any burst error caused by an increase in recording density and track density of a magnetic disk and an increase in data transfer rate due to high speed access is prevented.

Description

Description Information playback device Technical field

The present invention relates to an information reproducing apparatus or a disk drive apparatus that reproduces information from a signal indicating the alternating property of a rising polarity pulse and a falling polarity pulse. For example, the present invention relates to a method for recording run-length encoded channel data in a magnetic storage device. Regarding effective technology applied to reproduction. Landscape technology

In magnetic storage devices such as hard disk drives, user data is encoded into channel data as run-length encoded data and recorded on the disk as magnetic transitions. When recording a magnetic transition, the run length is specified using a fixed frequency clock signal period. The read signal of the recorded information by the magnetic head is a signal having alternating polarity of a rising polarity pulse and a falling polarity pulse having several kinds of pulse intervals defined in advance. To reproduce channel data from the read signal, the clock signal is reproduced based on the read signal, and the channel data is reproduced based on the relationship between the phase of the reproduced clock signal and the pulse width of the read signal. To play.

A PLL circuit can be used to reproduce the clock signal. That is, a read signal by the magnetic head is supplied to the PLL circuit to reproduce the clock signal. For example, in a magnetic storage device, a PLL pull-in pattern such as 101010 ... is written at the head in several bytes for each sector (unit of read data block of 512 bytes). Phase lock It is designed so that it can be easily performed.

However, the noise resistance of the PLL circuit is limited, and the PLL circuit is unlocked in a noisy signal state. Loss of lock of the PLL circuit is called a burst error, and the read channel will output all incorrect data from the time of the burst error. Normally, in a hard disk device, the data output from the read channel can be corrected by an ECC (Error Check and Correct) circuit, but this can only correct a few bytes of errors in one sector, and the There is no function to correct the de-evening that caused the problem. For this reason, the section in which the burst error occurred must be read again by retry, which degrades the data access performance of the hard disk drive.

In addition, considering that the information recording density and track density of a recording disk in an information reproducing device such as a hard disk device increase and that high-speed access is considered, a PLL circuit operating from 500 MHz to 1 GHz or more in the future will be considered. However, it is expected that designing such a high-speed PLL circuit itself will be difficult.

If the noise resistance of the PLL circuit is low, the logical value of the sampling data is determined 1/0 in synchronization with the clock signal at the subsequent stage.PRM L (Partial

Response Maximum Likelihood (Bi-Decoder) format Even if the decoder is capable of correctly judging data even under conditions of poor S / N (Signal / Noise), it is possible to input data with large noise. The possibility of burst error cannot be avoided.

Japanese Patent Application Laid-Open No. 9-120464 discloses a data recovery circuit with improved resistance to jitter. In this method, peak detection is performed on a signal, the interval between peaks is measured, 1, 0 patterns corresponding to the measured values are obtained from a look-up table, and run-length encoded data is reproduced. Also It is. Although this technology does not use a PLL circuit, it must detect the peak of the signal to be reproduced. In this peak detection, noise is likely to be regarded as a peak if the signal frequency is high, and in this regard, noise immunity is considered to be limited.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an information reproducing apparatus E capable of detecting a pulse interval of an input signal without using a reproduced clock signal by a PLL circuit and without detecting a peak for a human input signal. It is in.

Another object of the present invention is to improve the noise immunity of the information reproducing device that “reports” from the β signal, which makes the exchange between the rising polarity pulse and the falling polarity pulse.

Another II aspect of the present invention is to capture the S that can reliably generate run-length coded channel data for a high data rate i. .

Another purpose of the present invention is to provide an ecology report that is less likely to cause a burst error.

The above and other objective and novel features of the present invention will be apparent from the following description of this specification and the accompanying drawings.

Inquiry of invention

The information generator or the semiconductor device according to the present invention is configured such that a rising polarity pulse and a falling polarity pulse are alternated, and a channel of a bit train corresponding to the pulse interval is obtained from an information signal having a plurality of types of pulse intervals. A device that reproduces data. This information reproducing apparatus has ideal waveform data output means for outputting ideal waveform data for representing an ideal waveform relating to the rising polarity pulse and an ideal waveform relating to the falling polarity pulse for each pulse interval. Sampling or quantizing the signal The clock signal for sampling by the converting means is, for example, a clock signal having a cycle corresponding to the sampling point pitch of the ideal waveform data. This clock signal may be asynchronous with the information signal, does not need to be a clock signal recovered from the information signal, and does not require a PLL circuit for clock recovery. The pulse interval of the alternating pulse included in the information signal is detected by selecting the ideal waveform closest to the waveform of the information signal. That is, based on a difference between the data converted by the conversion means and each ideal waveform data output from the ideal waveform data output means, a waveform of an ideal waveform approximate to a pulse waveform or a pulse interval of the information signal is detected. It will be determined sequentially by means. Therefore, peak detection of the information signal is not required. In the waveform detection means, a bit string corresponding to the pulse interval of the ideal waveform determined sequentially is output. This bit string is cut out into channel data of a predetermined number of bits by channel data output means and output to the subsequent stage.

When determining the presence or absence of a pulse at every unit time or one bit for a pulse, the force required to increase the sampling point by a PLL circuit is required. Since the pulse interval of the alternate pulse included in the information signal is detected by the vehicle that selects the processing waveform that approximates the pulse interval, it is not essential to increase the sampling point accuracy. Therefore, it is not necessary to use a PLL circuit for reproducing the synchronization clock from the information signal.

A clock signal that is asynchronous with the information signal is different from a reproduced clock signal reproduced from the information signal in that the waveform detection means is configured to compensate for the effect of causing an error in frequency and phase in terms of frequency and phase. It is desirable to

First, the waveform detection means can be constituted by a data input buffer, a calculation means, a correlation buffer, and a tracking control means. One The evening input buffer has in series latch circuits of two or more stages larger than the maximum number of pulse intervals, and each latch circuit performs a latch operation in synchronization with a clock signal and is converted to the first stage by the conversion means. Enter the date. If the number of stages of the latch circuit is larger than the maximum number of pulse intervals by two or more, the sampling data that is continuous over the range in which the pulse polarity can be determined for the input data of the maximum pulse interval. Can be latched to a plurality of latch circuits of the data input buffer and output in parallel. The arithmetic means is configured to calculate each ideal waveform for the pulse waveform of the information signal based on a difference between data of each ideal waveform output from the ideal waveform data output means and latch data output in parallel from the plurality of latch circuits. Is calculated in synchronization with the clock signal. The correlation buffer can sequentially shift and hold the correlation data calculated by the calculation means by at least the number of clock signal cycles corresponding to the maximum value of the pulse interval. For example, if the maximum value of the pulse interval is m, the correlation data buffer having m consecutive correlation data for each ideal waveform will have a similarity for each pulse interval held by the information signal. A state censorship will appear. From this viewpoint, the tracking control means extracts the correlation data indicating the most similar state among the correlation data relating to the pulse of one polarity held in the correlation data buffer, and extracts Waiting for the correlation data buffer to be shifted in the correlation data buffer by the pulse interval of the ideal waveform corresponding to the calculated correlation data, the state of the correlation data that most closely approximates the pulse of the other polarity is determined. And the process of extracting the correlation data shown in FIG. Since the extraction of the correlation data by the tracking control means can be performed within a predetermined range that is temporally before and after in the correlation data buffer, the frequency error between the asynchronous clock signal and the reproduced clock signal is obtained. However, there is no substantial effect on the extraction of the closest ideal waveform data.

Secondly, the ideal waveform data output means separately outputs data in which the sampling points of the ideal waveform data are shifted by half a bit from each other at every pulse interval of the rising polarity and the falling polarity. Since the phase difference of the asynchronous clock signal with respect to the reproduced clock signal is 180 ° at the maximum, if the ideal waveform data is prepared in consideration of this, the reproduced clock signal is converted into an asynchronous clock signal. Even if a phase difference occurs with the clock signal, it does not substantially affect the extraction of the closest ideal waveform data.

The conversion means includes an A / D conversion circuit that converts the information signal into a digital signal in synchronization with a clock signal, or a sample and hold circuit that samples and holds the information signal in synchronization with a clock signal. In the former case, the waveform detection means may be constituted by a digital circuit. A digital signal processor may be used as the digital circuit. In the latter case, the waveform detecting means may be constituted by an analog circuit.

When the information signal is a read signal from a disk, if a frequency synthesizer for generating a synchronization signal of information to be written to the disk is provided, it is preferable to use a signal output from the frequency synthesizer as the clock signal. This makes it possible to easily reduce the frequency error between the asynchronous clock signal and the regenerated clock signal. The information reproducing device can be applied not only to a device for reproducing a read signal from a disk, such as a hard disk device, but also to a communication control device for receiving the information signal from a transmission medium. As one means for reducing the error rate of information reproduction, it is preferable to provide an ECC circuit that enables error checking and correction for the channel data output from the channel data output means. Since the conversion means asynchronously samples the information signal, even if the data converted by the conversion means is stored in the buffer memory in a relatively large unit such as one sector, the data is not wasted later. Absent. When using a PLL circuit, if the lock of the PLL circuit comes off, even if the data is stored in a buffer, the data cannot be used later.

If a buffer memory for storing the data converted by the conversion means is provided and the data extracted from the buffer memory is supplied to the waveform detection means, the processing conditions in the waveform detection means can be changed. By performing the processing a plurality of times, the error i correction ability can be improved. For example, ι) 恕恕波形波形段段段有し段有し段段段段段段段段段段段段段段段段段段段段段Classes shall be switchable when the ECC circuit detects an uncorrectable error for the channel data. At this time, it is not necessary to read the giant signal from the disk, and it is sufficient to perform the memory access to the buffer memory.

In order to cancel the memory access time at that time, ideal waveform data and other conditions are preliminarily changed. Waveform detection τ · stages are provided in several stages, these are operated in parallel in advance, and output is performed according to error conditions. You just have to select That is, at least a plurality of sets of processing means including the ideal waveform data output stage, the ¾ϊ means, the data buffer, the tracking control means, and the channel data output means are provided so as to operate in parallel. In addition, a selector for selecting the channel data output means included in the processing stages of each of the following and selecting the output of the selected channel data output means, and the output from the channel data output means selected by the selector. An ECC circuit is provided to enable error checking and correction for channel data. The selector switches the selection state when an uncorrectable error in the channel by the ECC circuit is detected. Made interchangeable.

The ideal waveforms output by the ideal waveform data output means included in each of the processing means are different data determined under the assumption of different use conditions relating to, for example, use atmosphere temperature and pressure. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram illustrating a read channel of a hard disk device to which an information reproducing apparatus according to the present invention is applied.

FIG. 2 is a logic circuit diagram showing a specific example of the detection gate circuit.

FIG. 3 is an explanatory diagram showing an example of ideal waveform data together with FIG.

FIG. 4 is an explanatory diagram showing an example of ideal waveform data together with FIG.

FIG. 5 is a logic circuit diagram showing a specific example of a decoder receiving the output of the detection gate.

FIG. 6 is an explanatory diagram illustrating an expression format of the correlation data held in the correlation buffer.

FIG. 7 is a flowchart schematically showing a processing procedure by the minimum path tracking control circuit.

FIG. 8 is a flowchart showing a specific example of processing by the minimum path tracking control circuit.

FIG. 9 is an explanatory diagram showing an operation example of the channel data output circuit. FIG. 10 is a block diagram showing an example in which a channel data reproducing circuit is mainly composed of an analog circuit.

FIG. 11 is a block diagram showing an example in which a channel data reproducing circuit is configured to be capable of performing software processing.

FIG. 12 is a block diagram showing an example having a buffer memory for storing quantized data. FIG. 13 is a block diagram showing an example in which the present invention is applied to a communication control device that receives an information signal from a transmission medium. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 illustrates a hard disk device to which the information reproducing apparatus according to the present invention is applied and its read channel.

The hard disk drive includes: a magnetic disk 1 on which ti information is recorded; a head 2 for writing / reading to / from the magnetic disk 1; and a semiconductor for controlling a signal from the head 2 and a signal to the head 2. An integrated read / write amplifier 3, a semiconductor integrated read / write channel 4 that performs write and read signal processing, and an error check and error correction of data reproduced in the read channel 4 are possible. A hard disk controller (HDC) 6 with a built-in ECC circuit 5, work memory 7, drive system control circuit 8, and a disk drive 9 under the control of the drive system control circuit 8 It consists of a power transistor circuit (C〇Μ Β〇) 11 etc. that drives the head module 10 etc. of the head assembly _(the hard disk controller 6 is not shown) Interfaced with host device.

When writing to the magnetic disk 1, the user data output from the hard disk controller 6 is encoded into the channel data as run-length encoded data by the encoding circuit 13 of the read channel 4, and the read amplifier 3 And via the head 2 to the magnetic disk 1 as magnetic transitions. When writing the magnetic transition, the run length is specified using a clock signal cycle of a fixed frequency, and the clock signal is a synchronization signal of the coding circuit 13. For example, if the frequency synthesizer 14 of read channel 4 is used as the clock signal 24, Use the one generated by

At the time of reading, the read waveform is read from the disk 1 by the head 2 and amplified by the read-amplifier 3, converted by the read channel 4 into the original data and output to the hard disk controller 6. That is, the read signal of the recording information by the head 2 has a rising polarity (hereinafter referred to as positive polarity) pulse and a falling polarity (hereinafter also referred to as negative polarity) having a plurality of types of pulse intervals defined in advance. ₍ Read channel 4 reproduces the channel data from the read signal. At this time, read channel 4 uses a PLL circuit to reproduce the clock signal from the read signal.) No. The error generated in the read channel 4 can be corrected by the ECC circuit 5. The drive system control circuit 8 controls the rotation of the magnetic disk 1 and the position of the head 2.

The read channel 4 includes an automatic gain controller (AGC) 16, a filter 17, and an A / D conversion circuit (ADC) 18 in addition to the coding circuit 13 and the frequency synthesizer 14. , A detection gate circuit 19, a decoder 20, a code decoding circuit 21, and a servo circuit 22.

The AGC 16 controls the amplitude of the reproduced waveform signal output from the read-write amplifier 3 at a constant level, and the filter 17 narrows down the frequency spectrum to within the Nyquist frequency and reduces the frequency noise component. Perform cutting, etc. The ADC 18 asynchronously samples and quantizes the output of the filter. The number of quantization bits is, for example, 6 bits. Here, “asynchronous” means that a clock signal is not reproduced from a signal input to the ADC 18 using a PLL circuit or the like, and sampling is not performed in synchronization with the reproduced clock signal. The sampling clock signal of the ADC 18 is, for example, the clock signal 24 generated by the frequency synthesizer 14 and the same as the clock signal used for the conversion. Since the reproduced waveform signal is an alternating waveform signal of a positive polarity pulse and a negative polarity pulse, the output data 27 of the ADC 18 quantized by the asynchronous sampling is a data train whose value rises and falls for each pulse. Become. The detection gate circuit 19 detects and analyzes the vertical relationship of the data train, and does not perform processing for accurately determining the position of a pulse by detecting the peak of each pulse.

The detection gate 19 and the decoder 20 perform the above-mentioned reporting based on the difference between the data sampled and converted by the ADC 18 and the ideal waveform data of the positive pulse and the negative pulse. Signal (meaning the filter output waveform input to ADC 18 here) 26 The pulse waveform (or pulse interval) of 26 is ideally determined to be the closest approximation to the ideal waveform, and the determined ideal It implements waveform detection means that forms a bit string that corresponds to the pulse interval of the waveform. That is, the waveform detection stage detects the pulse interval of the alternating Φ pulse included in the 'report ^ 26' by a car that selects the ideal waveform closest to the waveform of the report 26. The detection gate 19 synchronizes the clock signal 24 with the clock signal 24 as a scale to indicate whether the pulse waveform or pulse interval of the signal signal 26 or the pulse interval is close to any desired waveform. Generated every cycle. The decoder 20 holds the correlation data for a plurality of cycles of the clock signal 24 in the correlation buffer while shifting the correlation data for each ideal waveform, and pulses the held correlation data in a pulse. The smallest one is extracted for each polarity of, and a bit string corresponding to the pulse interval of the sequentially extracted ideal waveform is output as channel data (decoder output) 28. The code decoding circuit 21 converts the channel data 28 supplied from the decoder 20 into a user data format.

FIG. 2 shows a specific example of the detection gate circuit 19. Here, the pulse interval included in the information signal 26 is 1 to 5 for each polarity, There are 0 types. This is assumed in the following specific examples. The detection gate circuit 19 has a data input buffer 30 and waveform detection circuits WD1 to WD10.

The data input buffer 30 has two or more stages, for example, eight stages of latches FF1 to FF8 larger than the maximum number of pulse intervals (= 5) in series, and each of the latches FF1 to FF8 has The latch operation is performed in synchronization with the clock signal 24, and the data 27 converted by the ADC 18 is input to the first stage. Although the data is shown as one bit in the figure, as described above, data 27 is 6 bits, and it should be understood that each component has a configuration corresponding to 6-bit parallel processing. . Here, the number of stages of the latch circuits F F1 to F F8 is eight, which is three times larger than the maximum inter-pulse interval (= 5). This corresponds to the fact that the number of data (the number of sampling points for the ideal waveform) in the ideal waveform with pulse interval 5 is eight. If the number of stages of the latch circuits FF1 to FF8 is at least two times greater than the maximum number of pulse intervals (= 5), the pulse polarity can be determined for input data at the maximum pulse interval. This is because continuous sampling data can be latched to a plurality of latch circuits of the data input buffer 30 and output in parallel.

The waveform detection circuits WD1 to WD10 are connected to ideal waveform data buffers DB1a to DB10a, DB1b to DB1Ob as ideal waveform data output means, and arithmetic circuits EX1 to EX10. Have.

The ideal waveform data buffers 081 & to 0810 &, 0811) to 0810b store the ideal waveform data of the positive polarity pulse and the negative polarity pulse at every pulse interval and half-bit the sample points of the ideal waveform data with each other. Stagger and hold separately. The sampling point pitch of each ideal waveform is almost coincident with the period of the peak signal 24. In other words, the ADC 18 is The information signal 26 is quantized in synchronization with a clock signal 24 having a cycle corresponding to the sampling point pitch of the ideal waveform.

An example of the ideal waveform data is shown in FIGS. 3 and 4, in which (A) to (E) show an ideal waveform with a pulse interval of 1 to 5 and its sequence. The points marked with 〇 discretely on the ideal waveform mean the ideal waveform data. The left column of each of the above (A;) to (E) shows the data of the positive polarity pulse, the right column shows the data of the 1¾ polarity pulse, and the sample pitches in the upper and lower columns of (A) to (E) respectively. It is shifted by a half pitch (180 °). Pit shown in FIGS. 3 and 4 is the pulse interval. Although not particularly limited, each ideal waveform is considered to be data having two sampling points before and after a point included in a pulse interval, and an ideal waveform related to an ideal waveform with a pulse interval of 1. The data has four data points, and each time the pulse interval increases, the data point increases by one.

The reason why a sample pitch shifted by a half pitch is prepared as ideal waveform data is as follows. Since the phase difference of the asynchronous clock signal 24 with respect to the reproduced clock signal reproducible from the broadcast signal is a maximum of 180 °, if the ideal waveform data is prepared in consideration of this, the asynchronous This is because even if a phase difference occurs between the clock signal 24 and the raw clock signal, it does not substantially affect the extraction of the most similar ideal waveform data. The ideal waveform data buffer DBla to DB10a, DBlb to DB

10b outputs the corresponding ideal waveform data shown in FIG. 3 and FIG. 4 in parallel with the arrangement of each sampling point. For example, the ideal waveform data buffer DB1a outputs the ideal waveform data D1 to D4 in parallel as illustrated in FIG. 2 and FIG.

The arithmetic circuits EX 1 to EX 10 are provided with the ideal waveform data buffers DB 1 a to D

Each ideal waveform output from B 10a, DB lb to DB 10 b Correlation data S (1) indicating the approximate state of each ideal waveform with respect to the pulse waveform of the information signal based on the difference from the latch data output in parallel from the latch circuits FF1 to FF8 of the data input buffer 30. Calculate ~ S (10). For example, in the arithmetic circuit EX 1 whose details are exemplified, the ideal waveform data buffer DB 1 a has four arithmetic circuits each for calculating the difference between its output and the corresponding latch circuits FF 1 to FF 4. And the three adders ADDa for sequentially adding the outputs of the four squarers MULa and the squarer MULa for squaring the output of the subtractor SUBa. Similarly, the outputs of the four subtractors SUB b and S UB b that calculate the difference between the output of the ideal waveform data buffer DB 1 b and the outputs of the corresponding latch circuits FF 1 to FF 4 are provided on the side of the ideal waveform data buffer DB 1 b. It has three adders ADDb for sequentially adding the outputs of the four squarers MULb and MULb squared. According to this example, the smaller the value of the addition result by the adders ADDa and ADDb, the closer the input is to the ideal waveform. The conversion result obtained by the adder ADDa and the addition result obtained by the adder ADDb are compared by a comparator CMP, and the smaller addition result is selected by the selector SEL based on the comparison result, and is selected. The added result is output as correlation data S (1). Although the details of the other arithmetic circuits EX2 to EX10 are not particularly shown, the input from the data input buffer 30 is sequentially increased one by one with respect to the arithmetic circuit EX1, and the subtraction circuit SUB a , SUBb, squarers MULa, MULb, and adders ADDa, ADDb are sequentially increased in pairs.

FIG. 5 shows a detailed example of the decoder 20. The decoder 20 has a correlation data buffer RDB, a minimum path tracking control circuit LPS, and a channel data output circuit SRB.

The correlation data buffer RDB stores the correlation data calculated in the detection gate 19. Evening S (1) to S (10) are input to the first stage, and sequentially shifted in synchronization with the clock signal 24 to be held while being shifted. It has a book shift registry. The correlation buffer RDB calculates the correlation data S (1) to S (10) calculated by the detection gate 19 by using the clock signal 24 corresponding to the maximum value 5 of the pulse interval. It can be shifted and held sequentially for five cycles.

The correlation data held in the correlation data buffer RDB is represented as S (1,1) to S (10,5) as illustrated in FIG. The correlation buffer RDB outputs five correlation data that last for five cycles of the clock signal 24 to each ideal waveform ©, so the pulse of the ^ ffi signal at that time is stored in the data buffer RDB. Depending on the interval, data that takes a small value 1¾] will always appear. In short, since the S value of the pulse interval of the signal is 5, the correlation data S (l, 1) to S (10, 5) for 5 clock cycles is always one small. There is a time to become, and this is held by the correlation data buffer RDB.

As shown in Fig. 5, the S small path tracking control circuit LPS calculates the correlation data—the 50-phase of the chest held by the buffer RDB | the data S (1, 1) to S (1 0 , 5) in parallel.

Fig. 2 shows the processing procedure of the minimum path tracking control circuit LPS in a categorical manner. The minimum path tracking control circuit LPS extracts the ritual data showing the smallest value among the correlation data of the pulses of one polarity held in the correlation data buffer RDB. For example, the correlation data S (m, n) in FIG. 7 is extracted. Since the ideal waveform corresponding to the extracted correlation data S (m, n) can be considered to be included in the †, report signal at that time, the pulse interval (detection After several clock cycles, the ideal pulse for the next polarity reversal This makes it possible to specify a loose waveform. Therefore, after the correlation data is shifted in the correlation data buffer RDB by the detection pulse interval of the ideal waveform corresponding to the extracted correlation data S (m, n), the pulse of the other polarity is waited. A process is performed to extract the correlation data S (i, j) having the smallest value in the correlation data for. By repeating the process of extracting the minimum correlation data, the minimum correlation data is obtained. Since the extraction of the correlation data by the minimum path tracking control circuit LPS is performed within a data range of three clock cycles (3 cyc) that is temporally successive in the correlation data buffer RDB, the asynchronous clock signal and the reproduced clock signal are used. Even if the frequency error exists between the two, it does not substantially affect the extraction of the most approximated ideal waveform data.

The minimum path tracking control circuit LPS outputs a bit string corresponding to the pulse interval of the ideal waveform sequentially determined as described above. The bit string is determined in advance in accordance with the pulse interval of the ideal waveform, and is not particularly limited. However, as illustrated in FIGS. 3 and 4, when the pulse interval is 1, "1" "2" is "0 1", "Pulse interval 3" is "00 1", "Pulse interval" 4 is "000 1", and "Pulse interval 5" is "0000 1". You. In short, the number of logical values "0" inserted before the logical value "1" is determined according to the pulse interval.

FIG. 8 shows a specific example of the processing by the minimum path tracking control circuit LPS. First, there is no previous value in the initial state, so you have to decide where to start. For this reason, the smallest one of the 5 × 10 correlation data stored in the correlation data buffer RDB is searched. In the example of FIG. 8, correlation data 1 (S (2, 2) in FIG. 6) is extracted as illustrated in (A). Since the correlation data 1 is the correlation data with the pulse interval 2 of the positive polarity, the corresponding bit string "0 1" is output, and the correlation data is further shifted rightward. Wait for the shift operation to be performed twice (B, C).

Next, as illustrated in (C) of FIG. 8, 15 correlations on the negative polarity side, including each row before and after the row of correlation data S (X, 2) shifted by pulse interval 2 Select the minimum value from the data. As described above, in order to allow an error of ± 1 clock, the correlation data of one bit before and after the bit is also searched for the minimum data. In the example of the figure, correlation data 3 (S (9: 2) in FIG. 6) is extracted. The extracted position becomes the starting point of the next bit. Since the extracted correlation data 3 is the correlation data of the pulse interval 4 of the negative polarity, the corresponding bit string “000 1” is output. Furthermore, to extract the next correlation data, first wait for the correlation data to be shifted right four times (D, E, F, G).

Next, as shown in (G) of Fig. 8, 15 positive-side signals including one row before and after each row of correlation data S (X, 2) shifted by 4 pulse intervals Choose the minimum value from the list. In the example shown in the figure, the correlation data is 2 (S (l, 2) in FIG. 6). Since the correlation data 2 is the correlation data of the pulse interval 1 of the positive polarity, the corresponding bit string “1” is output, and the correlation data is shifted once to the right. (H).

Next, as illustrated in (H) of Fig. 8, 15 correlations on the negative polarity side, including each row before and after the row of correlation data S (x, 2) shifted by 1 pulse interval, are shown. Choose the minimum value from the night. In the example shown in the figure, the correlation data is 3 (S (6, 2) in FIG. 6). Since the correlation data 3 is a correlation data with the pulse interval 2 of the negative polarity, the corresponding bit string “0 1” is output, and the correlation data is shifted twice to the right. Wait for it to go (I, J). Then, as illustrated in (J) of FIG. 8, 15 correlation data on the positive polarity side including each row before and after the row of correlation data S (X, 2) shifted by pulse interval 2 Choose the minimum value from. In the example shown, the correlation data 2 (No. This is S (3, 2)) in Fig. 6. Since the correlation data 2 is the correlation data of the pulse interval 3 of the positive polarity, the corresponding bit string “001” is output. Hereinafter, although illustration is omitted, the same processing as above is repeated to continue the extraction of the minimum correlation data.

FIG. 9 shows an operation example of the channel data output circuit SRB. The channel data output circuit SRB is composed of a shift register that sequentially shifts the bit string output from the minimum path tracking control circuit LPS according to the pulse interval of the ideal waveform, right-justified, and has an 8-bit input. When the number of bits exceeds the limit, 8 bits are cut out and output as channel data, and the remaining bits are right-justified. According to the example of FIG. 8, the minimum path tracking control circuit LPS sequentially outputs bit strings “01”, “00001”, “1”, “01”, and serially outputs them. The shift-input channel data output circuit SRB cuts out the 8-bit bit string "0 1 0 0 0 1 1 0", and the surplus bit "1" becomes the beginning of the next channel data output It is shifted as follows.

According to the lead channel 4 described above, the following operation and effect can be obtained.

[1] When the positive polarity pulse and the negative polarity pulse are alternated and the channel data 28 of the bit string corresponding to the pulse interval is reproduced from the information signal 26 having a plurality of types of pulse intervals, it is quantized by the ADC 18. An ideal waveform closest to the pulse waveform or pulse interval of the information signal is detected based on the difference between the obtained data and each ideal waveform data output from the ideal waveform data output means. That is, the pulse interval of the alternating pulse included in the information signal is detected by selecting the ideal wave ^ closest to the waveform of the information signal. Therefore, it is not necessary to detect the peak of the information signal.

In addition, the presence / absence of a pulse per unit time or per bit for the pulse In order to judge, the force required to increase the accuracy of the sampling point by the PLL circuit s.In the above means, the information signal 26 is included in the information signal 26 by selecting the pulse waveform of the information signal or the ideal waveform closest to the pulse interval. It is not an essential condition to improve the accuracy of sampling points because it detects the pulse interval of alternating pulses. For this reason, it is not necessary to use a PLL circuit for reproducing the synchronous clock from the information signal 26.

Since there is no need to use a PLL circuit, the recording density and track density of the magnetic disk are high, and the need for a high-speed access to speed up the data transfer rate, while avoiding the occurrence of a burst error. Prevent: 'Ji can.

[2] (1) In the pulse interval, input the data converted into the S-child by the ADC 18 into a data input buffer having two or more latch stages in series which are larger than the human interval by at least two. Since the number of latch stages is larger than the ig large interval of the pulse question by two or more, the range ffl where the pulse polarity can be determined even for human-powered data of 1 large pulse It is possible to latch the continuous sampling data to multiple latch circuits in the data input buffer and output them in parallel.

[3] Data buffer RDB is before, 记 Waveform detection circuit W D1 to W D

The data detected at 10 can be sequentially shifted and held by at least the number of clock signal cycles corresponding to the s large value of the pulse interval, for example, the maximum value of the pulse interval is 5. Then, the correlation data in the correlation data buffer RDB that develops five consecutive censor data for each ideal waveform appears in the RDB in the most approximate state for each pulse interval held by the information signal Therefore, the processing of extracting the correlation data by the minimum path tracking control circuit LPS which inputs all the correlation data held in the correlation data buffer RDB in parallel is performed by the time of the RDB in the correlation data buffer RDB. It can be carried out within a predetermined range that can be changed before and after. Therefore, the asynchronous clock signal Even if there is the frequency error between the clock signal and the reproduced clock signal, the extraction of the most approximated ideal waveform data does not have a substantial effect.

[4] The ideal waveform data buffer DB la to DB 10b separates the data in which the sample points of the ideal waveform data are shifted by half a pitch from each other at every positive and negative pulse interval. Considering that the phase difference between the asynchronous clock signal and the reproduced clock signal is 180 ° at the maximum, even if the asynchronous clock signal has a phase difference with the reproduced clock signal, However, there is no substantial effect on the extraction of the closest ideal waveform data.

[5] According to the above [3] to [4], the clock signal 24 asynchronous with the information signal 26 is a reproduction clock signal reproducible from the information signal 26 and a force causing an error in frequency and phase. ^s , the effect of the error can be compensated, and relatively high accuracy can be realized in reproducing channel data.

FIG. 10 shows an example in which a channel data reproducing circuit portion is mainly composed of an analog circuit. Instead of the ADC 18, a sample-and-hold circuit 18A that samples and holds the information signal 26 in synchronization with a clock signal 24 is employed. In the subsequent stage, an analog detection gate 19A and an analog decoder 20A constituted by an analog circuit are arranged. The analog detection gate 19A and the analog decoder 20A reproduce the channel data by the same algorithm as the detection gate 19 and the decoder 20. This example is an example in which power consumption can be reduced when the power consumption of the ADC 18 is particularly large. FIG. 11 shows an example in which the reproducing circuit portion of the channel device is configured to be capable of performing software processing. That is, a digital signal processing processor (DSP) 40 that executes a digital signal processing program provides a detection gate function 19 B and a decoder function 2 by the same processing algorithm as the detection gate 19 and the decoder 20. 0 B You. Although not shown, the function of the code decoding circuit 21 is also realized by the DSP 40.

At this time, a buffer memory 41 for storing the data 27 converted by the ADC 18 is provided, and the data read from the buffer memory 41 is supplied to the DSP 40. According to this, by performing the reproduction process a plurality of times while changing the processing conditions included in the detection gate function 19 B, the error correction capability using the ECC circuit 5 can be improved. For example, when the ideal waveform data buffer is provided with a plurality of types of ideal waveform data determined assuming different use conditions, and an uncorrectable error in the channel data is detected by the ECC circuit, Enables to switch the seed of the ideal waveform output. Switching can be performed by software processing. At this time, it is not necessary to reread the information signal from the magnetic disk 1, and it is sufficient to perform the memory access to the buffer memory 41, so that the reprocessing time can be reduced. The plurality of types of ideal waveforms are different data determined under the assumption of different use conditions, such as the use atmosphere temperature and pressure.

The efficient use of the buffer memory 41 is ffl

Guaranteed by not using PLL circuit. That is, since the information signal 26 is asynchronously sampled, even if the sampled data is stored in the buffer memory 41 in a relatively large unit such as one sector, the data is not wasted later. If the PLL circuit is unlocked when using the pLL circuit, even if the data is stored in the buffer, the data cannot be used at all later.

The configuration having the buffer memory is not limited to the case where the DSP 40 is used. Naturally, the configuration described so far based on FIG. 1 and the like is also applicable. FIG. 12 shows still another example having a buffer memory. In the configuration of FIG. 11, in order to cancel the memory access time of the buffer memory 41 at the time of reprocessing, a pair of DSPs 40A and 40B similar to the DSP 40 is provided, and they are operated in parallel in advance. The output can be selected according to the error situation. That is, a selector 42 is provided for selecting the outputs of the DSPs 40A and 40B and supplying the outputs to the ECC circuit 5A. The selector 42 switches its selection state when an uncorrectable error in the channel data by the ECC circuit 5A is detected.

FIG. 13 shows an example in which the configuration for reproducing the channel data is applied to a communication control device that receives the information signal from a transmission medium. The major difference from FIG. 1 is that the input of the reproduced waveform is supplied from the transmission medium 46. The transmission data is supplied to the AGC 16 via the code conversion circuit 44, the transmitter 45, and the transmission medium 46. The clock signal 24 is generated by a frequency synthesizer or a reference clock generation circuit 14A. In this case as well, it is not necessary to generate a reproduced clock signal synchronized with the data by the PLL circuit and quantize the transmission signal as in the hard disk device. Other configurations are the same as those in FIG. 1 and the like, and detailed description thereof is omitted.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, the type of the pulse interval included in the information signal is not limited to the above example, and can be appropriately changed. According to this, the type of the ideal waveform data and the number of data in the ideal waveform data can be changed. Also, the number of latch stages O of the data input buffer 30 and the correlation data buffer RDB can be appropriately changed as long as the necessary conditions are satisfied. The calculation for detecting the minimum value of the correlation data is not limited to the sum of squares of the difference. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention can be widely applied to reproduction of run-length encoded channel data in a magnetic storage device such as a hard disk device or a communication control device.

Claims

An information reproducing apparatus for reproducing channel data of a bit train corresponding to a pulse interval from a signal signal in which a rising polarity pulse and a falling polarity pulse are alternated and having a plurality of types of pulse intervals.

Ideal waveform data output means for outputting ideal waveform data for representing an ideal waveform related to the rising polarity pulse and an ideal waveform related to the falling polarity pulse for each pulse interval;

Conversion means for sampling or quantizing the information signal in synchronization with a clock signal having a cycle corresponding to the sampling point bit of the ideal waveform data; data converted by the conversion means and output from the output means A waveform detecting means for sequentially determining an ideal waveform approximating the pulse waveform of the information signal based on a difference from each ideal waveform data;

Information reproducing means for forming a bit train corresponding to a pulse interval of an ideal waveform sequentially determined by the waveform detecting means and outputting the channel data as channel data; The waveform detecting means includes:

A latch circuit having two or more stages larger than the maximum interpulse interval of the pulse interval is provided in series, and each latch circuit performs a latch operation in synchronization with a clock signal and inputs data converted by the conversion means to a first stage. A data input buffer,

Based on a difference between each ideal waveform data output from the ideal waveform data output means and the latch data of the plurality of latch circuits, correlation data indicating a state of approximation of each ideal waveform with respect to the pulse waveform of the information signal is obtained. Calculating means for calculating in synchronization with the lip signal; A correlation data buffer capable of sequentially shifting and holding the correlation data calculated by the calculation means by at least the number of clock signal cycles corresponding to the maximum value of the pulse interval;

A process of extracting correlation data indicating the state of closest approximation among the correlation data of one polarity pulse held in the correlation data buffer; and a process of extracting an ideal waveform pulse interval corresponding to the extracted correlation data. Waits for the correlation data to be shifted in the correlation data buffer and extracts the correlation data that indicates the state that is the most similar among the correlation data for the pulse of the other polarity, and then performs the processing that is the most similar 2. The information reproducing apparatus according to claim 1, further comprising: a tracking control unit that obtains the correlation data.

3. The ideal waveform data output means outputs data in which sampling points of the ideal waveform data are shifted from each other by a half pitch for each pulse interval of rising polarity and falling polarity. The information reproducing apparatus according to claim 1 or 2.

4. The conversion means includes an A / D conversion circuit that converts the information signal into a digital signal in synchronization with a clock signal, or a sampler that samples and holds the 10-ft information signal in synchronization with a clock signal. 3. The information reproducing apparatus according to claim 1, wherein the information reproducing apparatus is a hold circuit.

5. The information signal is a read signal from a disk, and has a frequency synthesizer for generating a synchronization signal of information to be written on the disk, and the clip signal is output from the frequency synthesizer. 3. The information reproducing apparatus according to claim 1, wherein:

6. The information reproducing apparatus according to claim 1, wherein the information signal is received from a transmission medium.

7. For the channel data output from the channel data output means, 3. The information reproducing apparatus according to claim 1, further comprising an ECC circuit that enables error checking and correction. 8. The information reproducing apparatus according to claim 7, further comprising: a buffer memory for storing the data converted by the conversion means, wherein the data read from the buffer memory is supplied to the waveform detection means. The ideal waveform data output means has a plurality of types of ideal waveform data determined by assuming different use conditions, and the type of the output ideal waveform data cannot be corrected by the ECC circuit for the channel data. 9. The information reproducing apparatus according to claim 8, wherein switching is possible when an error is detected.

0. At least a plurality of sets of processing means including the ideal waveform data output means, calculation means, data buffer, tracking control means, and channel data output means are provided so as to operate in parallel,

A selector for selecting the channel data output means included in each of the processing means and selecting an output of the selected channel data output means; and a channel data output from the channel data output means selected by the selector. When an error and correction are enabled, an ECC circuit is provided.

3. The information reproducing apparatus according to claim 2, wherein the selector is configured to be able to switch a selection state when an uncorrectable error in the channel data by the ECC circuit is detected.

10. The method according to claim 10, wherein the ideal waveforms outputted by the ideal waveform data output means included in the respective processing means are different data determined under the assumption of different use conditions. Information playback device.

2. Rising polarity pulse and falling polarity A semiconductor device that reproduces channel data of a bit train corresponding to a pulse interval from an information signal having a similar pulse interval,

Separate the ideal waveform data for representing the ideal waveform related to the rising polarity pulse and the ideal waveform corresponding to the falling polarity pulse for each pulse interval, in which the sampling point pitch of the ideal waveform data is shifted by half a pitch. Means for outputting ideal waveform data to

A conversion unit for synthesizing the information signal or synthesizing the information signal in synchronization with a periodic signal having a cycle corresponding to the sampling point pitch;

A waveform for sequentially determining an ideal wave J that approximates the pulse interval of the report based on a portion between the data converted by the conversion stage and each ideal waveform data output from the output means. Detecting means;

and a channel data output means for forming a bit train corresponding to the pulse interval of the J1 pseudo waveform determined in the first step and outputting the data as end channel data. A semiconductor device characterized by the above-mentioned.

3. A rising polarity pulse and a falling polarity pulse are intersected and a multi-polarity pulse 15) is separated from ι, 'する ^ by the ι,' ί ^, and the channel data of the bit train corresponding to the pulse interval is PI It ’s a holiday rest is

An ideal waveform data output means for outputting an ideal waveform data for representing an ideal waveform corresponding to the rising polarity pulse and a falling polarity pulse for each pulse interval.

Conversion means for sampling or quantizing the broadcast signal in synchronization with the clock signal;

A latch circuit having two or more stages greater than the maximum inter-pulse interval of the pulse interval is provided in series, and each latch circuit performs a latch operation in synchronization with a clock signal and inputs data converted by the conversion means to a first stage. With data A force buffer,

Based on a difference between each ideal waveform data output from the output means and the latch data of the plurality of latch circuits, correlation data indicating an approximate state of each ideal waveform with respect to a pulse interval of the information signal is used as the cross-section. Calculating means for calculating in synchronization with a clock signal;

A correlation data buffer capable of sequentially shifting and holding the correlation data calculated by the calculation means by at least the number of click signal cycles corresponding to the maximum value of the pulse interval;

A process of extracting correlation data indicating the state of closest approximation among correlation data of one polarity pulse held in the correlation data buffer; and a pulse interval of an ideal waveform corresponding to the extracted correlation data. The correlation data is shifted in the correlation data buffer by a certain amount, and the process of extracting the correlation data that indicates the state that is the closest in the correlation data for the pulse of the other polarity is performed. A tracking control means for collecting state correlation data;

A channel data output stage for converting a bit train corresponding to a pulse interval of an ideal waveform corresponding to correlation data sequentially extracted by the tracking control means into a predetermined bit format and outputting the converted data as the channel data; An information reproducing apparatus characterized in that is formed on a semiconductor chip.