Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design

Definitions

• Field of Invention Invention relates to electronic data and signal processing, particularly to high-
• processors and instruction-set architectures that allow for the exploitation of hardware parallelism and software concurrency.
• High-performance is typically defined as the ability to execute a very large number of operations per second. This figure of merit is strongly dependent on the
• Instruction-set architecture refers to the actual programmer-visible sets of
• Instruction-level parallelism this approach, which exploits parallelism in hardware, provides for parallel threads of processing via the use of a very long or vectorized instruction word, whose fields can be
• multi-processor systems may employ multi-threaded
• Multi -threading generally is a known
• design or functional definition, algorithm, electronic signal, or data file is provided initially to include one or more multi-threaded representation.
• Such initial prototype is provided initially to include one or more multi-threaded representation.
• Such element is built by providing a datapath, whose structure and configurability is determined via profiling, a sequencer/finite-state-machine, whose structure and configurability is determined via
• profiling and local memory, whose structure is determined via profiling memory
• kernel elements are implemented entirely in software or programmable logic, or combination thereof.
• term “profiling” refers generally to
• FIG. 1 is a general methodology and tool architecture diagram for
• FIGs. 2A-B are functional block diagrams for implementing one aspect of the
• FIG. 3 is a representative functional diagram illustrating heterogeneous aspect
• FIG. 4 is a representative functional diagram illustrating reconfigurable aspect
• FIG. 5 is a representative functional diagram illustrating kernel aspect of the present invention.
• FIG. 6 is a representative functional diagram illustrating interface aspect of the present invention.
• FIG. 7 is a system methodology flow chart showing functional operations for implementing one or more aspects of the present invention.
• FIG. 8 is representative of software code stubs for implementing one or more aspects of the present invention.
• FIG. 9N-B are representative functional diagrams of one or more applications
• multi-threaded prototype may be used or otherwise be implemented in fixed, parameterizable, programmable, or configurable logic unit or
• multi-thread algorithms specific sequences of operations, patterns of memory accesses, or segments, each thread being profiled or characterized to optimize operation or implementation using fixed, parameterizable, programmable, or
• datapath structure is configured into single or multi-thread
• profiling terminology is understood to refer generally to any
• profiling is accomplished according to one or more previously and/or
• the generated symbolic representation may identify certain threads associated with the
• Each thread may be profiled for processing by corresponding kernel
• thread may further be mapped to identify the sequence, or scheduling information, for
• processing architecture may substantially include a set of kernel elements, such that
• one kernel element processes certain function represented by corresponding thread
• each thread may be profiled separately or hierarchically for
• group kernel element and a second-level or group kernel element are associated with a corresponding first thread and second thread in a given function or
• front-end processing e.g., data
• chip-rate processing e.g., sample epoch
• channel element processing e.g., alignment/deskewing, combiner, soft decision computer, interpath interference equalizer, receive antenna diversity
• interleaving e.g., deinterleaver controller
• channel coding e.g.,
• turbo decoder convolutional decoder, etc.
• kernel elements i.e., as determined by profiling technique as described further
• FIG. 1 is a general architecture or system block diagram showing top-level
• present design methodology serves to provide a tool architecture and processor implementation and architecture, or data file representative thereof, for enabling
• system architecture such as network implementation.
• netlist, or high-level description language (such as C or HDL) defining one or more functional modules or algorithms 12 is provided manually or computed automatically.
• profiling and mapping scheme 14 is processed or applied to primitives 16 and
• mapping 14 provides scheduling data for schedule operation tables 20.
• kernels 18 are processed and interconnected for implementation 22, for
• FIGs. 2A-B functional block diagrams show representative set of kernels 18,
• one or more kernel 18 is associated with or corresponds to profiled and mapped thread, and is implemented reconfigurably using sequencer 32, datapath 34,
• multi-threaded representation thereof which may be profiled effectively for parallel processing using one or more corresponding kernel logic elements (e.g., according to
• FIG. 3 functional diagram shows representative heterogeneous, reconfigurable
• kernel 8 may implement
• kernel 6 may implement "large” granularity
• kernel may be implemented or dynamically reconfigured according to design requirement or profile mapping preference.
• FIG. 4 functional diagram shows one or more
• kernels such as reconfigurable logic or programmable function units
• PFU 40 having programmable logic elements and switch matrix (e.g., for encoding bit-level operations), reconfigurable datapaths 42 having multiplexers, registers, adders, buffers, etc. and configurable signal flow through these elements (e.g., for
• reconfigurable control 46 having data memory, datapath, program memory, instruction decoder and controller, etc. (e.g., for real-time operating system process
• FIG. 5 functional diagram shows preferred functional elements for implementing kernel 18, including data sequencer 32, data memory 36, and parameterizable configurable
• ALU arithmetic logic unit
• FIG. 6 is a representative functional diagram illustrating optional interface
• DRL dynamically reconfigurable logic
• DRL process is heterogeneous and reconfigurable
• hardware interfaces 54 couples
• processor element 52 associated with library 62 and specified functional modules 60, including processor software model 57 having C-program model 56 and input/output
• information e.g., signal or data representation
• general system design e.g., signal or data representation
• processor model 50 for functional cooperation or emulated real-time signal
• FIG. 7 flow chart shows another aspect of present operational steps. Initially, user-generated or computer-generated functions are defined 70 for prototype or other
• one or more mathematical analysis or design performance optimization scheme may be applied 72 to initial design definition.
• one or more mathematical analysis or design performance optimization scheme may be applied 72 to initial design definition.
• constituent algorithms for design definition is provided 74, and representation of such algorithms is thereby coded 76, preferably in high-level, register transfer, or
• Algorithms may be profiled and mapped 78, or otherwise functionally defined
• communications semaphores 84 also are provided for communications semaphores 84 and scheduling and finite state
• FIG. 8 shows
• profiling processing or
• reconfigurable algorithms representative thereof is temporal, thereby including
• temporal application includes changes in receiver algorithms required in a cellular
• processing throughput requirements in one path may increase or decrease as processing progresses (e.g., from antenna to final retrieved data representation,) present profiling scheme serves to determine hardware-
• dependent changes in receive path of wireless receiver may need to change at startup for global reconfiguration between transaction configuration (e.g.,
• implementation may be selected, such as for processing data at highest data rate
• programmable interconnect For a datapath which may need to be selected at configuration time, but is not changed often, then programmable interconnect may be
• multiplexing structure may apply. Also, for control functions where operation
• parameterized kernels for processing operations may apply.
• FIG. 9A shows general aspects of applying present invention, including flow
• API API
• Preferred implementation receives configuration parameters through API 94 to define or implement one or more interconnected block modules 96, representing
• DSP digital signal processor
• ASIC application specific integrated circuit
• FPGA field programmable gate array
• DRL or other functional block
• kernel elements 98 are integers.
• configurable parameters 100 may be defined or implemented to correspond in
• design and implementation method or system serves to
• prototype function is thus profiled for parallel processing by one or more thread, for
• FIG. 9B portable mobile radio handsets 102 transmit and receive signals wirelessly
• base station 104 possibly coupled to other handsets 102 and base stations 104
• kernel elements may be configured for operation in base station 104 and/or handset units 102.
• kernels may be configured for profiled

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Evolutionary Computation (AREA)
• Geometry (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Logic Circuits (AREA)
• Stored Programmes (AREA)
• Mobile Radio Communication Systems (AREA)
• Advance Control (AREA)

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• 2001
  • 2001-01-29 DE DE10195202T patent/DE10195202T1/de not_active Ceased
  • 2001-01-29 AU AU2001233119A patent/AU2001233119A1/en not_active Abandoned
  • 2001-01-29 JP JP2001555391A patent/JP2003521072A/ja active Pending
  • 2001-01-29 WO PCT/US2001/002982 patent/WO2001055917A1/en active Application Filing
  • 2001-01-29 KR KR1020027009711A patent/KR100784412B1/ko not_active IP Right Cessation
  • 2001-01-29 GB GB0217126A patent/GB2374701B/en not_active Expired - Fee Related

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