WO2001053942A3 - Double-ended queue with concurrent non-blocking insert and remove operations - Google Patents

Double-ended queue with concurrent non-blocking insert and remove operations Download PDF

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Publication number
WO2001053942A3
WO2001053942A3 PCT/US2001/000042 US0100042W WO0153942A3 WO 2001053942 A3 WO2001053942 A3 WO 2001053942A3 US 0100042 W US0100042 W US 0100042W WO 0153942 A3 WO0153942 A3 WO 0153942A3
Authority
WO
WIPO (PCT)
Prior art keywords
concurrent
deque
array
double
blocking insert
Prior art date
Application number
PCT/US2001/000042
Other languages
French (fr)
Other versions
WO2001053942A2 (en
Inventor
Nir N Shavit
Ole Agesen
David L Detlefs
Christine H Flood
Alexander T Garthwaite
Paul A Martin
Guy L Steele Jr
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/547,288 external-priority patent/US7539849B1/en
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2001227533A priority Critical patent/AU2001227533A1/en
Publication of WO2001053942A2 publication Critical patent/WO2001053942A2/en
Publication of WO2001053942A3 publication Critical patent/WO2001053942A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Multi Processors (AREA)

Abstract

An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algorithm allows uninterrupted concurrent access to both ends of the deque, while returning appropriate exceptions in the boundary cases when the deque is empty or full. An interesting characteristic of the concurrent deque implementation is that a processor can detect these boundary cases, e.g., determine whether the array is empty or full, without checking the relative locations of the two end pointers in an atomic operation.
PCT/US2001/000042 2000-01-20 2001-01-02 Double-ended queue with concurrent non-blocking insert and remove operations WO2001053942A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001227533A AU2001227533A1 (en) 2000-01-20 2001-01-02 Double-ended queue in a contiguous array with concurrent non-blocking insert andremove operations

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US17708900P 2000-01-20 2000-01-20
US60/177,089 2000-01-20
US09/547,288 2000-04-11
US09/547,288 US7539849B1 (en) 2000-01-20 2000-04-11 Maintaining a double-ended queue in a contiguous array with concurrent non-blocking insert and remove operations using a double compare-and-swap primitive

Publications (2)

Publication Number Publication Date
WO2001053942A2 WO2001053942A2 (en) 2001-07-26
WO2001053942A3 true WO2001053942A3 (en) 2002-05-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/000042 WO2001053942A2 (en) 2000-01-20 2001-01-02 Double-ended queue with concurrent non-blocking insert and remove operations

Country Status (2)

Country Link
AU (1) AU2001227533A1 (en)
WO (1) WO2001053942A2 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7769791B2 (en) 2001-01-12 2010-08-03 Oracle America, Inc. Lightweight reference counting using single-target synchronization
US7299242B2 (en) 2001-01-12 2007-11-20 Sun Microsystems, Inc. Single-word lock-free reference counting
US7908441B2 (en) 2002-01-11 2011-03-15 Oracle America, Inc. Value recycling facility for multithreaded computations
US7836228B1 (en) 2004-06-18 2010-11-16 Oracle America, Inc. Scalable and lock-free first-in-first-out queue implementation
US9052944B2 (en) 2002-07-16 2015-06-09 Oracle America, Inc. Obstruction-free data structures and mechanisms with separable and/or substitutable contention management mechanisms
US7395274B2 (en) 2002-07-16 2008-07-01 Sun Microsystems, Inc. Space- and time-adaptive nonblocking algorithms
US7293143B1 (en) 2002-09-24 2007-11-06 Sun Microsystems, Inc. Efficient non-blocking k-compare-single-swap operation
US7814488B1 (en) 2002-09-24 2010-10-12 Oracle America, Inc. Quickly reacquirable locks
US7424477B1 (en) 2003-09-03 2008-09-09 Sun Microsystems, Inc. Shared synchronized skip-list data structure and technique employing linearizable operations
US10049127B1 (en) 2003-12-19 2018-08-14 Oracle America, Inc. Meta-transactional synchronization
US8074030B1 (en) 2004-07-20 2011-12-06 Oracle America, Inc. Using transactional memory with early release to implement non-blocking dynamic-sized data structure
US7703098B1 (en) 2004-07-20 2010-04-20 Sun Microsystems, Inc. Technique to allow a first transaction to wait on condition that affects its working set
US7395382B1 (en) 2004-08-10 2008-07-01 Sun Microsystems, Inc. Hybrid software/hardware transactional memory
US7711909B1 (en) 2004-12-09 2010-05-04 Oracle America, Inc. Read sharing using global conflict indication and semi-transparent reading in a transactional memory space
US7577798B1 (en) 2004-12-30 2009-08-18 Sun Microsystems, Inc. Space-adaptive lock-free queue using pointer-sized single-target synchronization
US7680986B1 (en) 2004-12-30 2010-03-16 Sun Microsystems, Inc. Practical implementation of arbitrary-sized LL/SC variables
US7533221B1 (en) 2004-12-30 2009-05-12 Sun Microsystems, Inc. Space-adaptive lock-free free-list using pointer-sized single-target synchronization
CN101290589B (en) * 2007-12-27 2010-06-16 华为技术有限公司 Parallel instruction operation method and device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986000434A1 (en) * 1984-06-27 1986-01-16 Motorola, Inc. Method and apparatus for a compare and swap instruction
EP0366585A2 (en) * 1988-10-28 1990-05-02 International Business Machines Corporation Method for comparing and swapping data in a multi-programming data processing system
EP0466339A2 (en) * 1990-07-13 1992-01-15 International Business Machines Corporation A method of passing task messages in a data processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986000434A1 (en) * 1984-06-27 1986-01-16 Motorola, Inc. Method and apparatus for a compare and swap instruction
EP0366585A2 (en) * 1988-10-28 1990-05-02 International Business Machines Corporation Method for comparing and swapping data in a multi-programming data processing system
EP0466339A2 (en) * 1990-07-13 1992-01-15 International Business Machines Corporation A method of passing task messages in a data processing system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
AGESEN O ET AL: "DCAS-BASED CONCURRENT DEQUES", SPAA 2000. 12TH. ANNUAL ACM SYMPOSIUM ON PARALLEL ALGORITHMS AND ARCHITECTURES. BAR HARBOR, ME, JULY 9 - 12, 2000, ANNUAL ACM SYMPOSIUM ON PARALLEL ALGORITHMS AND ARCHITECTURES, NEW YORK, NY: ACM, US, 9 July 2000 (2000-07-09), pages 137 - 146, XP002172095, ISBN: 1-58113-185-2 *
ARORA N S ET AL: "THREAD SCHEDULING FOR MULTIPROGRAMMED MULTIPROCESSORS", SPAA '97. 10TH. ANNUAL ACM SYMPOSIUM ON PARALLEL ALGORITHMS AND ARCHITECTURES. PUERTO VALLARTA, MEXICO, JUNE 28 - JULY 2, 1998, ANNUAL ACM SYMPOSIUM ON PARALLEL ALGORITHMS AND ARCHITECTURES, NEW YORK, NY: ACM, US, 28 June 1998 (1998-06-28), pages 119 - 129, XP002172092, ISBN: 0-89791-989-0 *
DETLEFS D L ET AL: "EVEN BETTER DCAS-BASED CONCURRENT DEQUES", DISTRIBUTED COMPUTING. 14TH INTERNATIONAL CONFERENCE, 4 October 2000 (2000-10-04), pages 59 - 73, XP002172096 *

Also Published As

Publication number Publication date
WO2001053942A2 (en) 2001-07-26
AU2001227533A1 (en) 2001-07-31

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