WO2001052060A1 - Dispositif de traitement de donnees a fichier registre reparti - Google Patents

Dispositif de traitement de donnees a fichier registre reparti Download PDF

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Publication number
WO2001052060A1
WO2001052060A1 PCT/EP2000/000259 EP0000259W WO0152060A1 WO 2001052060 A1 WO2001052060 A1 WO 2001052060A1 EP 0000259 W EP0000259 W EP 0000259W WO 0152060 A1 WO0152060 A1 WO 0152060A1
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WO
WIPO (PCT)
Prior art keywords
output
input
register
crossbar
processing device
Prior art date
Application number
PCT/EP2000/000259
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English (en)
Inventor
Jean-Paul Theis
Original Assignee
Theis Jean Paul
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Theis Jean Paul filed Critical Theis Jean Paul
Priority to EP00904914A priority Critical patent/EP1161722A1/fr
Priority to PCT/EP2000/000259 priority patent/WO2001052060A1/fr
Publication of WO2001052060A1 publication Critical patent/WO2001052060A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers

Definitions

  • a data processing device with distributed register file A data processing device with distributed register file
  • the present invention relates to the field of architecture design of data processing devices. More specifically, the invention is dealing with architecture design issues at register-transfer level and is focusing on data path architectures of processing devices.
  • the term 'data processing device' has a very broad meaning and can stand for terms like (micro)processor, micro-controller, central processing unit (CPU), digital signal processor (DSP), application specific integrated circuit (ASIC), application specific standard product (ASSP), application specific instruction set processor (ASIP).
  • a register-transfer level architecture of a processing device can be thought of as consisting of a limited number of elementary building blocks with which the processing device is built up.
  • the register transfer-level architecture of a processing device typically consists of Processing Elements (PEs), register files, busses, crossbars and a control unit which are arranged and connected to each other in a well defined manner.
  • a crossbar is a building block that makes connections between its inputs and outputs.
  • a fully connected crossbar is able to connect any input to one, more or even all outputs.
  • a partially connected crossbar is able to connect any input to one or more but not all outputs.
  • Multiplexers/demultiplexers are crossbars with one input/output and one or more outputs/inputs respectively.
  • the (register-transfer-level) data path architecture of a processing device comprises only building blocks directly involved in the data processing, e.g. PEs, register files, busses and crossbars, but not any control units used to control the building blocks of the data path. Therefore in all the following figures, control signals for crossbars, PEs and register files will only be shown when they are relevant in the context of the present invention. Furthermore, in all the figures that follow, arrows represent either bussed connections between building blocks or bussed inputs and bussed outputs of building blocks and processing devices, where the bus width of a bussed connection or of a bussed input/output is equal to one or more bits.
  • control signals for register files f.ex. determine the addresses of the register locations to/from which data are written/read respectively or represent clocking signals.
  • Register file inputs are also called write ports and register file outputs are also called read ports. Read/write ports may have simultaneous access to all register locations in the register file.
  • Control signals for PEs f.ex. select the operations to be performed.
  • Control signals for crossbars determine the connections to be made between crossbar inputs and crossbar outputs.
  • Figures 2, 3 and 4 can be used to retrace briefly the evolutionary steps of register-transfer-level architectures of processing devices with a distributed register file.
  • FIG. 2 shows one of the first data path architectures of a processing device with a distributed register file. It was called the polycyclic processor and was developed by ESL Inc. in the early 80's.
  • the data path architecture at register-transfer-level is shown and consists of a set of PEs whose inputs and outputs are connected to a crossbar with delay elements at each cross point.
  • the delay elements can be thought of as a particular implementation of a register file.
  • PEs, crossbar and delay elements are connected in the following way : (1) each PE (data) output is connected to as many independent cross points in a row of the crossbar as there are PE inputs (2) each PE input is connected to and selected out of as many cross points in a column as there are PE outputs.
  • a next step in the evolution of data path architectures with a distributed register file consisted in integrating the crossbar with delay elements as shown in figure 2 directly into the data path architecture of a microprocessor. This step was done in the data path architecture (again at register-transfer-level) of a video signal processor which was developed in the late 80's by Philips Research and which is shown in figure 3.
  • the crossbar is called a switch matrix
  • the delay elements are called Silos
  • the PEs are called ALEs (Arithmetic Logic Elements), where ALE is yet another word for ALU.
  • the Silos are used for slightly different data storage purposes : 1) as Memory Elements (MEs) which contain in addition to the Silos conventional memory for program data and logic for address calculation 2) as Buffer Elements (BEs) for buffering data 3) as Output Elements (OEs) for buffering data before they leave the processor.
  • MEs Memory Elements
  • BEs Buffer Elements
  • OEs Output Elements
  • the PEs can be of different type, and with several data inputs and data outputs.
  • the register files can be of different type as well as, like f.ex. stacks, FIFOs and register files with rotating properly where the data rotate in the register file, and they may have several read and write ports from and to which data can be read and written simultaneously.
  • the crossbar can be fully or only partially connected.
  • outputs of register files may be connected to PE inputs and/or to processor outputs.
  • Data path architectures with distributed register file try to overcome these shortcomings by using several and smaller register files with only a few read/write ports. All these register files together are of about the same size as a big single register file.
  • the prize that is paid to overcome the problems linked to a single register file consists in bigger code size.
  • data path architectures with distributed register files are typically VLIW processor architectures where a compiler is optimizing the program code statically in order to optimally exploit the multiple register.
  • the program code of VLIW processors is typically twice as large as for 'conventional ' processors (processing devices) with a single registerfile.
  • Figure 1 shows the data path architecture of a 'conventional' processor with a single registerfile.
  • FIG. 2 shows the data path architecture of the polycyclic processor developed by ESL Inc.
  • Figure 3 shows the data path architecture of a video signal processor developed by Philips Research.
  • Figure 4 shows the data path architecture of a processor with a distributed register file according to the prior art.
  • Figure 5 shows the data path architecture of a processing device with a distributed register file based on the present invention.
  • Figure 6 shows a specific example of the data path architecture of a processing device with a distributed register file based on the present invention.
  • Figure 7 shows two variants of a specific type of register file containing a shift register connected to a crossbar. One variant of this type of register file is shown at lower right, the other variant is shown at lower left.
  • Figure 8 shows a specific example of an array of processing devices built up according to the rules based on the present invention.
  • Figure 9 shows two processing devices of an array and visualizes the rules concerning a) processing device inputs which are connected to an array input and b) processing device inputs which are connected to an output of a processing device of the array.
  • Data path architectures of processing devices with a distributed register file based on the present invention differ significantly from the data path architectures of the prior art and are obtained by applying a set of building rules to a set of building blocks. The differences with the prior art will become clear when discussing these building rules.
  • a processing device comprising one or more inputs, one or more outputs and one or more processing elements, each processing element having one or more inputs and one or more outputs.
  • the terms 'data path architecture', 'crossbar', 'register file' and 'processing element' always refer to the considered processing device.
  • the first type of data path architecture of a processing device based on the present invention contains :
  • each processing device input is connected to the input of a register file
  • each output of each processing element is connected to the input of a registerfile
  • any output of any processing element and any other output of any processing element are not connected to the same input of a register file
  • each register file is connected either to an output of a processing element or to a processing device input
  • each output of each register file is connected to an input of a crossbar
  • any output of any register file and any other output of any other register file are not connected to a same input of a crossbar (I) each input of each crossbar is connected to an output of a register file
  • any input of any crossbar and any input of any other crossbar are not connected to the same output of any register file
  • each processing device output is connected to the output of a crossbar
  • each input of each processing element is connected to the output of a crossbar
  • any processing device output and any other processing device output are not connected to the same output of a crossbar
  • any processing element input and any other processing element input are not connected to the same output of a crossbar
  • the output of each crossbar is connected either to a processing device output or to an input of a processing element (s) the output of any crossbar and the output of any other crossbar are neither connected to a same processing device output nor to a same input of a processing element
  • the data values appearing on one or more inputs of the register file may be written/read into/from register locations according to similar rules as for the connections to be done inside a crossbar, depending on the bus width of the registerfile inputs, of the register cells contained in the registerfile and of the registerfile outputs.
  • FIG 5 A processing device with a data path architecture built up according to the rules mentioned above is shown in figure 5.
  • Figure 5 aims at visualizing the above rules, therefore the number of processing device inputs and outputs, the number of PEs as well as the number of PE inputs and PE outputs is not further specified.
  • figure 6 shows a specific example of a processing device with such a data path architecture : it contains two PEs, two processing device inputs and two processing device outputs. Each PE has two inputs and two outputs. Register files have either one, two or three outputs. Furthermore the number of existing connections between outputs of register file and inputs of crossbars differ from register file to register file and from crossbar to crossbar, in other words not all connections that are allowed by the rules are effectively realized.
  • the second type of data path architecture of a processing device based on the present invention slightly differs from the first type in the way that this second type of data path architecture contains one or more register files of a same type, this type of register file being shown in figure 7 and denoted by ' SR + # '.
  • This type of register file is shown in figure 7 and denoted by ' SR + # '.
  • the shift register contains one or more register cells
  • the shift register has one input and as many outputs as there are register cells contained in the shift register, each register cell having one input and one output
  • the crossbar is either partially or fully connected and has as many outputs as there are registerfile outputs
  • the crossbar has as many inputs as there are register cells, contained the shift register
  • the crossbar has as many inputs as the number obtained by incrementing by one the number of register cells contained in the shift register
  • the register file input is connected to the input of the shift register
  • the register file input is connected to the input of the shift register and to an input of the crossbar
  • each shift register output is connected to an input of the crossbar (m) any shift register output and any other shift register output are not connected to a same input of the crossbar (n) in case of one variant, each input of the crossbar is connected to a shift register output (o) in case of the other variant, each input of the crossbar is connected either to a shift register output or to the register file input (p) any input of the crossbar and any other input of the crossbar are neither connected to the same shift register output nor to the register file input (q) each output of the crossbar is connected to a register file output (
  • the difference between the two variants lies in the fact that in case of the variant shown at lower left in figure 7, the register file input can directly be forwarded to one or more register file outputs without traversing a cell of the shift register.
  • the shift register contained in the register file may have a gated clock input, in other words the contents of the register cells are only then shifted by one position in the shift direction within every clock cycle of some clock used in the processing device if some signals generated in the control unit(s) of the processing device have a specific value.
  • the value of these signals may change from clock cycle to clock cycle of some clock used in the processing device and generally depend on the program code, on the instructions that are executed by the processing device, on results of operations performed by the PEs and on data values stored in the register files.
  • the first cell of the shift register is the register cell with label 1
  • the last cell of the shift register is the cell with label m. Note that concerning the bus width of any connections between any inputs and outputs of the shift register, of the crossbar, of any register cell of the shift register and of the register file itself the same remark holds as for the connections done inside a processing device with a data path architecture of the first type as described above.
  • the present invention is also dealing with arrays of processing devices.
  • the data path architecture of the processing devices used in these arrays is closely related to the data path architecture of the first and second type as described above.
  • An array comprising two or more processing devices and one or more array inputs and one or more array outputs.
  • Each processing device of the considered array has one or more inputs and one or more outputs.
  • the term 'processing device' always refers to the considered array.
  • the array is built up according to the following rules :
  • each array input is connected to one or more inputs of one or more processing devices
  • each output of each processing device is connected to one or more inputs of one or more processing devices orto one or more array outputs
  • any output of any processing device and any output of any other processing device are neither connected to a same input of a processing device nor to a same array output
  • the first and second type of data path architecture as described above are used inside 'stand alone' processing devices, in other words processing devices which are not part of an array of several processing devices.
  • the type of data path architecture of processing devices which are part of an array slightly differs from the first and second type of data path architecture of a 'stand alone' processing device. The difference consists in the number of register files used inside each processing device of the array as well as in the way that inputs of register files are connected to processing device inputs.
  • the difference is as follows : if an input of any processing device of the considered array is not connected to an output of a processing device of the considered array but is connected to an array input, then it is connected to the input of a register file in the same way as for the data path architecture of the first and second type described above; if an input of any processing device of the considered array is connected to an output of a processing device of the considered array but is not connected to an array input, then it is directly connected to one or more inputs of one or more crossbars of the considered processing device.
  • Figure 9 shows thereby two processing devices of an array.
  • the input of the processing device at the right side which is connected to an output of the processing device at the left side, is not connected to an input of a register file but directly connected to one or more inputs of one or more crossbars of that processing device.
  • the input of the processing device at the right side which is connected to an array input, is connected to an input of a register file in the same way as forthe data path architecture of the first or second type described above.
  • the terms 'processing device input', 'processing device output', crossbar(s)', 'register file(s)' and 'processing elements)' always refer to the considered processing device.
  • each processing device of the considered array contains :
  • processing element outputs correspond to all the outputs of all the processing elements of the considered processing device
  • marked processing device inputs correspond to all those inputs of the considered processing device which are connected to an array input
  • each register file has one input and one or more outputs
  • each crossbar has one output and one or more inputs and has a register-transfer-level data path architecture which is built up according to the following rules :
  • each processing device input which is connected to an array input is connected to the input of a registerfile
  • each processing device input which is connected to an output of a processing device of the considered array is connected to one or more inputs of one or more crossbars
  • any processing device input and any other processing device input are neither connected to the same input of a register file nor to a same input of a crossbar
  • each output of each processing element is connected to the input of a register file (i) any output of any processing element and any other output of any processing element are not connected to the same input of a register file 0) the input of each register file is connected either to an output of a processing element or to a processing device input (k) the input of any register file and the input of any other register file are not connected to a same output of any processing element (I) the input of any register file and the input of any other register file are not connected to a same processing device input (m) each output of each registerfile is connected to an input of a crossbar
  • any output of any register file and any other output of any other register file are not connected to a same input of a crossbar
  • each input of each crossbar is connected either to an output of a register file or to a processing device input
  • any input of any crossbar and any input of any other crossbar are neither connected to the same output of any register file nor to a same processing device input
  • each processing device output is connected to the output of a crossbar
  • each input of each processing element is connected to the output of a crossbar
  • any processing device output and any other processing device output are not connected to the same output of a crossbar
  • any processing element input and any other processing element input are not connected to the same output of a crossbar
  • the output of each crossbar is connected either to a processing device output or to an input of a processing element
  • the output of any crossbar and the output of any other crossbar are neither connected to a same processing device output nor to a same input of a processing element
  • the application domain of 'stand alone' processing devices with a data path architecture based on the present invention is the same as the application domain of arrays of processing devices with data path architectures based on the present invention and consists of applications within image/multimedia/signal processing, graphics processing and linear algebra.
  • the present invention concerns a processing device according to claim 1 and an array of processing devices according to claim 8.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

L'invention concerne des architectures de trajet de données de dispositifs de traitement de données à fichier registre réparti. Ces architectures résultent de l'application d'une série de règles de construction à une série de blocs de construction. Le nombre de fichiers registres correspond au nombre d'entrées de dispositifs de traitement et de sorties d'éléments de traitement. Des règles spécifiques de connexion des fichiers registres aux éléments de traitement par crossbar de type réparti sont établies. L'invention concerne également des alignements de dispositifs de traitement. Les architectures de trajet de données des dispositifs de traitement propres à ces alignements diffèrent légèrement des architectures de dispositifs de traitement autonomes.
PCT/EP2000/000259 2000-01-14 2000-01-14 Dispositif de traitement de donnees a fichier registre reparti WO2001052060A1 (fr)

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Application Number Priority Date Filing Date Title
EP00904914A EP1161722A1 (fr) 2000-01-14 2000-01-14 Dispositif de traitement de donnees a fichier registre reparti
PCT/EP2000/000259 WO2001052060A1 (fr) 2000-01-14 2000-01-14 Dispositif de traitement de donnees a fichier registre reparti

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PCT/EP2000/000259 WO2001052060A1 (fr) 2000-01-14 2000-01-14 Dispositif de traitement de donnees a fichier registre reparti

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003083649A1 (fr) * 2002-03-28 2003-10-09 Koninklijke Philips Electronics N.V. Processeur a mot d'instruction tres long
WO2003085516A1 (fr) * 2002-04-10 2003-10-16 Koninklijke Philips Electronics N.V. Système de traitement de données
JP2013516006A (ja) * 2009-12-29 2013-05-09 エンパイア テクノロジー ディベロップメント エルエルシー エネルギー効率のよいマルチコアプロセッサのための共用メモリ

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EP0657802A2 (fr) * 1993-11-30 1995-06-14 Texas Instruments Incorporated Registre à rotation pour la transformation orthogonale des données
US5692139A (en) * 1988-01-11 1997-11-25 North American Philips Corporation, Signetics Div. VLIW processing device including improved memory for avoiding collisions without an excessive number of ports

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US5692139A (en) * 1988-01-11 1997-11-25 North American Philips Corporation, Signetics Div. VLIW processing device including improved memory for avoiding collisions without an excessive number of ports
EP0657802A2 (fr) * 1993-11-30 1995-06-14 Texas Instruments Incorporated Registre à rotation pour la transformation orthogonale des données

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MAKOTO IKEDA ET AL: "DATA BYPASSING REGISTER FILE FOR LOW POWER MICROPROCESSOR", IEICE TRANSACTIONS ON ELECTRONICS,JP,INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, vol. E78-C, no. 10, 1 October 1995 (1995-10-01), pages 1470 - 1472, XP000550056, ISSN: 0916-8524 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003083649A1 (fr) * 2002-03-28 2003-10-09 Koninklijke Philips Electronics N.V. Processeur a mot d'instruction tres long
WO2003085516A1 (fr) * 2002-04-10 2003-10-16 Koninklijke Philips Electronics N.V. Système de traitement de données
US7249244B2 (en) 2002-04-10 2007-07-24 Nxp B.V. Data processing system
JP2013516006A (ja) * 2009-12-29 2013-05-09 エンパイア テクノロジー ディベロップメント エルエルシー エネルギー効率のよいマルチコアプロセッサのための共用メモリ
US9367462B2 (en) 2009-12-29 2016-06-14 Empire Technology Development Llc Shared memories for energy efficient multi-core processors

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