WO2001050519A3 - Method of minimizing placement-related defects in the placement of semiconductor chips and other microelectronic components - Google Patents

Method of minimizing placement-related defects in the placement of semiconductor chips and other microelectronic components Download PDF

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Publication number
WO2001050519A3
WO2001050519A3 PCT/IB2000/001964 IB0001964W WO0150519A3 WO 2001050519 A3 WO2001050519 A3 WO 2001050519A3 IB 0001964 W IB0001964 W IB 0001964W WO 0150519 A3 WO0150519 A3 WO 0150519A3
Authority
WO
WIPO (PCT)
Prior art keywords
placement
pad
acceptable
effectual
nearest
Prior art date
Application number
PCT/IB2000/001964
Other languages
French (fr)
Other versions
WO2001050519A2 (en
Inventor
Peter Borgesen
Original Assignee
Universal Instruments Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universal Instruments Corp filed Critical Universal Instruments Corp
Priority to AU18798/01A priority Critical patent/AU1879801A/en
Publication of WO2001050519A2 publication Critical patent/WO2001050519A2/en
Publication of WO2001050519A3 publication Critical patent/WO2001050519A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A method is provided for minimizing placement-related defects in the placement of semiconductor chips or other microelectronic components with conductive bumps onto substrates with corresponding conductive pads using a placement machine having tolerances. A minimum-acceptable bump-center-to-nearest-pad-boundary distance and an acceptable defect level are determined. An effective minimum-acceptable bump-center-to-nearest-pad-boundary distance is then determined based on the tolerances of the machine, the minimum-acceptable bump-center-to-nearest-pad-boundary distance, and the acceptable defect level. Next, the positions of centers of selected bumps on the semiconductor chip and the positions of boundaries of conductive pads corresponding to the selected bumps are determined. Next, the boundaries of a modified pad region corresponding to the effective minimum-acceptable bump-center-to-nearest-pad-boundary distance are determined. Next, it is determined whether an effectual shift-and-rotation that places all the centers of the selected bumps within the boundaries of the modified pad region exists. If such an effectual shift-and-rotation exists, the effectual shift-and-rotation is optimized. If such an effectual shift-and-rotation does not exist, the substrate is rejected.
PCT/IB2000/001964 1999-12-30 2000-12-22 Method of minimizing placement-related defects in the placement of semiconductor chips and other microelectronic components WO2001050519A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU18798/01A AU1879801A (en) 1999-12-30 2000-12-22 Method of minimizing placement-related defects in the placement of semiconductorchips and other microelectronic components

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47504099A 1999-12-30 1999-12-30
US09/475,040 1999-12-30

Publications (2)

Publication Number Publication Date
WO2001050519A2 WO2001050519A2 (en) 2001-07-12
WO2001050519A3 true WO2001050519A3 (en) 2001-12-06

Family

ID=23886005

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2000/001964 WO2001050519A2 (en) 1999-12-30 2000-12-22 Method of minimizing placement-related defects in the placement of semiconductor chips and other microelectronic components

Country Status (2)

Country Link
AU (1) AU1879801A (en)
WO (1) WO2001050519A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0273561A2 (en) * 1986-12-23 1988-07-06 Nortel Networks Corporation Automated positioning system
US4980971A (en) * 1989-12-14 1991-01-01 At&T Bell Laboratories Method and apparatus for chip placement
US5383270A (en) * 1992-06-05 1995-01-24 Yamahahatsudoki Kabushiki Kaisha Method for mounting component chips and apparatus therefor
EP0895450A2 (en) * 1997-07-28 1999-02-03 Matsushita Electric Industrial Co., Ltd. Component feeder and mounter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0273561A2 (en) * 1986-12-23 1988-07-06 Nortel Networks Corporation Automated positioning system
US4980971A (en) * 1989-12-14 1991-01-01 At&T Bell Laboratories Method and apparatus for chip placement
US5383270A (en) * 1992-06-05 1995-01-24 Yamahahatsudoki Kabushiki Kaisha Method for mounting component chips and apparatus therefor
EP0895450A2 (en) * 1997-07-28 1999-02-03 Matsushita Electric Industrial Co., Ltd. Component feeder and mounter

Also Published As

Publication number Publication date
WO2001050519A2 (en) 2001-07-12
AU1879801A (en) 2001-07-16

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