WO2001045265A1

WO2001045265A1 - Averaging cell mismatches in integrated circuits

Info

Publication number: WO2001045265A1
Application number: PCT/US2000/033870
Authority: WO
Inventors: Kevin Johnstone; Yusuf A. Haque; Mark Albert Pinchback
Original assignee: Maxim Integrated Products
Priority date: 1999-12-14
Filing date: 2000-12-14
Publication date: 2001-06-21
Also published as: US6356225B1

Abstract

An integrated circuit includes matched cells (12, 14), each having an active transconductor (18), wherein the matched cells are coupled together through respective active transconductor circuits to average the effects of all mismatches. Each cell of the matched cells may have a first differential gain stage coupled to a second differential gain stage that is coupled to an output buffer stage (16), and an associated active transconductor circuit (18). The active transconductor of each cell is coupled to the gain stage of other cells to average the effect of cell mismatches.

Description

AVERAGING CELL MISMATCHES IN INTEGRATED CIRCUITS

Background of the Invention

This invention relates to systems and methods of averaging cell mismatches in integrated circuits, such as "flash" analog-to-digital converters (ADCs).

Many integrated circuits, such as analog-to-digital converters and digital-to- analog converters, are formed from a plurality of matched cells - that is, each cell has the same design and, ideally, should have the same operating characteristics. It is well known, however, that slight mismatches in the components of the cells are unavoidable in practical systems, and that such mismatches have an undesirable impact on the operating performance. For example, cell mismatches occurring in a flash ADC may adversely affect the differential nonlinearity and the integral nonlinearity. Differential nonlinearity is a measure of nonuniform step size between adjacent code transitions; integral nonlinearity is a measure of the deviation of the code center line from an ideal straight line drawn through the end points of the transfer characteristic.

Techniques for reducing the impact of cell mismatches in flash ADCs have been proposed. For example, Kattmarm (U.S. Patent No. 5,175,550) has proposed a flash ADC that includes a network of equal -valued resistors each of which is coupled between corresponding points of a pair of adjacent differential input cells of the ADC. Bult (U.S. Patent No. 5,835,048) has proposed a flash ADC that includes the same resistor network.

Summary of the Invention

In one aspect, the invention features an integrated circuit, comprising a pair of matched cells. Each cell has an active transconductor circuit associated with the cell, wherein the matched cells are coupled together through respective active transconductor s. The active transconductors generate currents which are used to average the effect of cell mismatches.

Embodiments may include one or more of the following features. Each cell may include first and second differential gain stages, an output buffer stage and a latch, with an active transconductor circuit coupled to the output of the second gain stage. The active transconductor circuit associated with each cell may include a differential pair of transistors controlled by the output of the output buffer stage of the associated cell and connected to the output of the second gain stage of the adjacent cells.

As used herein, the term "active transconductor" refers to one or more active circuit components (e.g., transistors) configured to convert a received input voltage into an output current.

In another aspect, the invention features an integrated circuit comprising several matched cells, each having a differential input stage, a gain stage and output buffer stage and a latch, and a transconductor circuit associated therewith, wherein the transconductor circuit of each cell is responsive to the output of the output buffer stage and is coupled to the gain stage of other cells to average the effect of cell mismatches.

Embodiments may include one or more of the following features.

A plurality of additional matched cells each having a differential input stage, a gain stage, an output buffer stage and a latch, and a transconductor circuit associated with each additional cell. The cells may be grouped with each having the associated transconductor circuit responsive to the output of the output buffer stage of that cell and coupled to the output of the second gain stage of the adjacent cells to provide currents to adjacent cells, thereby averaging the effect of cell mismatches. The transconductor circuit of each cell is an active transconductor circuit and may include a pair of differential pairs of bipolar transistors.

Among the advantages of the invention are the following.

The invention substantially reduces the impact of cell matching problems by generating currents to average cell mismatches. Since the transconductor circuit includes active devices, the impedance seen by the output of the preceding output buffer stage is high enough to not appreciably cause a gain attenuation of the gain stage of the cell. Also, by applying the generated currents to the output of the gain stage, rather than to the input stage, the impact of variations in the transconductors is reduced. Other features and advantages will become apparent from the following description, including the drawings and the claims.

Brief Description of the Drawings

Fig. 1 is a block diagram of an integrated circuit cell that includes an active transconductor.

Fig. 2 is a block diagram of a plurality of cells with pairs of adjacent cells coupled together to distribute offset averaging currents.

Fig. 3 is a circuit diagram of an integrated circuit cell that includes an active transconductor.

Fig. 4 is a circuit diagram of a plurality of cells with pairs of adjacent cells coupled together to distribute offset averaging currents.

Detailed Description

The following embodiments are described in connection with a flash ADC integrated circuit. The invention, however, may be used in other kinds of integrated circuits containing matched cells.

Referring to Figs. 1 and 2, a cell (I) of a flash ADC integrated circuit includes a first differential gain stage 12, a second gain stage 14, an output buffer stage 16 and a latch 40. The active transconductor circuit 18 is also associated with each cell. Differential input stage 12 is coupled to receive a voltage (V_m) and a reference voltage (V_ref.l) and is configured to produce amplified voltages Vj j and VQ J; the gain of differential input stage 12 may be about two to three. Gain stage 14 amplifies voltages V and V J with a gain of about five to produce voltages V'j and VQ J. AS explained in detail below, gain stage 14 also is coupled to receive currents Iχπ+i), IC(I+1) ^an<^ IT I-l)' Ic(l-l) fr°^m adjacent cells (1+1) and (1-1), respectively. The distribution of the currents among the coupled cells averages the adverse effects of component mismatches on the transfer characteristics of the ADC. Output buffer stage 16 receives amplified voltages V'j and Y'Q and provides a low impedance output to latch 40. Latch 40 is configured to produce an output voltage

that corresponds to a binary "1" or binary "0" depending upon the relative values of the input voltages V_m and V_ref . In particular, V_out(i) corresponds to a binary "1" when V_m exceeds V_ref , and Vout(I) corresponds to a binary "0" when V_m is less than V_ref .

Active transconductor circuit 18 also receives the output of output buffer stage 16 and is configured to produce currents ITYJ) and I I) which are distributed to adjacent cells (1-1) and (1+1). The currents Ij and IC(I) have ^a high source impedance and include a current component responsive to the output of the output buffer stage 16.

As shown in Fig. 2, cells (1-1) and (1+1) are coupled to receive respective reference input voltages V_re _i) and V_rem+ι γ The reference input voltages for each of the cells (1-1), (I) and (1+1) each correspond to a different progressive fraction of a voltage reference and may be provided by a resistor ladder network coupled between the voltage reference and a ground reference. The binary outputs of cells (1-1), (I) and (1+1) are coupled to known logic circuitry which is configured to produce an ADC voltage transfer characteristic from the cell outputs V_oujγj_i), V_out and V_0ut(τ+1

The cells (1-1), (I) and (1+1) are designed to be matched - that is, the cells are designed to have the same transfer characteristics. Practical integrated circuit fabrication techniques, however, are unable to perfectly match the cell components (e.g., resistors and transistors) and, consequently, slight differences in the transfer characteristics of each of the cells will exist. These differences may result in an undesirable level of differential nonlinearity and integral nonlinearity in the ADC transfer characteristic. The invention substantially reduces the impact of cell matching problems by generating currents to average the effect of cell mismatch among adjacent cells through active transconductor circuits 18. This effectively averages the cell offset errors across the entire transfer function of the ADC. The resulting cell offset errors are substantially reduced.

Referring to Fig. 3, in one embodiment, an ADC cell (I) may be implemented using BICMOS circuit fabrication techniques. Input stage 12 includes a CMOS differential input stage 20 which has a gain of about two to three. The voltages produced at the output of differential input stage 20 are applied to the inputs of differential gain stage 14, the output of which is buffered by an emitter-follower output buffer stage 16. The currents Iχ(i-i), ∑C(I-l) and Iτ(l+1 Ic(l+1) f°^r averaging the effect of cell mismatches which are received from cells (I-l) and (I+l) are applied to nodes 26 and 28 of gain stage 14, as shown.

Active transconductor circuit 18 is coupled to the output buffer stage 16 and is implemented as a degenerated, dual differential bipolar transistor pair, the dual differential transistor pairs being driven in unison by the output of the output buffer stage 16. When the output of the output buffer stage is zero, each transistor in the dual differential transistor pair generates or conducts the same amount of current, namely one fourth of the two current sources supplying current to the two ends of the degeneration resistor. When the output of the output buffer stage is not zero, one transistor in each dual differential transistor pair generates or conducts an increased current, and the other transistor in each dual differential transistor pair generates or conducts a corresponding decreased current, each in proportion to the output of the output buffer stage. In either case, the active transconductors steer the current of the current sources. The currents Iχ(i) and Ic(I) are distributed from cell (I) to cells (I-l) and (I+l) through nodes 32, 34, 36 and 38 of active transconductor 18. Because active transconductor circuit 18 includes active devices, the impedance seen by the output buffer stage 16 is relatively high. Since the output impedance of the output buffer stage 16 is low, the gain attenuation of gain stage 14 is minimal.

In operation, mismatches in differential input stage 12 and in gain stage 14 produce a voltage difference between nodes 26 and 28. This voltage is converted into a proportional current component by active transconductor circuit 18 and coupled to the output of the gain stage of adjacent cells. (Note that even if the differential output of the output buffer stage of a cell is zero, equal currents will be generated at all four nodes 32, 34, 36 and 38 of the cell and be coupled to adjacent cells.) The coupling of the generated currents from one cell to an adjacent cell is such as to cause the output of the gain stage and thus the output of the output buffer stage of the adjacent cell to shift in the direction of the output of the output buffer stage of the cell generating the currents, thereby tending to decrease differences between cells.

Latch 40 is implemented with CMOS transistors and is coupled to receive a latch command (LAT). Subsequent to a latch command, the input stage of the cell is disabled and the logic state at the output of the cell is stored until an "enable" or "unlatched" command is received.

Fig. 4 shows an integrated circuit for a flash ADC that includes twenty-one cells, with adjacent cells coupled together through respective active transconductors to distribute the effects of cell mismatch among the coupled cells. In this way, the input referred voltage offsets of individual cells are averaged. As explained above, this feature improves the linearity of the DC transfer function associated with the group of cells.

Other embodiments are with the scope of the claims. Although the above embodiments have been described as having a limited number of cells, other embodiments may contain a greater number of cells. Also, the cells of other embodiments may include a greater number of connections between the cells. For example, in addition to distributing currents due to cell mismatch between the nearest neighboring cells, each cell may also exchange currents due to cell mismatch with next- to-nearest neighboring cells (not necessarily of the same magnitude); in some embodiments, each cell may exchange cell mismatch currents with each of the other cells of the integrated circuit.

Claims

WHAT IS CLAIMED:

1. An integrated circuit comprising a plurality of matched cells each having active transconductors associated therewith, wherein the matched cells are coupled together through respective active transconductors to average the effect of cell mismatches.

2. The integrated circuit of claim 1 wherein each cell comprises a gain stage, an output buffer stage and a latch, each cell having active transconductors associated therewith and responsive to the output of the respective output buffer stage to provide currents to the output of the gain stages of adjacent cells to average the effect of cell mismatches.

3. The integrated circuit of claim 1 wherein each cell comprises first and second gain stages, an output buffer stage and a latch, each cell having active transconductors associated therewith and responsive to the output of the respective output buffer stage to provide currents to the output of the second gain stages of adjacent cells to average the effect of cell mismatches.

4. The integrated circuit of claim 3 wherein the first and second stages and the output buffer stage are differential stages.

5. The integrated circuit of claim 1 wherein the active transconductors of each cell comprise at least one differential pair of transistors.

6. The integrated circuit of claim 5 wherein the transistors are bipolar transistors.

7. A method of averaging the effect of cell mismatches in a plurality of matched cells comprising: generating currents responsive to the output of each cell; and, coupling the generated currents to adjacent cells to encourage the output of the adjacent cells toward the output of the cell generating the respective currents.

8. The method of claim 7 wherein the currents are generated responsive to the output of each cell by steering the currents of current sources responsive to the output of each cell.

9. The method of claim 8 wherein each cell has an output buffer stage, wherein the currents responsive to the output of each cell are responsive to the output of the output buffer stage of the respective cell, and the generated currents are coupled to the input of the output buffer stages of adjacent cells to encourage the output of the adjacent cells toward the output of the cell generating the respective currents.