WO2001045212A1

WO2001045212A1 - High density, high frequency linear and area array electrical connectors

Info

Publication number: WO2001045212A1
Application number: PCT/US2000/003843
Authority: WO
Inventors: Che-Yu Li; Matt A. Korhonen; Weimin Shi
Original assignee: High Connection Density, Inc.
Priority date: 1999-12-14
Filing date: 2000-02-15
Publication date: 2001-06-21
Also published as: TW498574B

Abstract

Electrical connections are made between daughter cards and mother boards and between a chip carrier and an interposer (16) by using receptacle holes (24) or Plated Through Holes (PTH) structures in the mother board itself or the interposer (16). Fingers (22a) protrude from the contact pad and serves as a bending protrusions of spring like contact element. The metal layer of the flanges can be either built up by well known additive or subtractive PCB fabrication technique, or formed or stamped separately, then laminated. The connectors can be fabricated in sparsely or fully populated linear or area arrays.

Description

HIGH DENSITY, HIGH FREQUENCY LINEAR AND AREA ARRAY ELECTRICAL CONNECTORS

Field of the Invention:

The invention pertains to the field of electrical connectors and, more particularly, to high density, interfitting insert connectors suitable for high frequency integrated circuit chips or board-level connections.

BACKGROUND OF THE INVENTION

It is now a cliche and an understatement that computer technology is advancing rapidly. The demand for ever increasing computing power in this age of digital imagery, telecommunications, and Internet applications shows no sign of diminishing. The challenge for electrical engineers and logic designers is to create ever faster and ever more densely packed solid state electronic components in ever smaller sizes.

A host of unforeseen problems occurs when the components to be mounted and connected are designed for use at high frequencies, reaching and exceeding 500 MHz. With conventional pin and socket connectors, the phenomenon of crosstalk or noise, for example, becomes significant. It has been discovered that the longer the length of the pin the more it contributes to noise in the connection.

As the clock rate or frequency of component operation increases, it is critical to minimize the current loop common area between the signal lines or nets to reduce or eliminate crosstalk between signal lines. For this reason, it is necessary to reduce the connector stack height. Portable devices, such as notebook computers and cell phones, also benefit from a reduction in connector stack

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currently in high demand in the microelectronics industries. Most conventional PGA connections use molded pin carriers and interposers that contain the receptacle sockets, the coefficients of thermal expansion (CTEs) of which, unfortunately, cannot be matched with those of the glass/epoxy substrates. Conventional PGA connectors utilize parts for both pins and receptacles that are mechanically formed (e.g., stamped or coined) and are relatively costly. Generally, pin grid array connectors are not suitable for high frequency applications because of their stack height and due to the fact that they can not be easily shielded.

In United States Patent No. 5,199,879, granted to Kohn et al . , a pin/hole connection is disclosed for use with a PCB substrate. Metallized polyimide tabs are disposed on the receptacle hole edge, extending inwardly towards the receptacle hole center. Such metallized tab structures are analogous to those applied in tape-automated bonding (TAB) technology, but are beyond commonly practiced, cost- effective printed circuit board (PCB) technology. Due to lever action, which counters the adhesion of the metallized tab, repeated insertion tends to cause delamination. The structure of Kohn is not amenable to connection directly to a plated through hole (PTH) . Therefore, the KOHN design requires two plated through holes, one for pin insertion and a second for the electrical connection to the pin. Such a configuration is commonly known as via aside construction. Furthermore, the design of the KOHN tabs offers very limited spring action reducing the reliability of the connection after repeated matings. Although the connector of Kohn uses PCB technology which is preferable, it falls short of the objectives of the present invention.

In the present invention the pins are directly connected to a single plated through hole and the need for only a single hole allows for much greater densities in the interconnections. The actual construction of the inventive connection pads by PCB manufacturing technologies, ensures better adhesion of the top pad to the plated through holes. Also, the contact tabs are more robust than can be manufactured by the conventional PCB technology.

In United States Patent No. 4,950,173, issued to

Minemura, a pin/hole connection is described in which the female receptacle is made of a shape memory alloy to allow a very low or zero insertion force. However, this method necessitates that the mating temperature of the contact is different from the service temperature. The use of shape memory alloys requires special considerations that may not easily be met in practice.

In "Analysis of an Interference-Fit Pin Connection", by R.P. Goel, April 24-26, The Institute of Electrical & Electronic Engineers, Inc., pp. 116-120, 1978; and in "IEEE Transactions on Components, Hybrids, and Manufacturing Technology", by the same author, 0148-6411/78/0900-0248, pp. 248-251, September, 1978, a compliant fit pin is directly inserted into plated through holes in an organic substrate or printed circuit board. This AT&T pin design can be applied for attaching a chip carrier to a PCB substrate. In this reference, the connecting pins contain a bulb-like section of enlarged dimensions in the middle of the pin. These bulb-like middle sections, mating with sidewalls of the plated through holes when pins are inserted therein, provide an area of good metal -to-metal electrical contact. However, difficulties arise because exceedingly high insertion forces are required to initiate the plastic deformation in the bulb-like pin section.

In United States Patent No. 5,278,005 for SELF- ASSEMBLED LOW- INSERTION FORCE CONNECTOR ASSEMBLY, hereby incorporated by reference, an electrical connection concept is described, based on the use of a buckling element and a tapered pin. Such a tapered pin, in combination with a stiff buckling component, must have a working distance that b accommodates inaccuracies in pin and hole diameters. That working distance increases the stack height, limiting its application to low profile devices, such as notebook computers and cellular phones. The stack height also limits the use of this connector type for high frequency applications. In the aforementioned patent, a number of embodiments are discussed, including their applications, especially for connections in a computer. The present invention involves embodiments that implement innovative concepts beyond those disclosed in the aforementioned patent application, and with a broader range of application.

It would be advantageous to provide a cost effective, high density connector system for use with components that operate at high frequencies.

It would also be advantageous to provide a connector system that reduces or eliminates crosstalk or noise between components mounted on the same card and between daughter cards and the mother board.

It would further be advantageous to provide a connector system that reduces such noise without using conventional shielded wires.

It would also be advantageous to provide a system that provides wire shielding in the connector itself and that may be implemented with relatively short pins to maintain a low profile of the overall device and to reduce coupling noise .

It would still further be advantageous to provide a connector system that includes demountable connectors disposed in the substrate to which are mounted a plurality of integrated circuit cards. It would also be advantageous to provide a connector system that matches the coefficient of thermal expansion of the chip carrier with that of the mother board and that of the pin carrier.

It would also be advantageous to provide a high- density, high frequency connector system having a low profile .

In addition, it would be advantageous to provide a high density, high frequency connector system which provides matching of thermal coefficients of expansion between connected components.

It would still further be advantageous to provide a high density, high frequency connector system providing impedance matching between the connected components.

SUMMARY OF INVENTION

In accordance with the present invention, there is provided a new type pin grid array electrical connection. A connecting pin array is attached to a first electrical circuit component, such as a chip carrier. The array is electrically connected to an array of receptacles contained in an interposer, attached to a second electrical circuit component, such as a printed circuit board. The interposer of the present invention consists of holed connecting pads, fabricated on the surface of a dielectric substrate itself. The substrate is preferably an FR-4 epoxy/glass composite. Fingers or flanges protrude from the center-holed contact pad and serve as the bending beams of spring-like contact elements. The flanges, in the plane of the PCB, allow the small PCB hole to accommodate the connector tolerance, while providing durability, with bending and/or torsion of the flanges. The metal layer of the flanges can either be fabricated by the conventional build-up and/or subtractive techniques, or formed or stamped separately, then laminated.

BRIEF DESCRIPTION OF THE DRAWINGS

A complete understanding of the present invention may be obtained by reference to the accompanying drawings, when considered in conjunction with the subsequent detailed description, in which the same reference numbers refer to the same parts throughout the different views, and in which:

FIGURE la is a cross-sectional view of receptacle disposed in an interposer structure, in accordance with the present invention;

FIGURE lb is a top view of the receptacle disposed in an interposer structure shown in FIGURE la;

FIGURE lc is a bottom view of the receptacle disposed in an interposer structure shown in FIGURE la;

FIGURE 2a is a cross-sectional view of a receptacle disposed in a printed circuit board including a receptacle pad that overhangs a plated through hole, forming a flange- like protrusion in accordance with the invention;

FIGURE 2b is a top view of the receptacle disposed in a printed circuit board shown in FIGURE 2a;

FIGURE 2c is a bottom view of the receptacle disposed in a printed circuit board shown in FIGURE 2a;

FIGURE 3a is an enlarged view of a first, alternate embodiment of receptacle pads, showing flange-like protrusions formed therein; and FIGURE 3b is an enlarged view of a second, alternate embodiment of receptacle pads, showing flange-like protrusions formed therein.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention utilizes an array of generally cylindrical pins which may be tapered. The pins are engaged by an array of contact pads having a center hole, with protruding finger-like flange or beam contact elements. Electrical connections are created by spring- like bending action of the protruding metallic fingers or flanges interacting with the array of pins.

The pin/socket linear or area array connectors of the present invention utilize printed circuit board technologies for design and manufacturing. The primary purpose of the connector system of the present invention is to provide high density, cost-effective, pin/socket type, linear or area array connections having superior electrical performance .

PCB technology, with receptor flanges laminated to the PCB or etched on the PCB, enables the construction of high density, extremely thin, low profile connectors, in comparison with bulky springs in the molded, matrix-type connectors of the prior art .

The printed board technology provides means to fabricate the carrier for the pin arrays. In such a system, the coefficient of thermal expansion of the chip carrier, the mother board, the pin carrier, and any interposers can be relatively easily matched to maximize connection reliability during thermal cycles encountered in service. In the present invention, the flanges, the contact pads, and interconnecting traces may be fabricated by either subtractive or additive metallization processes. In a subtractive process, for example, an existing conductive surface layer may be selectively etched to provide the required flange or beam pattern at a hole (e.g., a plated through hole) . In an additive process, the flange or finger element may be pre-formed by a stamping or similar operation and then laminated to the surface of an existing PCB or similar structure. As well, ground planes and traces can be fabricated in the same way in order to provide shielding and impedance control .

The interconnections between the top and bottom surfaces of the PCB, as well as of the intermediate metallization layers, are generally accomplished by plated through holes, solid vias, or blind vias. Other interconnection strategies well known to those skilled in the art may also be employed when appropriate.

Low cost, cylindrical pins may be used, thereby reducing the higher profile and the working length usually required by tapered pins to accommodate variations in pin and hole sizes.

High speed, high frequency circuit design requires that current loop areas be minimized. This is accomplished by locating any decoupling capacitors as close as possible to the active elements that they service. Such decoupling capacitors or other passive electrical components may be either discrete and mounted on the PCB, or may actually be embedded in the PCB itself. Molded connectors of the prior art cannot accommodate this need for locating the capacitors and/or other components at suitable distances from the active circuits. The small bulk of the inventive connector, however, allows much closer placement of these capacitors or other components. Discrete components, for example, may be located on the top surface of a PCB near

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Ω SD rt 3 CO CD 0 μ- rt μ- CQ TJ 3 ri μ- Φ ri H 3 Hi H < ω rt 0 3 μ-

SD tr SD tr Φ 3 Ω 3 μ- 3 — ' ri SD Φ 3 μ- SD ri tr φ 1 μ- H SD φ Φ

3 o Φ Ω SD Φ Φ <! Φ μ- 3 CQ Ω 3 TJ rt Φ Φ 3 tr 3 ^• ri O

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TJ Ω 0 0 Ω CQ tr H ri Φ ri rr μ- Ω 0 Ω Φ -¹ tr 3 3 SD 3 i μ- φ 0 ri tr rt CQ φ 0 0 μ- Ω tr rt ii tr Ω *< CO Ω (X SD 3 ri Hi r-h rt

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Ω SD Ω rt 3 tr rt SD ri ii 3 3 0 3 TJ rt 0 tr Ω tr i Ω tr 3 0 Φ h-¹ tr CQ Φ tr Ω φ μ- Φ 0 tr Φ 3 3 co SD SD 3 3 rt i 0 0 μ- CQ Hi Φ Φ CO φ ^•—• 0 Hi ^ CO CO φ tr CQ 3 0 μ- Φ μ- Hi 3

TJ Φ rt CD - Φ SD ϋ rt μ- rt μ- Φ Φ 0 Φ rt

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0 Φ H μ- 3 ri 3 < ri rt Φ Φ H rt 0 μ- rt Φ rt

H Φ 0 α 3 SD Φ rt tr 3 • ; ri Φ 3 SD

H SD φ CO CD SD ^•

Because the pin and receiving hole/flange structure may be manufactured from materials having closely-matched CTEs, the task of creating a high-reliability connector system is simplified. In general, larger and denser arrays are made possible by the present invention when compared to those of the prior art .

An important application of the pin grid array connector of the present invention is to electrically and mechanically mate a chip carrier containing, for example, a CPU and memory chips, to a PCB having glass/epoxy laminated substrates and glass/epoxy pin carriers.

Referring now to FIGURES la, lb and lc, there are shown cross-sectional, top, and bottom views, respectively, of a substantially cylindrical, electrically conductive pin 10 and corresponding receptacle 12 disposed in an interposer structure 16. Such interposer structures 16 generally have a great number of receptacles 12 into which a plurality of pins 10 are inserted and engaged. For purposes of this description, however, only one pin 10 and one receptacle 12 are shown.

The pin 10 shown in FIGURE la is substantially cylindrical, but it should be understood that the scope of the invention is intended to include other cross-sectional geometries of the pin, such as square, rectangular, elliptical, polygonal and irregular shapes. The pin 10 may also be tapered in order to facilitate insertion and tight mechanical and electrical connection to the receptacle 12.

Interposer 16 is made of a core 32 of conventional glass/epoxy composite (e.g., FR-4 or its equivalent). It should be noted that other well known dielectric materials can be used for core 32.

A solid plated through hole wall 25 of copper or a copper alloy is deposited using conventional printed circuit board fabrication techniques well known to those skilled in the art. Land pads and flange sections 22 and 22a can be fabricated in place by build-up and/or subtractive techniques. During plating, the underside of the flange may be plated at the same time as the PTH is formed. Such plating will reinforce the attachment of the flange to PCB preventing delamination during repeated pin insertions. The plating, when present, is also useful to ensure good electrical connection between top pads and flanges, and to bottom pads 27 and ball grid array (BGA) pads 29.

The inner edges 22a of each copper receptacle pad 22 overhangs as a finger-like or flange-like protrusion over the through hole 24 to allow a sufficient bending action when the connecting pin 10 is engaged. FIGURE lb shows a more detailed view of the geometry of the overhanging portion of pad 22 and protruding edges 22a. Note that besides build-up in place, the pad arrays with flanges can be formed separately, e.g. by stamping, and then laminated on the interposer.

Referring now also to FIGURE lc, there is shown a corresponding bottom view detail of bottom pad 27 and ball grid array (BGA) pads 29.

Referring to FIGURE la, there there are shown a ground planes 41 and traces 44, appropriately loacted to form integral built-in parts of the interposer. Also there can be traces or pads (not shown) for attaching discrete components such as capacitors as an integral part of the interposer structure.

Referring now to FIGURE 2a, there is shown a partial, sectional, schematic view of the inventive connector system applied directly to a printed circuit board (PCB) . A multi-layer PCB 40 is constructed from a number of layers of epoxy-glass 32 with interspersed conductive copper layers 41, 42, respectively. A hole has been drilled in PCB 40 and plated to form a plated through hole (PTH) 24.

Before lamination of PCB 40, copper layers 41, 42 are etched or otherwise prepared. Consequently, certain copper layers 42 continue to the edge of hole 24. Copper layers 41 or traces 44, serving for grounding, end a predetermined distance from the edge of hole 24, thereby preventing electrical connection to PTH 24. The construction of the flanges 22a and their interaction with conductive pin 10 are similar or identical to the interposer 16 (FIGURE 1) , as described hereinabove.

By utilizing the inventive construction directly with a PCB 40, the mechanical and electrical advantages already enumerated may be applied to a direct attachment of chip carrier to a card or mother board. In addition, the inclusion of ground planes 41 or traces 44 allows the design of an electrical interconnection system having distinct advantages over the prior art. First, shielding of the electrical signal passing through pin 10 into receptacle 22 and on into a wiring trace in or on PCB 40 may be accomplished easily. These ground planes or traces may be strategically placed to form a classic stripline transmission line having a predetermined characteristic impedance. This allows the innovative connector system to operate effectively with high frequency signals while still providing a connection density vastly superior to that available with prior art connectors.

The inventive connector system allows easy testing of a component; a component, such as a memory module, may be installed temporarily, affording great flexibility in assembling cards. The cards and components may first be assembled and then tested. Assuming that the assembly is good, the card assembly may then be wave-soldered, bonded with a conductive adhesive, or otherwise permanently

and advantages of the present invention.

Referring now to FIGURES 3a and 3b, there are shown plan views of two possible flange structure alternate embodiments. In FIGURE 3a there is shown a radial structure. This structure may be made more robust but with the trade-off of spring-back after withdrawal of the pin from the receptacle, due to the retentivity of the fingers.

FIGURE 3b shows a non-radial embodiment of the flange structure. This particular embodiment allows longer fingers to be used, which results in greater spring-back after pin withdrawal. The trade-off in this design is that narrower fingers must be used, resulting in a less robust structure than that of the embodiment shown in FIGURE 3a.

It should be obvious to those skilled in the art that numerous other flange designs could be chosen, each having a particular applicability and trade-off balance between retentivity and spring-back.

Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, this invention is not considered limited to the example chosen for purposes of this disclosure, and covers all changes and modifications which does not constitute departures from the true spirit and scope of this invention.

Having thus described the invention, what is desired to be protected by Letters Patent is presented in the subsequently appended claims.

What is claimed is:

Claims

1. An array of electrical connectors for attaching an electrical device having a plurality of electrically- conductive pins to a printed circuit, comprising: a planar printed circuit structure with a plurality of holes disposed therein, each of said holes comprising a central opening with an electrically conductive protrusion extending inwardly into said central opening, proximate one distal end thereof, so that said electrically-conductive pins of an electrical device fit into respective ones of said central openings of said holes, whereby when said pins are inserted into said holes, said protrusions deform, engaging said pins and producing a mechanically-retentive force thereupon, resulting in an electrically conductive connection therebetween.

2. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 1, wherein at least one of said plurality of holes comprises a plated through hole (PTH) .

3. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 2, wherein said printed circuit structure comprises a pin-receiving side and wherein said plurality of electrically-conductive pins is inserted into said plurality of holes from said pin-receiving side.

4. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 3, wherein said pin-receiving side of said printed circuit structure comprises an electrically-conductive pattern.

5. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 4, wherein said electrically-conductive protrusions form an integral part of said electrically-conductive pattern.

6. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 5, wherein said electrically-conductive protrusions are substantially co-planar with said electrically- conductive pattern, and are formed concurrently therewith.

7. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 6, wherein said plurality of holes is arranged in a predetermined pattern.

8. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 7, wherein said predetermined pattern of holes comprises a linear array.

9. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 7, wherein said predetermined pattern of holes comprises an area array.

10. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 6, wherein said electrically-conductive pins have a substantially circular cross section.

11. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 10, wherein said electrically-conductive pins are substantially cylindrical.

12. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 10, wherein said electrically-conductive pins are longitudinally tapered.

13. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 10, wherein said electrical device comprises at least one from the group: integrated circuit chip, chip carrier, daughter card, and multichip module.

14. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 13 , wherein said at least one electrical device has a coefficient of thermal expansion substantially matched to a coefficient of thermal expansion of said printed circuit .

15. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 5, wherein said electrically-conductive pattern comprises conductive pads proximate said plated through holes and said protrusions are subsequently added to said electrically-conductive pattern proximate said conductive pads after the formation of said electrically-conductive pattern.

16. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 15, wherein said protrusions are laminated to said electrically-conductive pads.

17. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 15, wherein said plurality of holes is arranged in a predetermined pattern.

18. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 17, wherein said predetermined pattern of holes comprises a linear array.

19. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 17, wherein said predetermined pattern of holes comprises a rectangular array.

20. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 17, wherein said electrically-conductive pins have a substantially circular cross section.

21. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 20, wherein said electrically-conductive pins are substantially cylindrical.

22. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 20, wherein said electrically-conductive pins are longitudinally tapered.

23. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 20, wherein said electrical device comprises one from the group of: chip carrier, integrated circuit chip, daughter board, and multichip module.

24. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 20, wherein said printed circuit structure comprises a mother board and said electrical device comprises a daughter card.

25. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 20, wherein said printed circuit comprises at least one ground plane disposed therein, said ground plane being adapted to interact with at least one of said array of electrical connectors to provide a shield to said at least one of said array of connectors .

26. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 20, wherein said printed circuit comprises at least one ground plane disposed therein, said ground plane forming a portion of a stripline transmission line.

27. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 20, wherein said printed circuit comprises traces and pads for discretes as capacitors.

28. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 23, wherein said stripline transmission line facilitates high frequency operation of said array of connectors .

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Φ rt ri Φ

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Φ 3 α

33. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 31, wherein said predetermined spacing of said array of PTHs comprises a first predetermined spacing along a first axis and a second predetermined spacing along a second, orthogonal axis.

34. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 31, wherein said first predetermined spacing of said array of PTHs is less than approximately 1.25 mm.

35. The array of electrical connectors for attaching an electrical device to a printed circuit as recited in claim 31, wherein said second predetermined spacing of said array of PTHs is less than approximately 1.25 mm.