WO2001042877A2 - Procede et systeme destines a ameliorer la largeur de bande dans un pont de bus - Google Patents

Procede et systeme destines a ameliorer la largeur de bande dans un pont de bus Download PDF

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Publication number
WO2001042877A2
WO2001042877A2 PCT/US2000/042497 US0042497W WO0142877A2 WO 2001042877 A2 WO2001042877 A2 WO 2001042877A2 US 0042497 W US0042497 W US 0042497W WO 0142877 A2 WO0142877 A2 WO 0142877A2
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WO
WIPO (PCT)
Prior art keywords
bus
bandwidth
bus bridge
delays
packets
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PCT/US2000/042497
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English (en)
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WO2001042877A3 (fr
Inventor
David V. James
Bruce Fairman
David Hunter
Hisato Shima
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Sony Electronics, Inc.
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Application filed by Sony Electronics, Inc. filed Critical Sony Electronics, Inc.
Priority to AU45142/01A priority Critical patent/AU4514201A/en
Publication of WO2001042877A2 publication Critical patent/WO2001042877A2/fr
Publication of WO2001042877A3 publication Critical patent/WO2001042877A3/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40058—Isochronous transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40065—Bandwidth and channel allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40071—Packet processing; Packet format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40078—Bus configuration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40091—Bus bridging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40117—Interconnection of audio or video/imaging devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462—LAN interconnection over a bridge based backbone
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462—LAN interconnection over a bridge based backbone
    • H04L12/4625—Single bridge functionality, e.g. connection of two networks over a single bridge
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/12—Discovery or management of network topologies
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5046—Resolving address allocation conflicts; Testing of addresses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5053—Lease time; Renewal aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5061—Pools of addresses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5076—Update or notification mechanisms, e.g. DynDNS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5092—Address allocation by self-assignment, e.g. picking addresses at random and testing if they are already in use
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2101/00—Indexing scheme associated with group H04L61/00
    • H04L2101/60—Types of network addresses
    • H04L2101/604—Address structures or formats
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2101/00—Indexing scheme associated with group H04L61/00
    • H04L2101/60—Types of network addresses
    • H04L2101/618—Details of network addresses
    • H04L2101/622—Layer-2 addresses, e.g. medium access control [MAC] addresses

Definitions

  • the present invention relates generally to audio, video, and audio /video interconnected systems for home and office use.
  • the present invention relates to a method and system for improving isochronous bandwidth in a bus bridge interconnect.
  • A/V consumer electronic audio/video
  • digital A/V applications such as consumer A/V device control and signal routing and home networking
  • various types of data in various formats can now be transferred among several audio /video control (AV/C) devices via one digital bus system.
  • AV/C audio /video control
  • Typical computer systems solve the bandwidth problem by increasing the bandwidth of the system bus to handle all of these forms, types and amount of data.
  • the system bus has become more clogged with information other than information directly utilized and needed by the main processor.
  • a first bus commonly referred to as a memory bus
  • a second bus is used for communications between peripheral devices such as graphics systems, disk drives, or local area networks.
  • a bus bridge is utilized to "bridge" and thereby couple, the two buses together.
  • IEEE 1394 standard serial bus implemented by IEEE Std 1394-1995, Standard For A High Performance Serial Bus, August 30, 1996 (hereinafter "IEEE 1394 standard”) and related other 1394 standards.
  • the IEEE 1394 standard is an international standard for implementing a high-speed serial bus architecture, which supports both asynchronous and isochronous format data transfers.
  • the IEEE 1394 standard defines a bus as a non-cyclic interconnect, consisting of bus bridges and nodes. Within a non- cyclic interconnect, devices may not be connected together so as to create loops. Within the non-cyclic interconnect, each node contains an AV/C device, and bus bridges serve to connect buses of similar or different types.
  • the primary task of a bridge is to allow data to be transferred on each bus independently without degrading the performance of the bus, except when traffic crosses the bus bridge to reach the desired destination on the other bus.
  • the bridge is configured to understand and participate in the bus protocol of each of the buses.
  • Multi-bus systems are known to handle the large amounts of information being utilized.
  • communication between buses and devices on different buses is difficult.
  • a bus bridge may be used to interface I/O buses to the system's high-performance processor /memory bus.
  • the CPU may use a 4-byte read and write transaction to initiate DMA transfers.
  • the DMA of a serial bus node When activated, the DMA of a serial bus node generates split- response read and write transactions which are forwarded to the intermediate system backbone bus which also implements serial bus services.
  • the host-adapter bridge may have additional features mandated by differences in bus protocols.
  • the host bus may not directly support isochronous data transfers.
  • the host- adapter bridge may enforce security by checking and translating bridge-bound transaction addresses and may often convert uncached I/O transactions into cache-coherent host-bus transaction sequences.
  • IEEE 1394 standard serial bus Each time a new device or node is connected or disconnected from an IEEE 1394 standard serial bus, the entire bus is reset and its topology is reconfigured.
  • the IEEE 1394 standard device configuration occurs locally on the bus without the intervention of a host processor. In the reset process, three primary procedures are typically performed; bus initialization, tree identification, and self identification.
  • bus initialization In the reset process, three primary procedures are typically performed; bus initialization, tree identification, and self identification.
  • a single node must first be established as the root node during the tree identification process in order for the reconfiguration to occur.
  • Bus bridges have an internal datapath that is of limited bandwidth.
  • the volume of isochronous data traffic passing through the internal data path of the bus bridge is sometimes low and sometimes high.
  • the isochronous data traffic has a worst case maximum volume as well as an average volume that may be significantly lower. For example during each cycle, one isochronous data packet may be sent. However, due to differnces in clock rates between nodes and the bus bridge, two isochronous data packets may occasionally be sent. For example, the extra packet may be only sent once every thousand cycles.
  • a method for averaging bandwidth requirements through a bus bridge system is disclosed.
  • Data packets are provided to a buffer, wherein the buffer contributes to an excess delay budget.
  • the excess delay budget is allocated among one or more bus bridges.
  • the data packets from the buffer are transmitted according to the excess delay budget allocation.
  • Figure 1 is a block diagram of one embodiment for an interconnect topology
  • Figure 2 is a block diagram of a device of Figure 1;
  • Figure 3 is a block diagram of one embodiment for a 1394 standard bus bridge system
  • Figure 4 is a block diagram of one embodiment for a 1394 bus bridge topology
  • Figure 5 is a block diagram of one embodiment for a looped bus bridge topology
  • FIG. 6 is a block diagram of one embodiment for bus bridge components
  • FIG. 7 is a block diagram of one embodiment for bus bridge isochronous transfer
  • FIG. 8 is a block diagram of another embodiment for bus bridge isochronous transfer
  • Figure 9 is a block diagram of one embodiment for 1394 bus bridge components
  • Figure 10 is an illustration of the bandwidth of isochronous data versus time
  • Figure 11A is a diagram of one embodiment of a stream of isochronous data packets having a below average bandwidth
  • Figure 11B is a diagram one embodiment of a stream of isochroous data packets having a below average bandwidth as transmitted from a bus bridge;
  • Figure 11C is a diagram of one embodiment of a stream of isochronous data packets having a greater average bandwidth
  • Figure 11D is a diagram of one embodiment of a stream of isochronous data packets having a greater than average bandwidth as transmitted from a bus bridge
  • Figure 12 is a block diagram of one embodiment for bus bridge topology
  • Figure 13 is a block diagram of one embodiment for a 1394 bus bridge topology 1400 for accumulating delay preferences
  • Figure 14 is a block diagram of one embodiment for a 1394 standard bus bridge system for confirming delay allowances of Figure 13;
  • Figure 15 is a flow diagram of one embodiment for the distribution of delays in a standard 1394 bus bridge system.
  • a method and system for improving bandwidth in a bus bridge are described.
  • Data packets are provided to a buffer, wherein the buffer contributes to an excess delay budget.
  • the excess delay budget is allocated among one or more bus bridges.
  • the data packets from the buffer are transmitted according to the excess delay budget allocation.
  • FIG. 1 is a block diagram of one embodiment for an interconnect topology 100.
  • server 102 is connected to a wide area network (WAN) 110 and to a bus bridge 170.
  • the bus bridge is interconnected to a number of audio, video, and/or audio/video devices, 120, 130, 140, 150, and 160.
  • the devices (120-160) are connected to bus bridge 170 via the IEEE 1394 standard serial bus.
  • Server 102 may be any device that is capable of connection to both a bus bridge 170 and wide area network 110, such as, for example, a personal computer or a set-top box.
  • network 110 may be a wide area network, such as, for example, the Internet, or a proprietary network such as America Online®, CompuServe®, Microsoft Network®, or Prodigy®.
  • WAN 110 may be a television communications network.
  • Server 102 includes a network interface which communicates with WAN 110.
  • Topology 100 includes high speed serial bus 180a and 180.
  • serial bus 180 is the IEEE 1394 standard serial bus.
  • Topology 100 includes various consumer electronic devices 120-160 connected via the high speed serial bus 180 to bus bridge 170.
  • the consumer electronic devices 120-160 may include, for example, a printer, additional monitor, a video camcorder, an electronic still camera, a video cassette recorder, digital speakers, a personal computer, an audio actuator, a video actuator, or any other consumer electronic device that includes a serial interface which complies with a serial interface standard for networking consumer electronic devices — for example, the IEEE 1394 standard.
  • Topology 100 may be contained within a home or office.
  • Bus bridge 170 is used to connect devices 120-160 in which devices 120-160 may be physically located within different rooms of the home or office.
  • any communication media may be used such as radio frequency (RF) communication or the like.
  • FIG 2 is a block diagram of a device 120.
  • device 120 may be a laser printer, digital camera, set-top box, or any other appropriate consumer electronic device capable of being connected via a high speed serial bus 180.
  • the device 120 includes a controller 202, memory 208, and I/O 210, all connected via bus 215.
  • Memory 208 may include, for example, read only memory (ROM), random access memory (RAM), and /or non-volatile memory.
  • I/O 210 provides connection with wide area network 110, bus bridge 170, and another peripheral device (130-160).
  • I/O 210 is a serial bus interface that complies with a serial interface standard for networking with consumer electronic devices (120- 161) and bus bridge 170 within topology 100.
  • the serial bus interface and topology 100 may use the IEEE 1394 standard serial bus.
  • I/O 210 provides for receiving signals from and transmitting signals to other consumer electronic devices (130-160) or bus bridge 170.
  • Memory 208 provides temporary storage for voice and data signal transfers between outside network 110 and topology 100.
  • memory 208 may buffer digital voice and data signals received by I/O 210 from WAN 110 before signals are transmitted onto IEEE 1394 standard bus 180.
  • Controller 202 controls various operations of device 120. Controller 202 monitors and controls the traffic through the device 120 to and from topology 100 and WAN 110.
  • Device 120 I/O 210 may have one or more physical ports.
  • a single port device discontinues the bus along the given branch of the bus, whereas devices with two or more ports allow continuation of the bus.
  • Devices with multiple ports permit a daisy chained bus topology, even though the signaling environment is point-to-point. That is, when a multi-port node receives a packet of data, the data is detached and retransmitted to the necessary port as indicated within the data. The configuration is performed dynamically as new devices are attached and /or removed from bus 180.
  • FIG. 3 is a block diagram of one embodiment for a 1394 standard bridge bus system 400.
  • system 400 includes bridge 402 which connects two or more buses 408 and 410.
  • Bus 408 and 410 may be the same or different types of buses.
  • bus 408 may be a 1394 standard serial bus and bus 410 may be a different high performance bus.
  • the 1394 standard bus architecture limits the number of nodes or devices 310 on a bus 263 and supports multiple bus systems via bus bridge 402.
  • CSR control and status register
  • ISO/IEC 13213 ANSI/IEEE 1212
  • CSR Information systems-Control and Status Registers
  • Microcomputer Buses defines the 1394 standard bus addressing structure, which allows approximately 2 16 nodes (404, 406, 412-420).
  • the CSR standard defines their registry, their functionality, and, where appropriate, where they appear in the address space.
  • Figure 3 is the simplest instance of a bus topology in which the net has one bus bridge.
  • Figure 4 illustrates a net that may have more than one bus bridge and, when so structured, is hierarchical in nature.
  • Figure 5 illustrates a network whose physical topology may have loops, but whose loops are electronically disabled to generate a hierarchical structure.
  • a collection of multiple buses connected through a bus bridge is referred to as a "net”.
  • FIG 4 is a block diagram of one embodiment for a 1394 bridge bus topology 500.
  • topology 500 has one prime portal 504 and one or more alpha portals 506 and 508.
  • the primary bus 525 has exactly one prime portal 504 and the secondary buses 527, 529, 531, 533, and 535 have exactly one alpha portal each — 506, 508 and 510.
  • Each bus 525-535 may have any number of secondary portals.
  • An alpha portal is on the path to a prime portal. Any portal not a prime portal or an alpha portal is a secondary portal.
  • the prime portal or the alpha portal may be referred to as a primary portal.
  • the bridge portal with the largest portal ID identifier is elected to become the prime portal 504.
  • the bridge portal with the smallest portal ID identifier is elected to become the prime portal 504.
  • Each portal appears as a node on its attached bus.
  • the bus with the prime portal 504 is termed the primary bus 525 and other buses 527-535 are termed secondary buses. On secondary buses 527-535, the bridge portal that leads to the primary bus 525 is called the alpha portal (506, 508).
  • any node within the interconnect may be accessed by its unique 16-bit node identification address.
  • the node identification address contains the bus ID and the local ID components. Referring to Figure 4, the bus identification IDs of nodes 512-524 are indicated by the letters a, b, and c and the local ID is indicated by the numbers 0-4.
  • Alpha portal 504 is responsible for rejecting missed address asynchronous data packets by accepting these requests and returning error reporting responses.
  • the previous and current prime and alpha portal identifiers are used to classify nodes when an interconnect topology changes, and the alpha portal is the isochronous clock reference for other nodes on the bus.
  • Bus bridge topology 500 may change and be established dynamically during operation of bus bridge system 500.
  • the bus bridge topology 500 is established during net refresh.
  • portals selectively route packets.
  • Asynchronous routing tables are stable until topology 500 changes during a net refresh or net reset operation.
  • Asynchronous routing tables are dynamic and are changed by their asynchronous connect and disconnect operations of the protocols.
  • FIG. 5 is a block diagram of one embodiment for a looped bus bridge topology 600.
  • portal 606 may be added to the topology 600 forming a loop.
  • a path exists from a0-b4 through cO back to aO.
  • the redundant portal 606 is disabled so that a hierarchical bus bridge topology remains.
  • cyclical net topologies may be allowed.
  • software routines may partially activate the redundant bridge 606 and allow a shortest path routing between nodes. For example, traffic between bus a 605 and bus c 615 may be efficiently routed without introducing deadlocks.
  • FIG 6 is a block diagram of one embodiment for bus bridge components 700.
  • bus bridge components 700 are maintained within each portal in which bus "a" to bus “b” components 702 and bus “b” to bus “a” components 704 are independently maintained.
  • Components 700 also contains shared microprocessor and RAM 706.
  • Asynchronous and isochronous packet transfers may not acquire a bus at the same time. Therefore, asynchronous packets are placed in request queues 708, 720 and response queues 710, 722. The asynchronous packets are selected for transfer at times when isochronous packets are not being transferred. Isochronous packets are received and time stamped 712, 724. Time gates 718, 730 release the isochronous packets 714, 726, together with common isochronous packet (CIP) headers 716, 728, at fixed times. Routing tables select which asynchronous and isochronous packets are accepted and queued for adjacent bus delivery.
  • CIP isochronous packet
  • Topologies may share physical buffer space rather than implementing physical distinct stacks subject to the following: bus "a" to bus “b” and bus “b” to bus “a” queues operate independently, response processing is never blocked by queued requests, and asynchronous subactions and isochronous packets are forwarded independently. Topologies may block a request behind the previously queued response without generating potential deadlocks; however, requests and responses are processed independently.
  • Isochronous routing decisions are made by checking the isochronous packet's channel number. Accepted packets are converted and retransmitted on the adjacent bus with newly assigned channel numbers, speeds, and CIP-header and, when a CIP-header is provided, time-stamp parameters 716, 728 from the CIP-header. CIP-headers may be pre-appended to some isochronous packets to further describe their format and function and desired presentation time. When the packets incur delays while traversing through a bridge, then presentation time must be adjusted to compensate for this delay. CIP headers are defined in ISO/IEC 61883 specification. Isochronous packets received in cycle n are forwarded to the adjacent bus in cycle n+k where k is an implementation dependent constant.
  • Messages may be passed around one bus or pass through a bridge by writing to a standardized message location 732, 734, 736, 738 on a bridge's portal. This allows bus-interconnect topologies to be restored while freezing, or discarding when necessary, previously queued subactions.
  • Distribution of clock-sync information 740, 742 from the primary-bus source is performed by placing calibration information in isochronous-clock pseudo queues before forwarding this information to the clock master on the adjacent portal.
  • clock-sync information flows from the primary bus downward, so that only one clock-sync pseudo queue may be required.
  • each node has two node ID addresses: physical ID address and virtual ID address.
  • a physical node ID has a 3FF 16 valued bus ID; a virtual node ID has smaller bus ID addresses.
  • all nodes are accessed through their physical addresses.
  • the physical address is used to configure the node and the virtual address is normally used thereafter.
  • Directed-asynchronous routing decisions are made by checking the destination ID addresses of pass-through packets. Accepted packets are directly routed to the bridge's opposing port.
  • an asynchronous quarantine is maintained which selectively enables forwarding of a request sub-action based on the local identification of a bus-local requester.
  • a set of legacy bits identifies local nodes which requires specific processing of sourced requests and returning responses.
  • FIG 7 is a block diagram of one embodiment for bus bridge isochronous transfer.
  • isochronous connections involve one talker 802 and one or more multiple listener 804 /controller 806 pairs. Isochronous packets are accepted based on the current channel identification and are retransmitted on the adjacent bus with a new channel ID.
  • a controller 806 establishes an isochronous connection. The isochronous connection enables communication between talker 802 and listener 804. An isochronous connection may be made between a single talker 802 and multiple listeners 804.
  • Isochronous non-overlaid connections proceed as follows: controller 806 sends a message to the final portal 810a in the path towards listener 804. If necessary, portal 810a forwards the message to the first portal on the path between the listener 804 and talker 802 (in this case, portal 808a).
  • Portal 808a acquires isochronous resources from IRM 825 on its bus. IRM may be located within portal 808a or any other node. The message is forwarded towards the talker bus 805, which results in the message being received by portal 808b.
  • Portal 808b acquires the isochronous resources in IRM 825 and updates the oPCR within talker 802. The message is forwarded back toward listener 804, which results in it being received by portal 808a.
  • Portal 808a updates the iPCR on listener 804 so that it listens to the correct channel.
  • Portal 808a forwards a message-complete indicator to controller 806.
  • a disconnect message is sent from controller to portal 810b.
  • Portal 810b forwards the message to portal 808a which updates the iPCR on listener 804 and releases the IRM resources associated with bus 807.
  • the message is forwarded to portal 808b.
  • the oPCR of talker 802 is updated in order to stop transmission.
  • Portal 808b updates the IRM resources associated with bus 805.
  • a completion message is then sent from portal 808b to controller 806.
  • controller 806 sends a disconnect message toward listener 810a, which results in the message being received by portal 810a.
  • Portal 810a forwards the message to portal 808a (the talker side portal of listener 804).
  • Portal 808a forwards the message towards talker 802, which results in the message being received by portal 808b.
  • Portal 808b updates the oPCR of talker 802 in order to stop transmission.
  • Portal 808b accesses IRM 825 to release isochronous channel and bandwidth resources associated with bus 805.
  • Portal 808b forwards the message toward listener 804, which results in the message being received by portal 808a.
  • Portal 808a updates the iPCR of listener 804 in order to stop listener 804 from listening.
  • Portal 808a updates the IRM isochronous resources associated with bus 807.
  • Portal 808a then sends a completion message to controller 806.
  • FIG 8 is a block diagram of another embodiment for a bus bridge isochronous transfer. Referring to Figure 8, a common connection isochronous transfer is illustrated.
  • Talker 902 is connected by controller 906 to listener 904.
  • controller 906 may be on the talker bus 905, listener bus 915, or other bus.
  • Each listener 904 is associated with a controller 906.
  • the controller 906 may be the same or different for the various listeners 904.
  • connection message from controller 906 is processed by portal 912a in which it is found to have the same stream ID. This allows the new listener to listen to the previously established channel.
  • a disconnect message is sent from controller 906 towards listener 904, which results in the message being received by portal 912a.
  • Portal 912a updates the iPCR of listener 904 in order for listener 904 to stop listening.
  • Portal 912a decrements its use count and returns a completion message to controller 906.
  • FIG. 9 is a block diagram of one embodiment for 1394 bus bridge components 1000.
  • isochronous data is provided to and from bus bridge 1000 via buses "a” and “b.”
  • buses “a” and “b” may be 1394 serial buses.
  • Bus bridge 1000 includes a microprocessor 1030 connected to RAM 1040.
  • isochronous buffer 1050 is connected to time gate 1060.
  • Time stamp 1070 is connected to isochronous buffer 1050.
  • isochronous buffer 1055 is connected to time gate 1065.
  • Time stamp 1075 is connected to isochronous buffer 1050.
  • Topologies may share physical buffer space rather than implementing physical distinct stacks subject to the following: bus "a” to bus “b” and bus “b” to bus “a” queues operate independently.
  • Isochronous data packets are received and time stamped 1070, 1075.
  • Time gates 1060, 1065 release the isochronous packets from isochronous buffers 1050, 1055 at fixed times.
  • Isochronous data packets are stored into buffer 1050 during transmission through bus bridge 1000.
  • a delay is introduced in the transmission of isochronous data packets 1000 by storing the isochronous data packets in buffer 1050.
  • the delay effectively provides for the averaging of the bandwidth of the isochronous data packets.
  • Averaging conserves bandwidth on buses "a” and "b.” For example, the volume of isochronous data traffic is sometimes low and sometimes high.
  • the isochronous data traffic has a worst case maximum bandwidth requirement and an average bandwidth requirement that is significantly lower than the maximum bandwidth requirement.
  • isochronous buffer 1055 fills up since it can not transmit all that the data it receives. Meanwhile, isochronous buffer 1050 empties because it transmits one cycle, when only one half of a cycle's data is received. When the isochronous data sets from bus "b" is low, Isochronous buffer 1055 transmits faster than it receives, meanwhile Isochronous buffer 1050 fills to maintain a fixed delay through the bus bridge 1000.
  • isochronous data traffic originates at a talker 802.
  • the talker 802 may send one isochronous data packet.
  • the talker 802 may send two data packets.
  • the additional packet may be sent due to differences in clock rates of a bus and the talker 802.
  • the transmission of an additional packet occurs infrequently - for example, once every thousand cycles.
  • allocating bandwidth for the worst case requires doubling the minimum bandwidth requirement.
  • Allocating bandwidth for the minimum bandwidth required may result in lost data packets.
  • allocating bandwidth for the average bandwidth requirement allows all data packets to be transmitted, by introducing delays.
  • Figure 10 is an illustration of the bandwidth of isochronous data 1110 over time 1120.
  • Figure 10 illustrates an average value and maximum value bandwidth tor the isochronous data packets entering bus bridge 1000.
  • the maximum bandwidth 1130 specifies the maximum number of bytes transferred in an isochronous cycle.
  • the average bandwidth 1140 specifies the average number of bytes transferred in multiple isochronous cycles.
  • Maximum bandwidth time periods 1151, 1154, 1156 and 1160 represent multiple transmission cycles in which the isochronous data is transferred at maximum bandwidth, which temporarily exceeds the bandwidth of the internal data path of the bus bridge .
  • Greater than average time periods 1157 and 1158 represent transmission cycles in which isochronous data packets are transferred at more bandwidth than the average bandwidth 1140, but less than the maximum bandwidth 1130.
  • Less than average time periods 1150, 1152, 1153, 1155, 1159 and 1161 represent transmission cycles that consume less than the average bandwidth 1140.
  • the actual bandwidth may fluctuate from below the average bandwidth 1140 to the maximum bandwidth 1130.
  • interconnects may not be able to operate at the full serial bus rate, due to physical media or other limitations.
  • interconnects may be twisted-pair phone lines or wireless RF and IR transmissions that operate at a slower rate.
  • more isochronous channels can be supported if the isochronous data flows can be buffered and sent at an average bandwidth rate.
  • the bandwidth allocation on these interconnects depends on the number of delays introduced by the bus bridge, since buffer delays are necessary to average the isochronous bandwidths over multiple cycles. Acceptable delay values may be specified and excess delays may be budgeted and divided among multiple bus bridges, allowing bridges to average bandwidths over larger numbers of cycles.
  • FIG 11A is a diagram of one embodiment of a stream of isochronous data packets having a below-average-value bandwidth.
  • Each isochronous date packet 1201 has a fixed size and rate. For example, each packet may be 300 bytes and be transmitted from a talker or another bus bridge at 20 Megabits per second. If the internal data path of bus bridge 1000 is limited to 25 Megabits per second, some of the available bandwidth is still available when transmitting isochronous data at 20 Megabits per second. The extra bandwidth may be expressed as excess delays 1202 between the packets.
  • FIG 11B is a diagram of one embodiment of a stream of isochronous data packets having a below-average bandwidth, as transmitted from a bus bridge.
  • each isochronous data packet 1221 is transmitted at a new data rate greater than its original data rate.
  • the new data rate is equal to the limit of the internal data path of bus bridge 1000.
  • the new data rate may be equal to the average bandwidth of the isochronous data packets, as described above.
  • the bus bridge collects excess delays 1222 for distribution at a later time.
  • FIG 11C is a diagram of one embodiment of a stream of isochronous data packets having a greater than average bandwidth, as transmitted from the bus bridge.
  • Each isochronous data packet 1251 has a fixed size and transmission rate. For example, each packet may be 300 bytes and be transmitted from a talker 802 or from another bus bridge at 30 Megabits per second. If the internal data path of bus bridge 1000 is limited to 25 Megabits per second, all of the available bandwidth is used and 5 Megabits per second is still needed. If the bandwidth is not available, some of the data packets 1231 may be lost.
  • FIG 11D is a diagram of one embodiment of a stream of isochronous data packets having a greater than average bandwidth, as transmitted from a bus bridge.
  • Each isochronous data packet 1281 is transmitted at a new data rate less than its original, greater than average, data rate. The new data rate is attained by inserting delays 1282 between the isochronous data packets 1281. No data packets 1281 are lost, due to the limited bandwidth of the internal data path of the bus bridge 1000 - since the data is first stored in a buffer, thus effectively inserting delays.
  • Figure 12 is a block diagram of one embodiment for bus bridge topology 1300. Talker 1305 is connected via data bus 1310 to bus bridge A 1315. Bus bridge A 1315 is connected via data bus 1320 to bus bridge B 1325.
  • Bus bridge B 1325 is connected via data bus 1330 to bus bridge C.
  • Bus bridge C 1335 is connected via data bus 1340 to listener 1345.
  • talker 1305 sends isochronous data packets having variable bandwidth, such as multimedia data.
  • the isochronous data packets have a maximum bandwidth required by talker 1305.
  • the maximum bandwidth represents the maximum number of data quadlets transmitted by talker 1305 during any given cycle.
  • Delays are distributed throughout bus bridges 1315, 1325, 1335 between taker 1305 and listener 1345.
  • the total number of delays available from bus bridge A 1315, bus bridge B 1325, and bus bridge C 1335 may be accumulated and then redistributed at a later time, based upon each bus bridge's potential benefit from receiving the delays, as described in greater detail below.
  • the total number of delays available is the maximum allowable delay. For example, suppose the total number of delays available is 256 cycles.
  • Bus bridge A 1315 may require a minimum of 4 delays; bus bridge B 1325 may require a minimum of 8 delays; and bus bridge C 1335 may require a minimum of 16 delays.
  • bus bridge A 1315 may benefit three times more than bus bridge B 1325 or bus bridge C 1335 by receiving the delays.
  • Bus bridge B 1325 may benefit four times more than bus bridge A 1315 or bus bridge C 1335 by receiving the delays.
  • bus bridge C 1335 may only benefit one time greater than any bus bridge A 1315 or bus bridge B 1325.
  • bus bridge B 1325 is allocated the greatest number of delays. In one embodiment bus bridge B 1325 may be allocated four eighths or 114 delays of the 228 available delays.
  • Bus bridge A 1315 may be allocated three eighths or 86 delays and bus bridge C 1335 may be allocated the remaining 28 delays. The allocation of excess delays is an excess delay budget.
  • Figure 13 is a block diagram of one embodiment for a 1394 bus bridge topology 1400 for accumulating delay preference information.
  • a connection is established between talker 1420 and listener 1410 by sending messages in the listener 1410-to-talker 1420 direction.
  • Each portal 1440, 1450, and 1460 between listener 1410 and talker 1420 modifies this connection message with delay information.
  • the delay information includes how much of a benefit each portal 1440, 1450, and 1460 would experience if allocated an excess delay, the minimum delay required by each portal 1440, 1450, and 1460 and the amount of additional bandwidth or excess delays each portal 1440, 1450 and 1460, could return allowing the calculation of the total available excess delay cycles.
  • the message is sent from listener controller 1430 to listener portal 1450. Listener 1410 and controller 1430 are connected via bus 1415 to listener portal 1450. The message is tagged with delay information and is sent from listener portal 1450, and arrives at talker portal 1470. Listener portal 1450, talker portal 1470 and neighbor portal 1460 are connected to bus 1425.
  • the message is tagged with the necessary delay information and leaves talker portal 1470 and arrives at neighbor portal 1460. Finally the message is sent from talker portal 1470 to the talker 1420 via bus 1435. Thus, bandwidth information in the form of residual delays have been acquired along with benefit information.
  • the connection message reaches the talker 1420, the message includes the total number of delays required from each intermediate bus bridges.
  • Figure 14 is a block diagram of one embodiment for a 1394 standard bus bridge system for assigning delay allowances of Figure 13.
  • Connection confirmation messages flow from the talker 1505 to listener 1525. Confirmation messages allocate required delay cycles and distribute excess delay cycles.
  • the confirmation message originates at talker portal 1505 and is sent via bus 1510 to listener portal 1515. From listener portal 1515, the confirmation message is passed via bus 1520 to listener 1525 and controller 1535. As described above, the excess delays are distributed based upon the potential benefit to each bus bridge.
  • Figure 15 is a flow diagram of one embodiment for the distribution of delay cycles in a 1394 standard bus bridge system.
  • a stream of data packets are provided from a node to a bus bridge.
  • talker 1420 transmits isochronous data packets to talker portal 1470 via bus 1435.
  • the bus bridge system calculates the average bandwidth of the data packets based upon the maximum and minimum transmission values associated with the talker.
  • the stream of packets is divided into a plurality of groups of a number of packets. In one embodiment, 16 packets may be grouped together. In another embodiment, 8 packets are grouped together, as shown in Figures 11A-11D. If too few packets are grouped together, the results are undesirable, because the next interval will have too many packets. If too many packets are grouped together, the delay will be too long for practical use.
  • excess delays are gathered from groups having below average bandwidths as described in reference to Figure 11B.
  • the excess delays are distributed to groups of packets that have bandwidth greater than the average bandwidth of the stream of data packets, as described in reference to Figure 11D, according to the excess delay budget.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un procédé destiné à effectuer une moyenne des besoins en largeur de bande via un système de pont de bus. Des paquets de données sont présentés à un tampon (1050, 1055), ce tampon contribuant à un budget de dépassement de temps d'attente. Le budget de dépassement de temps d'attente est attribué à un ou à plusieurs ponts de bus (1000). Les paquets de données du tampon (1050, 1055) sont émis selon l'attribution de budget de dépassement de temps d'attente.
PCT/US2000/042497 1999-11-29 2000-11-29 Procede et systeme destines a ameliorer la largeur de bande dans un pont de bus WO2001042877A2 (fr)

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AU45142/01A AU4514201A (en) 1999-11-29 2000-11-29 Method and system for improving bandwidth in a bus bridge

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US16795899P 1999-11-29 1999-11-29
US60/167,958 1999-11-29
US53108100A 2000-03-18 2000-03-18
US09/531,081 2000-03-18

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2828946A1 (fr) * 2001-08-24 2003-02-28 Canon Kk Procede de gestion des delais isochrones associes a des ponts heterogenes dans un heterogene de bus numeriques
EP1289211A1 (fr) * 2001-08-24 2003-03-05 Canon Kabushiki Kaisha Méthode pour établir un flux de données isochrone, en appliquant un délai total isochrone prédéterminé à un ou plusieurs chemins de routage

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623483A (en) * 1995-05-11 1997-04-22 Lucent Technologies Inc. Synchronization system for networked multimedia streams

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623483A (en) * 1995-05-11 1997-04-22 Lucent Technologies Inc. Synchronization system for networked multimedia streams

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2828946A1 (fr) * 2001-08-24 2003-02-28 Canon Kk Procede de gestion des delais isochrones associes a des ponts heterogenes dans un heterogene de bus numeriques
EP1289211A1 (fr) * 2001-08-24 2003-03-05 Canon Kabushiki Kaisha Méthode pour établir un flux de données isochrone, en appliquant un délai total isochrone prédéterminé à un ou plusieurs chemins de routage
US7269137B2 (en) * 2001-08-24 2007-09-11 Canon Kabushiki Kaisha Method for setting up an isochronous data stream connection, with the application of a predetermined, total isochronous delay on one or more routing paths

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AU4514201A (en) 2001-06-18

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