WO2001035587A1 - Commutation de cadre temporel en fonction d'une reference temporelle commune globale - Google Patents

Commutation de cadre temporel en fonction d'une reference temporelle commune globale Download PDF

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Publication number
WO2001035587A1
WO2001035587A1 PCT/US2000/030390 US0030390W WO0135587A1 WO 2001035587 A1 WO2001035587 A1 WO 2001035587A1 US 0030390 W US0030390 W US 0030390W WO 0135587 A1 WO0135587 A1 WO 0135587A1
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WIPO (PCT)
Prior art keywords
time
channels
queues
time frame
switch
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PCT/US2000/030390
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English (en)
Inventor
Yoram Ofek
Mario Baldi
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Synchrodyne Networks, Inc.
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Publication date
Priority claimed from US09/536,948 external-priority patent/US6778536B1/en
Priority claimed from US09/536,708 external-priority patent/US6674754B1/en
Priority claimed from US09/535,831 external-priority patent/US7426206B1/en
Priority claimed from US09/536,811 external-priority patent/US6735199B1/en
Application filed by Synchrodyne Networks, Inc. filed Critical Synchrodyne Networks, Inc.
Priority to AU14626/01A priority Critical patent/AU1462601A/en
Publication of WO2001035587A1 publication Critical patent/WO2001035587A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647—Synchronisation among TDM nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/28—Flow control; Congestion control in relation to timing considerations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/56—Queue scheduling implementing delay-aware scheduling
    • H04L47/564—Attaching a deadline to packets, e.g. earliest due date first
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5603—Access techniques
    • H04L2012/5604—Medium of transmission, e.g. fibre, cable, radio
    • H04L2012/5605—Fibre
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3063—Pipelined operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0007—Construction
    • H04Q2011/0016—Construction using wavelength multiplexing or demultiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0007—Construction
    • H04Q2011/0024—Construction using space switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0039—Electrical control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0045—Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/005—Arbitration and scheduling

Definitions

  • This invention relates generally to a method and apparatus for switching of data packets in a communications network in a timely manner while providing low switching complexity and performance guarantees.
  • Circuit-switching networks which are still the main carrier for real-time traffic, are designed for telephony service and cannot be easily enhanced to support multiple services or carry multimedia traffic. Its almost synchronous byte switching enables circuit-switching networks to transport data streams at constant rates with little delay or jitter. However, since circuit-switching networks allocate resources exclusively for individual connections, they suffer from low utilization under bursty traffic. Moreover, it is difficult to dynamically allocate circuits of widely different capacities, which makes it a challenge to support multimedia traffic. Finally, the almost synchronous byte switching of SONET, which embodies the Synchronous Digital Hierarchy (SDH), requires increasingly more precise clock synchronization as the lines speed increases [John C. Bellamy, "Digital Network Synchronization", IEEE Communications
  • Packet switching networks like IP (Internet Protocol)-based Internet and Intranets handle bursty data more efficiently than circuit switching, due to their statistical multiplexing of the packet streams.
  • IP Internet Protocol
  • Current packet switches and routers operate asynchronously and provide "best effort" service only, in which end-to-end delay and jitter are neither guaranteed nor bounded.
  • statistical variations of traffic intensity often lead to congestion that results in excessive delays and loss of packets, thereby significantly reducing the fidelity of real-time streams at their points of reception.
  • One approach to an optical network that uses synchronization was introduced in the synchronous optical hypergraph [Y. Ofek, "The Topology, Algorithms And Analysis Of A Synchronous Optical Hypergraph Architecture", Ph.D.
  • RISC-like forwarding in which a packet is forwarded, with little if any delay, one hop every time frame in a manner similar to the execution of instructions in a Reduced Instruction Set Computer (RISC) machine.
  • RISC Reduced Instruction Set Computer
  • Yemini et al. disclose a switched network architecture with a time reference.
  • the time reference is used in order to determine the time in which a multiplicity of nodes can transmit simultaneously over one predefined routing tree to one destination. At every time instance the multiplicity of nodes are transmitting to a different single destination node.
  • the patent very briefly mentions the requirement for synchronization among nodes, and does not teach or suggest the means in which it can be provided, or the method in which it can be used.
  • Circuit switches exclusively use time for routing.
  • a time period is divided into smaller time slices, each possibly containing one byte.
  • the absolute position of each time slice within each time period determines where that particular byte is routed.
  • time-based routing is supported with more complex periodicity in timing than circuit switching provides for.
  • the time frames of the present invention delineate a vastly larger time period than the time slices — and even the time cycle — associated with circuit switching.
  • the present invention uses a Common Time Reference (CTR).
  • CTR Common Time Reference
  • the CTR concept is not used in circuit switching (e.g., Tl, T3, and the SONET circuit switching: OC-3, OC-12, OC-48, OC-192, and OC-768).
  • Using or not using CTR has far reaching implications when comparing circuit switching and the current invention. For example, CTR ensures deterministic no slip of time slots or time frames, while enabling deterministic pipeline forwarding of time frames. This is in contrast to circuit switching, where (1) there are time slot slips, and (2) deterministic pipeline forwarding is not possible.
  • Optical data communications include single wavelength standards, wherein a single data stream is transmitted into a series of pulses of light carried by an optical fiber from source to destination. These pulses of light are generally of a uniform wavelength. This single wavelength vastly under-utilizes the capacity of the optical fiber, which may reasonably carry a large number of signals each at a unique wavelength. Due to the nature of propagation of light signals, the optical fiber can carry multiple wavelengths simultaneously with no degradation of signal, no interference, and no crosstalk imposed by the optical fiber.
  • wavelength division multiplexing The process of carrying multiple discrete signals via separate wavelengths of light on the same optical fiber is known in the art as wavelength division multiplexing (WDM).
  • WDM wavelength division multiplexing
  • the present invention permits a novel combination of time-based routing, which is similar but not identical to circuit switching, combined with data packet forwarding as in packet switching.
  • This combination provides for communication of data via a reserved time frame mechanism, where time frames periods permit communications of a very large number of bytes that are scheduled and switched in a time-based fashion within reserved and scheduled time frames, while simultaneously providing for non- scheduled data packet (NSDP) traffic to be switched and routed via the same WDM (wavelength division multiplexing) optical channels.
  • the non-scheduled data packet (NSDP) traffic can be transmitted during empty portions of an otherwise partially reserved and scheduled time frame period.
  • the non-scheduled traffic can also be routed during fully reserved and scheduled time frame periods that have no scheduled traffic presently associated with them.
  • NSDPs can be routed during unreserved time frames.
  • the system can decode and be responsive to the control information in the non- scheduled data packet header.
  • the time frame switching in the present invention provides a novel mode of operation where the connection between an input port and an output port is only changed infrequently, such as on a time frame by time frame basis.
  • This mode of operation is an enabling technology to utilize purely optical switching apparatus, as it circumvents the problems typically associated with long switching cycle time.
  • the present invention enables the utilization of very simple interconnection networks such as Banyan Networks [L. R. Goke, G. J. Lipovski,
  • DBTN Dynamic Burst Transfer Time-Slot-Base Network
  • DTM deploys a structure of frames and small slots (64 bits) to perform resource allocation and circuit switching. Slots are allocated to the end-systems according to a predefined distribution; a distributed algorithm based on the deployment of control slots is used to reallocate unused slots.
  • a fast switching method is disclosed and is tailored to operate responsive to a global common time such that the switching delay from input to output is known in advance and is minimized in a deterministic way. Consequently, such a switch can be employed in the construction of a backbone network using optical fibers with dense wavelength division multiplexing (DWDM).
  • DWDM dense wavelength division multiplexing
  • Such optical fiber links have a transmission rate, with multiple wavelengths, of a few terabits (1012) per second.
  • the design method disclosed in this invention minimizes the time required for the routing decision and switching of every data packet. Consequently, for a given solid state technology, memory access time and memory word width, this method can support the highest speed optical DWDM links. Moreover, the above is independent of the number of switch ports.
  • the switching and data packet forwarding method combines the advantages of both circuit and packet switching. It provides for allocation and exclusive use of transmission capacity for predefined connections and for those connections it guarantees loss free transport with low delay and jitter. When predefined connections do not use their allocated resources, other non-reserved data packets can use them without affecting the performance of the predefined connections.
  • the present invention provides real-time services by synchronous methods that utilize a time reference that is common to the switches and possibly end stations comprising a wide area network.
  • the common time reference can be realized by using UTC (Coordinated Universal Time), which is globally available via, for example, GPS (Global Positioning System -- see, for example: [Peter H. Dana, "Global Positioning System (GPS) Time Dissemination for Real-Time Applications", Real-Time Systems, 12, pp. 9-40, 1997].
  • GPS Global Positioning System
  • UTC is the scientific name for what is commonly called GMT (Greenwich Mean Time), the time at the 0 (root) line of longitude at Greenwich, England. In 1967, an international agreement established the length of a second as the duration of 9,192,631,770 oscillations of the cesium atom. The adoption of the atomic second led to the coordination of clocks around the world and the establishment of UTC in 1972.
  • the Time and Frequency Division of the National Institute of Standards and Technologies (NIST) (see http://www.boulder.nist.gov/timefreq) is responsible for coordinating UTC with the International Bureau of Weights and Measures (BIPM) in Paris.
  • UTC timing is readily available to individual PCs through GPS cards.
  • TrueTime, Inc. (Santa Rosa, California) offers a product under the trade name PCI-SG, which provides precise time, with zero latency, to computers that have PCI extension slots.
  • PCI-SG provides precise time, with zero latency, to computers that have PCI extension slots.
  • NTP Network Time Protocol
  • routing is not performed only based on timing information: routing can be based also on information contained in the header of data packets. For example, Internet routing can be done using IP addresses or using an IP tag/label when MPLS is deployed.
  • One embodiment of the present invention utilizes an alignment feature within an input port for aligning incoming data packets to a time frame boundary prior to entry to a switching fabric. This embodiment has the additional benefit of providing for filtering non-reserved traffic from the data packet stream and routing said traffic to a separate routing controller for best effort transport.
  • the system decodes and is responsive to control information in the non-reserved data packet header.
  • the remainder of the traffic represents reserved traffic that is first aligned to a time frame boundary and then routed through the switch fabric on a subsequent time frame, thus preserving the synchronous operation of the system.
  • the present invention also provides means to reintegrate the filtered non-scheduled traffic into idle portions as may coexist within the scheduled traffic streams.
  • One embodiment of the present invention utilizes a deferred alignment feature, which permits the alignment of incoming data packets to be deferred after preliminary routing and queuing has been performed.
  • This embodiment trades additional storage required for a larger pluraUty of queues for reduced complexity required in the switch fabric.
  • the switch fabric becomes simpler because it is logically divided into a first portion and a second portion, the first portion of which can be relocated upstream of (i.e., before) the alignment buffer queues.
  • the first portion of the switch fabric may be implemented as a simple data path expander to fan out the data to a large pluraUty of queues.
  • the complexity and throughput requirements of each queue are also reduced as the functionaUty is spread out over a wider number of queues.
  • a novel time frame switching fabric control is provided in accordance with an alternate embodiment of the present invention, which stores a predefined sequence of switch fabric configurations, responsive to a high level controUer that coordinates multiple switching systems, and applies the stored predefined sequence of switch fabric configurations on a cycUcal basis having complex periodicity.
  • the application of the stored predefined switch fabric configurations permits the switches of the present invention to relay data over predefined, scheduled, and/or reserved data channels without the computational overhead of computing those schedules ad infinitum within each switch.
  • the computational requirements of determining a smaU incremental change to a switch fabric are much less than having to re-compute the entire switch fabric configuration. Further, the bookkeeping operations associated with the incremental changes are significantly less time-consuming to track than tracking the entire state of the switch fabric as it changes over time.
  • FIG. 1 is a schematic block diagram of one embodiment of a switch connected to a pluraUty of WDM Unks with a switch scheduler in accordance with the present invention
  • FIG. 2 is a timing diagram of a common time reference (CTR) that is aligned to the coordinated universal time (UTC) standard, as utilized by the present invention, wherein the CTR is divided into a plurality of contiguous periodic super-cycles each comprised of at least one contiguous time cycle each comprised of at least one contiguous time frame, wherein the super-cycle is equal to and aligned with the UTC second;
  • FIG. 3 is a schematic block diagram of a virtual pipe and its timing relationship with a common time reference (CTR) as in the present invention;
  • FIG. 4 illustrates the mapping of time frames into and out of a node on a virtual pipe of the present invention
  • FTG. 5A is a schematic block diagram illustrating at least one serial transmitter and at least one serial receiver connected with a WDM link, in accordance with the present invention
  • FIG. 5B is a table iUustrating a 4B/5B encoding scheme for data
  • FIG. 5C is a table illustrating a 4B/5B encoding scheme for control signals
  • FIG. 6A is a map of a data packet with a header, as utiUzed in accordance with the present invention.
  • FIG. 6B illustrates a mapping of additional details of the encoding of the data packet of FIG. 6A
  • FIG. 7 illustrates a wave division multiplexing (WDM) switch that is connected to optical link with multiple wavelengths, wherein each of the wavelengths constitutes a communication channel that has a time division multiplexing (TDM) structure with time frames, time cycles and super-cycles in accordance with the present invention
  • FIG. 8 illustrates multi-dimensional mapping with four input variables as an example: p-in - input port #, w-in - input wavelength (color), t-in - time frame # in (within a time cycle), c-in - time cycle # in (within a super-cycle); and four output variables: p-out - output port #, w-out - output wavelength (color), t-out - time frame # out (within a time cycle), c-out - time cycle # out (within a super-cycle) in accordance with the present invention;
  • FIG. 9 illustrates an example of mapping time frames, received over the same wavelength received through multiple input ports, to one wavelength (channels) on the same output port, in accordance with the present invention
  • FIG. 10 illustrates an example of multi-dimensional mapping for all time-driven optical switching with no wavelength conversion, the optical switching being responsive to the common time reference in accordance with the present invention
  • FIG. 11 A is a schematic diagram of an all optical switch with at least one optical switching fabric, which switches a plurality of optical wavelengths, wherein the optical switching matrix (as in FIG. 10, for example) changes every time frame;
  • FIG. 1 IB is a timing diagram of the all optical switch operation with two phases: one in which the actual switching is performed and the other in which the current switching matrix is being replaced by a new switching matrix;
  • FIG. 12 iUustrates an example of pipeline forwarding of time frames, in accordance with the present invention
  • FIG. 13A is a functional description of a switch with 16 ports - each with 16- wavelength division multiplexing optical channels, such that it is possible to transfer: From (any time frame (TF) of any Channel at any Input) To (a predefined time frame (TF) of any Channel at any Output);
  • FIG. 13B is a timing diagram of a switching operation that is responsive to the common time reference 002 with two pipeline forwarding phases;
  • FIG. 14 is a functional block diagram illustrating a wavelength division multiplexing input port with a pluraUty of serial receivers, serial-to-paraUel conversion and a plurality of aUgnment subsystems;
  • FIG. 15 is a functional block diagram of the alignment subsystem that operates responsive to CTR and the serial link relative timing
  • FIG. 16 is a timing diagram of the aUgnment subsystem operation responsive to CTR and the serial link relative timing
  • FIG. 17 is a block diagram and schematic of the structure of a switch and a fabric controller with memory for a plurality of switching matrices
  • FIG. 18 is iUustrates a wavelength division multiplexing output port
  • FIG. 19 is a functional block diagram of a wavelength division multiplexing input port with data packet filters for detecting non-scheduled data packets, which are forwarded to a routing module;
  • FIG. 20 is a block diagram of a routing module
  • FIG. 21 is a block diagram of a data packet filter connected to an alignment subsystem that is connected to a switch fabric and a fabric controller;
  • FIG. 22 is a block diagram of a switch design with a 16-to-256 expander, wherein the expander output lines are connected to alignment subsystems;
  • FIG. 23 is a more detailed description of the 16-to-256 expander of FIG. 22;
  • FIG. 24 is a functional block diagram of the connection from the alignment subsystems to an output port via a plurality of selectors
  • FIG. 25 is a functional block diagram of an SVP interface with per time frame queues
  • FIG. 26A is a functional block diagram of an SVP interface with per SVP queues
  • FIG. 26B is a functional block diagram of multiple SVP interfaces to a multiprotocol time driven SVP switch
  • FIG. 27 is a system block diagram of a network with a plurality of multiprotocol time driven SVP switches that are connected to SVP interfaces and other vendors' optical cross connects (OXCs), showing channels, interfaces, and so forth;
  • OXCs optical cross connects
  • FIG. 28 is a high level diagram of communications layering and a description of a two layer system, wherein the low/inside layer is dense wavelength division multiplexing (DWDM) and the outer layer is IP/MPLS;
  • DWDM dense wavelength division multiplexing
  • IP/MPLS IP/MPLS
  • FIG. 29 is a diagram of an 8-by-8 multi-stage interconnection switch that is constructed of 2-by-2 switching elements
  • FIG. 30A is a comparison table of a multi-stage interconnection switch with a crossbar switch.
  • FIG. 30B is a block diagram of a 256-by-256 multi-stage interconnection switch that is constructed of 4-by-4 switching elements.
  • the present invention relates to a system and method for switching and forwarding data packets over a packet switching network with optical WDM (wavelength division multiplexing) Unks.
  • the switches of the network maintain a common time reference (CTR), which is obtained either from an external source (such as GPS ⁇ Global Positioning System) or is generated and distributed internaUy.
  • CTR common time reference
  • the common time reference is used to define time intervals, which include super-cycles, time cycles, time frames, time slots, and other kinds of time intervals.
  • the time intervals are arranged both in simple periodicity and complex periodicity (like seconds and minutes of a clock).
  • a packet that arrives to an input port of a switch is switched to an output port based on either specific routing information in the packet's header (e.g., IPv4 destination address in the Internet, VCI/VPI labels in ATM, MPLS-multi-protocol label switching-labels) or arrival time information.
  • IPv4 destination address in the Internet e.g., IPv4 destination address in the Internet, VCI/VPI labels in ATM, MPLS-multi-protocol label switching-labels
  • arrival time information e.g., IPv4 destination address in the Internet, VCI/VPI labels in ATM, MPLS-multi-protocol label switching-labels
  • Each switch along a route from a source to a destination forwards packets in periodic time intervals that are predefined using the common time reference.
  • a time interval duration can be longer than the time duration required for communicating a data packet, in which case the exact position of a data packet in the time interval is not predetermined.
  • a data packet is defined to be located within the time interval which contains the communication of the first bit of the packet, even if the length of the packet is sufficiently long to require multiple time intervals to communicate the entire data packet.
  • Data packets that are forwarded inside the network over the same route and in the same periodic time intervals constitute a virtual pipe and share the same pipe-ID or PID.
  • a pipe-ID or PID can be either explicit, such as a tag or a label that is generated inside the network, or implicit such as a group of IP addresses or the combination of fields in the data packet header.
  • a virtual pipe can be used to transport data packets from multiple sources and to multiple destinations. The time interval in which a switch forwards a specific packet is determined by the time it reaches the switch, the current - l i vable of the common time reference, and possibly the packet's pipe-ID.
  • a virtual pipe can provide deterministic quatity of service guarantees.
  • congestion-free packet switching is provided for pipe-IDs in which capacity in their corresponding forwarding Unks and time intervals is reserved in advance. Furthermore, packets that are transferred over a virtual pipe reach their destination in predefined time intervals, which guarantees that the delay jitter is smaller than or equal to one time interval.
  • Packets that are forwarded from one source to multiple destinations share the same pipe-ID and the links and time intervals on which they are forwarded comprise a virtual tree. This facilitates congestion-free forwarding from one input port to multiple output ports, and consequently, from one source to a multiplicity of destinations. Packets that are destined to multiple destinations reach all of their destinations in predefined time intervals and with delay jitter that is no larger than one time interval.
  • a system for managing data transfer of data packets from a source to a destination.
  • the transfer of the data packets is provided during a predefined time interval, comprised of a plurality of predefined time frames.
  • the system is further comprised of a pluraUty of switches.
  • a virtual pipe is comprised of at least two of the switches interconnected via communication links in a path.
  • a common time reference signal is coupled to each of the switches, and a time assignment controller assigns selected predefined time frames for transfer into and out from each of the respective switches responsive to the common time reference signal.
  • Each communications tink may use a different time frame duration generated from the common time reference signal.
  • first predefined time frame and a first predefined wavelength within which a respective data packet is transferred into the respective switch there is a second predefined time frame and a second predefined wavelength within which the respective data packet is forwarded out of the respective switch, wherein the first and second predefined time frames may have different durations.
  • the time assignment provides consistent fixed time intervals between the input to and output from the virtual pipe.
  • each of the switches is comprised of one or a plurality of uniquely addressable input and output ports.
  • a routing controller maps each of the data packets that arrives at each one of the input ports of the respective switch to a respective one or more of the output ports of the respective switch.
  • each input port and each output port is comprised of one or a plurality of uniquely addressable optical WDM (wavelength division multiplexing) channels.
  • the virtual pipes comprised of at least one of the switches interconnected via communication links in a path.
  • the communication link is a connection between two adjacent switches; and each of the communications links can be used simultaneously by at least two of the virtual pipes. Multiple data packets can be transferred utilizing at least two of the virtual pipes.
  • a predefined interval is comprised of a fixed number of contiguous time frames comprising a time cycle.
  • Data packets that are forwarded over a given virtual pipe are forwarded from an output port within a predefined subset of time frames in each time cycle.
  • the number of data packets that can be forwarded in each of the predefined subset of time frames for a given virtual pipe is also predefined.
  • the time frames associated with a particular one of the switches within the virtual pipe are associated with the same switch for all the time cycles, and are also associated with one of input into or output from the particular respective switch.
  • a fixed number of contiguous time cycles comprise a super-cycle, which is periodic.
  • Data packets that are forwarded over a given virtual pipe are forwarded from an output port within a predefined subset of time frames in each super-cycle.
  • the number of data packets that can be forwarded in each of the predefined subset of time frames within a super-cycle for a given virtual pipe is also predefined.
  • the common time reference signal is devised from the GPS (Global Positioning System), and is in accordance with the UTC (Coordinated Universal Time) standard.
  • the UTC time signal does not have to be received directly from GPS.
  • Such signal can be received by using various means, as long as the delay or time uncertainty associated with that UTC time signal docs not exceed half a time frame.
  • the super-cycle duration is equal to one second as measured using the UTC (Coordinated Universal Time) standard. In an alternate embodiment the super-cycle duration spans multiple UTC seconds. In another alternate embodiment the super-cycle duration is a fraction of a UTC second. In a preferred embodiment, the super-cycle duration is a small integer number of UTC seconds.
  • Data packets can be Internet Protocol (IP) data packets, multi-protocol label switching (MPLS) data packets, Frame Relay frames, fiber channel data units, or asynchronous transfer mode (ATM) ceUs, and can be forwarded over the same virtual pipe having an associated pipe identification (PID).
  • IP Internet Protocol
  • MPLS multi-protocol label switching
  • ATM asynchronous transfer mode
  • the PID can be expUcitiy contained in a field of the packet header, or implicitly given by an Internet protocol (IP) address, Internet protocol group multicast address, a combination of values in the IP and/or transport control protocol (TCP) and/or user datagram protocol (UDP) header and/or payload, an MPLS label, an asynchronous transfer mode (ATM) virtual circuit identifier (VCI), and a virtual path identifier (VPI), or used in combination as VCI/VPI.
  • IP Internet protocol
  • TCP transport control protocol
  • UDP user datagram protocol
  • MPLS label an MPLS label
  • ATM asynchronous transfer mode virtual circuit identifier
  • VPNI virtual path identifier
  • the routing controller determines two possible associations of an incoming data packet: (i) the output port, and (ii) the time of arrival (ToA).
  • the ToA is then used by the scheduUng controller for determining when a data packet should be forwarded by the select buffer controller to the next switch in the virtual pipe.
  • the routing controller utilizes at least one of Pipe-ID, Internet protocol version 4 (IPv4), Internet protocol version 6 (IPv6) addresses, Internet protocol group multicast address, Internet MPLS (multi protocol label swapping or tag switching) labels, ATM virtual circuit identifier and virtual path identifier (VCI/VPI), and IEEE 802 MAC (media access control) addresses, for mapping from an input port to an output port.
  • IPv4 Internet protocol version 4
  • IPv6 Internet protocol version 6
  • VCI/VPI virtual path identifier
  • IEEE 802 MAC media access control
  • the mapping from an input port to an output port can also be determined, solely or in conjunction with the foregoing information, according to the ToA of the data packet.
  • Each of the data packets is comprised of a header, which can include an associated time stamp.
  • For each of the mappings by the routing controller there is an associated mapping by the scheduling controUer, of each of the data packets between the respective associated time stamp and an associated forwarding time, which is associated with one of the predefined time frames.
  • the time stamp can record the time at which a packet was created by its application.
  • the time stamp is generated by the Internet real-time protocol (RTP) entity within a predefined one of the sources or switches.
  • the time stamp can be used by a scheduling controUer in order to determine the forwarding time of a data packet from an output port.
  • Each of the data packets originates from a source or an end station, and the time stamp is generated at the respective end station for inclusion in the respective originated data packet.
  • Such generation of a time stamp can be derived from UTC either by receiving it directly from GPS or by using the Internet's Network Time Protocol (NTP).
  • NTP Network Time Protocol
  • the time stamp can alternatively be generated at the sub-network boundary, which is the point at which the data enters the synchronous virtual pipe.
  • a system for transferring data (packets) across a data network whUe maintaining for reserved data traffic constant bounded jitter (or delay uncertainty) and no congestion-induced loss of data (packets).
  • data packets
  • whUe maintaining for reserved data traffic constant bounded jitter (or delay uncertainty) and no congestion-induced loss of data (packets).
  • Such properties are essential for many multimedia applications, such as, telephony and video teleconferencing.
  • one or a plurality of virtual pipes 25 are provided, as shown in FIG. 3, over a data network with general topology. Such data network can span the globe.
  • Each virtual pipe 25 is constructed over one or more switches 10, shown in FIG. 3, which are interconnected via communication links 41 in a path.
  • FIG. 3 is a schematic illustration of a virtual pipe and its timing relationship with a common time reference (CTR), wherein delay is determined by the number of time frames between the forward time out at Node A and the forward time out at Node D.
  • CTR common time reference
  • Each virtual pipe 25 is constructed over one or more switches 10 which are interconnected via communication Unks 41 in a path.
  • FIG. 3 illustrates a virtual pipe 25 from the output port 40 of switch A, through switches B and C.
  • the illustrated virtual pipe ends at the output port 40 of node D.
  • the virtual pipe 25 transfers data packets from at least one source to at least one destination.
  • the data packet transfers over the virtual pipe 25 via switches 10 are designed to occur during a pluraUty of predefined time intervals, wherein each of the predefined time intervals is comprised of a plurality of predefined time frames.
  • the timely transfers of data packets are achieved by coupling a common time reference signal (not shown) to each of the switches 10.
  • An output port 40 is connected to a next input port 30 via a communication link 41, as shown in FIG. 3.
  • the communication link can be realized using various technologies compatible with the present invention including fiber optic conduits with WDM (wavelength division multiplexing) channels, copper and other wired conductors, and wireless communication Unks — including but not limited to, for example, radio frequency (RF) between two ground stations, a ground station and a satellite, and between two satellites orbiting the earth, microwave links, infrared (TR) links, optical communications lasers.
  • RF radio frequency
  • TR infrared
  • the communication link does not have to be a serial communication link.
  • a paraUel communication link can be used ⁇ such a parallel Unk can simultaneously carry multiple data bits, associated clock signals, and associated control signals.
  • FIG. 1 is a schematic block diagram of one embodiment of a time driven SVP switch with a switch scheduler in accordance with the present invention.
  • the SVP switch 10 comprises a common time reference means 20, at least one input port 30, at least one output port 40, a switching fabric 50 with a fabric controller 52, and a switch scheduler 60.
  • the common time reference means 20 is a GPS receiver which receives a source of common time reference 001 (e.g., UTC via GPS) via an antenna as iUustrated.
  • the common time reference means 20 provides a common time reference signal 002 to all input ports 30, all output ports 40, and the switch scheduler 60.
  • GPS time receivers are avaUable from a variety of manufacturers, such as, TrueTime, Inc. (Santa Rosa, CA). With such equipment, it is possible to maintain a local clock with accuracy of ⁇ 1 microsecond from the UTC (Coordinated Universal Time) standard everywhere around the globe.
  • Each respective one of the input ports 30 is coupled to the switch scheduler 60 and to the switching fabric 50 with a fabric controller 52.
  • Each respective one of the output ports 40 is coupled to the switch scheduler 60 and to the switching fabric 50.
  • the fabric controller 52 is additionally coupled to the switch scheduler 60.
  • the switch scheduler 60 supplies a slot clock signal 65 to each respective one of the input ports 30 and each respective one of the output ports 40.
  • the slot clock is an indication of time slots within a single time frame.
  • the switch scheduler 60 also suppUes input schedule messages 62 and input reject messages 63 to each respective one of the input ports 30.
  • Each respective one of the input ports 30 supplies input request messages 61 to the switch scheduler 60.
  • the switch scheduler 60 also supplies a fabric schedule 64 to the fabric controller 52.
  • the switch scheduler 60 is constructed of a central processing unit (CPU), a random access memory (RAM) for storing messages, schedules, parameters, and responses, a read only memory (ROM) for storing the switch scheduler processing program and a table with operation parameters.
  • CPU central processing unit
  • RAM random access memory
  • ROM read only memory
  • FIG. 2 is an illustration of a common time reference (CTR) that is aligned to UTC.
  • CTR common time reference
  • Consecutive time frames are grouped into time cycles. As shown in the example Ulustrated in FIG. 2, there are 100 time frames in each time cycle. For illustration purposes, the time frames within a time cycle are numbered 1 through 100. Consecutive time cycles are grouped together into super-cycles, and as shown in
  • FIG. 2 there are 80 time cycles in each super-cycle. For Ulustration purposes, time cycles within a super-cycle are numbered 0 through 79. Super-cycles 0 and m are shown in FIG. 2.
  • FIG. 2 is illustrative of the relationship of time frames, time cycles, and super- cycles; in alternate embodiments, the number of time frames within a time cycle may be different than 100, and the number of time cycles within a super-cycle may be different than 80.
  • FIG. 2 iUustrates how the common time reference signal can be atigned with the UTC (Coordinated Universal Time) standard.
  • the duration of every super-cycle is exactly one second as measured by the UTC standard.
  • the beginning of each super-cycle coincides with the beginning of a UTC second. Consequently, when leap seconds are inserted or deleted for UTC corrections (due to changes in the earth rotation period), the cycle and super-cycle periodic scheduUng will not be affected.
  • the time frames, time cycles, and super-cycles are associated in the same manner with aU respective switches within the virtual pipe at all times.
  • the super-cycle duration is equal to one second as measured using the UTC (Coordinated Universal Time) standard.
  • the super-cycle duration spans multiple UTC seconds.
  • the super-cycle duration is a fraction of a UTC second.
  • the super-cycle duration is a smaU integer number of UTC seconds.
  • a time frame may be further divided into time slots in the preferred embodiment, not iUustrated in FIG. 2.
  • Pipeline forwarding relates to data packets being forwarded across a virtual pipe 25 (see FIG. 3) with a predefined delay in every stage (either across a communication link 41 or across an SVP switch 10 from input port 30 to output port 40). Data packets enter a virtual pipe 25 from one or more sources and are forwarded to one or more destinations.
  • the SVP switch 10 structure as shown in FIG. 3, can also be referred to as a pipeline switch, since it enables a network comprised of such switches to operate as a large distributed pipeline architecture, as it is commonly found inside digital systems and computer architectures.
  • a data packet is received by one of the input ports 30 of switch A at time frame 1, and is forwarded along this virtual pipe 25 in the following manner: (i) the data packet 41A is forwarded from the output port 40 of switch A at time frame 2 of time cycle 1, (ii) the data packet 41B is forwarded from the output port 40 of switch B, after 18 time frames, at time frame 10 of time cycle 2, (iii) the data packet 41C is forwarded from the output port 40 of switch C, after 42 time frames, at time frame 2 of time cycle 7, and (iv) the data packet 41D is forwarded from the output port 40 of switch D, after 19 time frames, at time frame 1 of time cycle 9.
  • the data packets that exit the virtual pipe 25 i.e., forwarded out of the output port 40 of switch D
  • the data packets that exit the virtual pipe 25 can be forwarded simultaneously to multiple destinations, (i.e., multi-cast (one-to-many) data packet forwarding).
  • the communication link 41 between two adjacent ones of the switches 10 can be used simultaneously by at least two of the virtual pipes.
  • a plurality of virtual pipes can multiplex (i.e., mix their traffic) over the same communication links.
  • a pluraUty of virtual pipes can multiplex (i.e., mix their traffic) during the same time frames and in an arbitrary manner.
  • the same time frame can be used by multiple data packets from one or more virtual pipes.
  • the SVP switch 10 structure can also be referred to as a pipeline switch, since it enables a network comprised of such switches to operate as a large distributed pipeline architecture, as it is commonly found inside digital systems and computer architectures.
  • FIG. 4 iUustrates the mapping of the time frames into and out of a node on a virtual pipe, wherein the mapping repeats itself in every time cycle illustrating the time in, which is the time of arrival (ToA), versus the time out, which is the forwarding time out of the output port.
  • FIG. 4 shows the periodic scheduling and forwarding timing of a switch of a virtual pipe wherein there are a predefined subset of time frames (/, 75, and 80) of every time cycle, during which data packets are transferred into that switch, and wherein for that virtual pipe there are a predefined subset of time frames (i+3, 1, and 3) of every time cycle, during which the data packets are transferred out of that switch.
  • a first data packet 5a arriving at the input port of the switch at time frame / is forwarded out of the output port of the switch at time frame +3.
  • the data packet is forwarded out of the output port at a later time frame within the same time cycle in which it arrived.
  • the delay in transiting the switch (dts) determines a lower bound on the value ( +dts). In the illustrated example, dts must be less than or equal to 3 time frames.
  • a second data packet 5b arriving at the input port of the switch at time frame 75 is forwarded out of the output port of the switch at time frame 1 within the next time cycle.
  • the data packet is forwarded out of the output port at a earher numbered time frame but within the next time cycle from which it arrived. Note that data packets in transit may cross time cycle boundaries.
  • each of the three data packets has 125 bytes (i.e. 1000 bits), and there are 80 time frames of 125 microseconds in each time cycle (i.e. a time cycle duration of 10 milliseconds), then the bandwidth aUocated to this virtual pipe is 300,000 bits per second.
  • the bandwidth or capacity allocated for a virtual pipe is computed by dividing the number of bits transferred during each of the time cycles by the time cycle duration.
  • the bandwidth allocated to a virtual pipe is computed by dividing the number of bits transferred during each of the super-cycles by the super-cycle duration.
  • FIG. 5A is an illustration of a serial transmitter and a serial receiver.
  • FIG. 5B is a table illustrating the 4B/5B encoding scheme for data
  • FIG. 5C is a table Ulustrating the 4B/5B encoding scheme for control signals.
  • a serial transmitter 49 and serial receiver 31 are illustrated as coupled to each tink 41.
  • a variety of encoding schemes can be used for a serial line tink 41 in the context of this invention, such as, SONET/SDH, 8B/10B Fiber Channel, and 4B/5B Fiber Distributed Data Interface (FDDI).
  • FDDI Fiber Distributed Data Interface
  • the serial transmitter/receiver (49 and 31) sends/receives control words for a variety of in-band control purposes, mostly unrelated to the present invention description.
  • time frame dehmiter TFD
  • position delimiter PD
  • TFD time frame dehmiter
  • PD position delimiter
  • the TFD marks the boundary between two successive time frames and is sent by a serial transmitter 49 when a CTR 002 clock tick occurs in a way that is described hereafter as part of the output port operation.
  • the PD is used to distinguish between multiple positions within a time frame and is sent by a serial transmitter 49 upon receipt of a position delimiter input 47B.
  • the serial transmitter 49 and receiver 31 are comprised of AM7968 and AM7969 chip sets, respectively, both manufactured by AND Corporation.
  • FIG. 5B Ulustrates an encoding table from 4-bit data to 5-bit serial codeword.
  • the 4B/5B is a redundant encoding scheme, which means that there are more codeword than data words. Consequently, some of the unused or redundant serial codeword can be used to convey control information.
  • FIG. 5C is a table with 15 possible encoded control codewords, which can be used for transferring the time frame delimiter (TFD) over a serial Unk.
  • the TFD transfer is completely transparent to the data transfer, and therefore, it can be sent in the middle of the data packet transmission in a non-destructive manner.
  • the time frame detimiter cannot be embedded as redundant serial codeword, since SONET/SDH serial encoding is based on scrambling with no redundancy. Consequently, the TFD is implemented using the SONET/SDH frame control fields: transport overhead (TOH) and path overhead (POH).
  • TOH transport overhead
  • POH path overhead
  • FIG. 6A is an Ulustration of a data packet structure with a header that includes a time stamp, two priority bits, a multi-cast bit, and an attached time of arrival (ToA), port number, and Unk type.
  • the packet header together with the attached time of arrival (ToA), port number, and Unk type constitute a scheduUng header.
  • the scheduling header is used for scheduling the data packet switching from input to output.
  • FIG. 6B is additional detail about the encoding of the priority and multi-cast bits of FIG. 6A.
  • an incoming data packet consists of a header and a payload portion.
  • the header includes, as shown in FIGS. 6 A and 6B, a time stamp value 35TS, a multi-cast indication 35M, a priority indication 35P, and a virtual PID indication 35C.
  • the priority indication 35P may include encoding of a high and a low priority.
  • multiple levels of priority are encoded by priority indication 35P.
  • the multiple levels of priority include Constant Bit Rate (CBR) priority, Variable Bit Rate (VBR) priority, "best-effort" (BE) priority, and Rescheduled priority.
  • CBR Constant Bit Rate
  • VBR Variable Bit Rate
  • BE best-effort priority
  • Rescheduled priority Rescheduled priority.
  • the multi-cast indication 35M may include encoding indicating one destination or a plurality of destinations. In the case of a plurality of destinations there can be one or more PIDs.
  • the data packet header in FIG. 6A further comprises of a 2-bit, L1/L2, field 35L, which provides information regarding this data packet location within a stream of data packets that are part of the same SVP or the same call connection.
  • Ll/L2 00 - first data packet location in the flow (SVP) - compute a schedule
  • Ll/L2 01 - middle data packet location in the flow - same as the previous schedule
  • Ll/L2 10 - last data packet location in the flow (SVP) - same as the previous schedule
  • Ll/L2 l 1 - decode this data packet address and schedule it regardless of its location.
  • the main motivation for having the L1/L2 bits in field 35L is for minimizing the scheduling delay.
  • a data packet in the middle of a flow of the same SVP/call/connection will use the same schedule to get across the switching fabric as a predecessor data packet in this flow. This implies that only decoding of the PID 35C is needed in order to determine to which output port the incoming data packet should be switched to.
  • the ToA 35T and time stamp 35TS can have a plurality of numerical formats.
  • One example is the format of the Network Time Protocol [D. MiUs, Network Time Protocol (version 3) IETF RFC 1305] which is in seconds relative to Oh UTC on 1
  • the full resolution NTP timestamp is a 64- bit unsigned fixed point number with the integer part in the first 32 bits and the fractional part in the last 32 bits. In some fields where a more compact representation is appropriate, only the middle 32 bits are used; that is, the low 16 bits of the integer part and the high 16 bits of the fractional part. The high 16 bits of the integer part must be determined independently.
  • the incoming data packet can have various formats, such as but not limited to Internet protocol version 4 (IPv4), Internet protocol version 6 (IPv6), and asynchronous transfer mode (ATM) cells.
  • IPv4 Internet protocol version 4
  • IPv6 Internet protocol version 6
  • ATM asynchronous transfer mode
  • the data packet's PID 35C can be determined by but is not timited to one of the following: an Internet protocol (IP) address, an asynchronous transfer mode (ATM), virtual circuit identifier, a virtual path identifier (VCI/VPI),
  • IPv6 Internet protocol version 6
  • MPLS Internet Multi Protocol Label Swapping
  • IEEE 802 MAC media access control
  • FIG. 7 depicts two channels: G or green channel that is connected to 41-1, and R or red channel that is connected to 41-k.
  • G or green channel that is connected to 41-1
  • R or red channel that is connected to 41-k. The time over each channel is partitioned in accordance to the common time reference
  • Time frames are grouped into time cycles (in FIG. 7, time frames G1-G4 are grouped into a time cycle, and time frames R1-R4 are grouped into a time cycle on another channel), and time cycles are grouped into super-cycles, wherein a super-cycle can be aligned with UTC (Coordinated Universal Time), which is globaUy avaUable via, for example, GPS (Global Positioning System).
  • UTC Coordinatd Universal Time
  • GPS Global Positioning System
  • the super-cycle duration is equal to one second as measured using the UTC (Coordinated Universal Time) standard.
  • the super- cycle duration spans multiple UTC seconds or is a fraction of one UTC second.
  • time frame duration and time cycle duration can be different on different wavelength channels.
  • a novel time frame switching fabric control is provided by the present invention which stores a predefined sequence of switch fabric configurations, responsive to a high level controller that coordinates multiple switching systems, and applies the stored predefined sequence of switch fabric configurations on a cyclical basis having complex periodicity.
  • the application of the stored predefined switch fabric configurations permits the switches of the present invention to relay data over predefined, scheduled, and/or reserved data channels without the computational overhead of computing those schedules ad infinitum within each switch. This frees the switch computation unit to operate relatively autonomously to handle transient requests for local traffic reservation requests without changing the predefined switch fabric configurations at large, wherein the switch computation unit provides for finding routes for such transient requests by determining how to utilize underused switch bandwidth (i.e., "holes" in the predefined usage).
  • FIG. 12 shows an example of time frame (TF) switching and forwarding through a sequence of the switches: Switch A, Switch B, and Switch C.
  • TF time frame
  • time frame switching is extremely useful in reducing the switching complexity of communications systems with a very high transmission rate (e.g., OC-48, OC-192, OC-768) and/or a plurality of wavelengths (i.e., WDM channels), as shown in FIG. 7.
  • a very high transmission rate e.g., OC-48, OC-192, OC-768
  • WDM channels i.e., WDM channels
  • FIG. 7 there are two channels: G or green channel that is connected to 41-1 and R or red channel that is connected to 41-k.
  • the time over each channel is partition in accordance to the common time reference (CTR) - as was depicted in FIG. 2.
  • CTR common time reference
  • time frames are grouped into time cycles (in FIG. 7, time frames G1-G4 are grouped into a time cycle, and time frames R1-R4 are grouped into a time cycle on another channel), and time cycles are grouped into super- cycles.
  • the switching from input to output maps input time frames to output time frames in an arbitrary manner.
  • the following mapping is performed for the green channel: Gl to the position of R3, G2 to the position of G4, G3 to the position of Rl, G4 to the position of G2, and the following mapping is performed for the red channel: Rl to the position of G3, R2 to the position of R4, R3 to the position of Gl, R4 to the position of R2.
  • FIG. 8 depicts a general mapping format for time frame switching and forwarding over a pluraUty of WDM channels: (p-in, w-in, t-in, c-in) TO (p-out, w-out, t- switch, c-switch, t-out, c-out), wherein p-in - input port #, w-in - input wavelength (color), t-in - time frame # in (within a time cycle), c-in - time cycle # in (within a super-cycle) and p-out - output port #, w-out - output wavelength (color), t-switch - time frame # switch (within a time cycle), c-switch - time cycle # switch (within a super-cycle), t-out - time frame # out (within a time cycle), c-out - time cycle # out (within a super-cycle).
  • the table 2700 in FIG. 8 shows time frame switching for a given p-in (input port).
  • the rows in table 2700 represent two WDM channels (red and green) with four time frames in every time cycles, which are corresponding to the description in FIG. 7.
  • the columns in table 2700 represent 1 time cycles of one super-cycle.
  • Each entry in table 2700 represents: p-out or the output port, w-out or the output wavelength, t-switch or the time frame switching time from input to output, c-switch or the cycle time switching time from input to output, t-out or the time frame out of the out put port, c-out or the time cycle out of the output port.
  • FIG. 9 depicts the basic WDM time frame switching property: The source of any wavelength (Wl, W2, and W3) in any time frame can come from any input port, 1
  • Wl, W2 and W3 with the following time frame mapping: Wl from input i, Wl from input j, Wl from input k, W2 from input 1, W2 from input m, W2 from input n, W3 from input o, W3 from input p, W3 from input q.
  • the outgoing content (i.e., data packets) in every time frame on any WDM channel can be the incoming content of any time frame on any WDM channel.
  • the delay between the outgoing time frame and the incoming time frame is a predefined number of 1, 2, 3 and so on time frames.
  • this input to output delay is not longer than 3-4 time frames.
  • each time frame can contain a pluraUty of format types that are scheduled and transferred wftile maintaining individual identity, wherein the possible format types are, but not limited to: a fixed size ATM ceU, a variable sized IP data packet, a frame relay data packet, a fiber channel data packet.
  • Method 2 as in the previous method, Method 1 , the content of the whole time frame is switched in the same way - namely, aU the data packets in the time frame are switched to the same output port. Consequently, there is no need to use time slots.
  • Method 2 the switching is done optically by an aU-optical time frame switch, as shown in FIGS. 10 and 11. The all optical switching is stiU being controlled by digital electronic circuitry.
  • the control function of the all-optical time frame switch operates by the following principle (FIG. 10): In every time frame within a time cycle and within a super-cycle, an input wavelength is switched to a selected defined subset of the out-going optical channels performing the foUowing mapping:
  • the above mapping is defined by a switching matrix.
  • the switching matrix is defined by a plurality of tables 3000 for w-in and p-in in FIG. 10.
  • the rows in this table 3000 are for each of the 4 time frames in a time cycle and the columns are for each of the 4 time cycles in a super-cycle.
  • the table 3000 has an entry for each time frame of a super-cycle.
  • Each entry in the table 3000 defines p-out, w-out, t- out, and c-out.
  • FIG. 12 shows an example of time frame (TF) switching and forwarding through a sequence of the switches: Switch A, Switch B, and Switch C.
  • TF time frame
  • Switch B switches the content of a TF that was forwarded from Switch A at time frame 2 will reach Switch B at time frame 5, then switched to the output port at time frame 6, then forwarded at time frame 7 and wiU reach Switch C at time frame 9.
  • FIG. 11 A shows an example of an optical switch block diagram.
  • the incoming optical WDM signal gets through an optical demultiplexer 3120, which separates the multiplexed incoming optical signal, 41-1 to 41-3, into three separate optical signals, la, lb, and lc, which are coupled with the all optical switching fabric 3100.
  • the optical demultiplexer may consist of an optical-to-electronic conversion together with an electronic-to-optical conversion in order to restore the optical signal into its original quality.
  • the outputs of the optical switching fabric 3100, le, If, and lg, are coupled into an optical multiplexer 3130.
  • the optical multiplexer may consist of an optical-to-electronic conversion together with an electronic-to-optical conversion in order to restore the optical signal into its original quahty.
  • the output of the optical multiplexer 3130 is coupled to the optical Unk 41-1 to 41-3.
  • the optical switching matrix for every time frame is extracted from the pluraUty of tables 3000 for w-in and p-in in FIG. 10.
  • the optical transmission and switching have the foUowing temporal pattern, as defined in FIG. 1 IB, with two alternating phases: (1) t-sw - the period of time, responsive to CTR 002, in which the optical switch is switching the optical signals: la, lb, and lc to le, If, and lg, and (2) t-su - the period of time, responsive to CTR 002, in which the optical switching pattern is changed - during this period of time a new optical switching matrix is set-up.
  • the time period of t-sw is much larger than t-su.
  • Method 1 and Method 2 utilize alignment of time frames as shown in FIGS. 13-18.
  • the switch that is described in FIG. 13A operates according to the following switching principle: - From (any TF of any Channel at any Input)
  • predefined TF is either an immediate TF- next TF-or a non- immediate TF-after two, three or more TFs.
  • the switch in FIG. 13A has 16 input ports 3400 and 16 output ports 3800, wherein each port is connected to 16 WDM optical channels 3420.
  • the input ports and output ports are coupled by a switching fabric 50 and the switching operation is controlled by a fabric controUer 52.
  • the fabric controller determines the switching pattern through the switching fabric from the plurality of input optical channels 3420 to the pluraUty of output optical channels 3420.
  • FIG. 13B presents an example of two-phase switch operation:
  • Phase 1 - Receiving & Alignment - in this phase the data packets are received via the optical channels, and stored in the alignment subsystem 3500 in FIG. 14 and ahgned with the CTR 002, which is discussed below.
  • Phase 2 - Switching & Transmitting - in this phase the content of a whole time frame is switched and then transmitted to the optical channel responsive to the CTR, which means that the transmission of the content of a time frame starts at the beginning of a time frame as determined by the CTR.
  • the input from the optical channel can come either from an output port 3800 of another switch or from an SVP interface 4500 that performs synchronizer/shaper functions, which consist in mapping of asynchronous data packets into time frames. This kind of mapping is typically needed at the network ingress, as shown in FIG. 14.
  • the alignment subsystem 3500 receives its data packet input from the l-to-16 Optical DMUX & Serial Receivers (SONET/SDH) &Serial-to-Parallel
  • the 3430 connection can be either a serial Unk or a paraUel bus.
  • the data packets that output from the aUgnment subsystem 3500 are transferred to out-going optical channels via the switching fabric 50.
  • Each of the incoming optical channels (j) has a unique time reference (UTR-j), as shown in FIG. 16, that is independent of the CTR 002, also shown in FIG. 16.
  • the (UTR-j) is divided into SCs (super-cycles), TCs (time cycles), and TFs (time frames) of the same durations as the SCs, TCs, and TFs of the CTR used on optical channel (j), as it was shown in FIG. 2.
  • Each of the SCs, TCs, and TFs of the (UTR-j) starts and ends at a time different than the respective start and end in time of the SCs, TCs, and TFs of the CTR.
  • a plurality of buffer queues 3550 are part of each aUgnment subsystem 3500, wherein each of the respective buffer queues is associated, for each of the TFs, with a unique combination of one of the incoming optical channels and one of the outgoing optical channels.
  • TCs, and TFs of the UTR-j can be exphcit or implicit delimiters.
  • the explicit delimiters can be realized by one of the control codewords from
  • FIG. 5C There can be a different delimiter control word to signal the beginning of a new TF (i.e., a time frame delimiter - TFD), TC (i.e., a time cycle delimiter - TCD) and SC (i.e., a super-cycle delimiter - SCD).
  • the explicit delimiter signaUng can be reaUzed by the SONET/SDH path overhead field that was design to carry control, signaling and management information.
  • An implicit delimiter can be realized by measuring the UTR-j time with respect to the CTR.
  • a mapping controller within the fabric controller 52 system for logically mapping, for each of the (UTR-j) TFs, selected incoming optical channels (j) to selected buffer queues, and for logically mapping, for each of the CTR TFs, selected ones of the pluraUty of buffer queues to selected outgoing channels (1).
  • Each aUgnment subsystem 3500 selects which of the buffers 3550 wiU receive data packets from the optical channel (j) at every time frame as it is defined by the (UTR-j).
  • the selection process by the alignment subsystem 3500 is responsive to the Select-in signal 3510 received from the fabric controUer 52.
  • the Select-in signal 3510 is fed into a l-to-3 DMUX (demultiplexer) 3520 that selects one of 3 queue buffers in 3550: TF Queue 1, TF Queue2, TF Queue3.
  • the buffer queues in the aUgnment subsystem for each time frame can be filled with data packets in arbitrary order to an arbitrary level, prior to output.
  • the aUgnment subsystem 3500 comprised of a pluraUty of TF queues, wherein each of the time frame queues comprises means to determine that the respective time frame queue is empty, wherein each of the time frame queues further comprises means to determine that the respective time frame queue is not empty.
  • the empty (and not empty) signal 3450 is provided to the fabric controller 52.
  • the mapping controller further provides for coupling of selected ones of the time frame queues 3550 to respective ones of the outgoing channels (1), for transfer of the respective stored data packets during the respective associated CTR time frames. This operation is performed responsive to the Select-out signal 3530, as shown in FIG. 15.
  • FIG. 16 A timing diagram description of the alignment operation is provided in FIG. 16.
  • TF queue (TF Queue 1, TF Queue2, TF Queue3 - 3550) is not written into and read from at the same time.
  • the Select-in signal 3510 and the Select-out signal 3530 wiU not select the same TF queue at the same time.
  • the alignment subsystem 3500 can have more than three TF queues 3550 - this can be used for Non-immediate forwarding method: in this method a data packet is delayed in the input port until there is an available time frame to be switched to the selected one of the outgoing optical channels (1). In this method the delay is increased, Le., more time frames may be needed to get from input to output. The non-immediate forwarding add flexibility to the scheduling process of SVPs.
  • the alignment subsystem 3500 comprises only two buffers and an optical delay Une.
  • One buffer receives data from the corresponding input link, while data to be transferred through the switching fabric are retrieved from the other buffer.
  • the delay line between the input link and the aUgnment subsystem ensures that the UTR of the corresponding link is aligned with the CTR.
  • the time a packet takes to travel from the aUgnment subsystem of the upstream time driven switch 10 to the aUgnment subsystem of the considered switch is an integer multiple of a TF.
  • the delay element adds a link delay equal to the difference between a beginning of the CTR time frame and a beginning of the UTR-j time frame.
  • the optical delay line can have programmable tap points possibly comprised of optical switches.
  • the optical delay Une can be external to the switch, internal, or integrated in the optical receiver.
  • FIG. 18 shows the output port 3800 for 16 optical channels 3420. The output port performs the Parallel- to- Serial Conversion, the SONET/SDH Transmission, and the 16-to-l Optical MUX into an optical fiber.
  • FIG. 17 shows a switching fabric 50 with a fabric controller (FC) 52.
  • FC fabric controller
  • the switching matrices 3721 follow the following restrictions:
  • an input optical channel can be connected to one or more output optical channels (multicast - MCST operation of 1 -to-many is possible)
  • an output optical channel can be connected to at most one input optical channel
  • the information contained in the switching matrices 3721 is defined in a pluraUty of examples, which were presented in FIG. 8 and FIG. 10.
  • the fabric controller 52 is responsive to UTC 002 and provides the foUowing control signals: (1) Select-in signal 3510 and the Select-out signal 3530 to the alignment subsystem 3500, and (2) Read signals 3921 to the Routing Module 4000.
  • the switching fabric 50 in FIGS. 1, 13, 17 and 21, as well as the switching expander 4300 in FIGS. 22-23, can be reaUzed in many ways.
  • a well known but complex method is a crossbar.
  • the crossbar has a switching element between every input and every output. Consequently, the total number of switching elements required to realize the crossbar is the number of inputs (N) times the number of outputs
  • switching fabric 50 and switching expander 4300 there are many other ways to realize the switching fabric 50 and switching expander 4300 with fewer switching elements, such as, a generalized multi-stage cube network, a Clos network, a Benes network, an Omega network, a Delta network, a multi- stage shuffle exchange network, a perfect shuffle, a Banyan network, a combination of demultiplexers and multiplexers.
  • a generalized multi-stage cube network such as, a Clos network, a Benes network, an Omega network, a Delta network, a multi- stage shuffle exchange network, a perfect shuffle, a Banyan network, a combination of demultiplexers and multiplexers.
  • FIGS. 29C- 30B are examples of multi-stage shuffle exchange networks or generaUzed-cube networks that can be used to realized the switching fabric 50 and switching expander 4300 in the context of this invention.
  • the shuffle exchange network requires only a*N*lgaN switching elements, where N is the number on inputs and outputs, and a is the number of inputs and outputs of each switching block 4900.
  • the number on inputs and outputs of the switching fabric 50 in FIG. 29C is 8
  • Method 3 utilizes combined time frame switching with asynchronous packet switching as shown in FIGS. 19-24.
  • part of the content of a time frame is routed according to time and part according to information contained in the data packet header.
  • Data packets routed according to time have reserved transmission capacity and are forwarded according to a predefined schedule.
  • Packets that are routed according to header information do not have reserved capacity and a predefined schedule (non- scheduled data packets or NSDPs).
  • NSDP are forwarded during time frames presenting some spared capacity.
  • FIG. 19 is the functional architecture of an input port 3900.
  • the DWDM optical channels are demultiplexed and each stream of bits converted in an equivalent parallel stream 3430 by an optical demultiplexer module 3410.
  • a Filter module 3910 separates data packets that are to be routed according to header information from those that are to be routed according to time information, i.e., based on the time frame in which they have been received.
  • the Filter module 3910 sorts out packets based on information contained in their header.
  • FIG. 6A shows a sample data packet header; the Filter 3910 sorts data packets based on the content of the priority field 35P.
  • Other examples of information that can be used for filtering are the Differentiated Services (DS) Field in the header of an IP packet or the MPLS label of an Multi-Protocol Label Switching frame.
  • the Filter module 3910 can operate also based on a single bit contained in the header that differentiates NSDPs from scheduled data packets.
  • a control codeword (see FIG. 5) is inserted into the time frame for separating the non-scheduled type of service data packets from the scheduled type of service data packets.
  • the Filter module 3910 sorts separates scheduled data packets from NSDP by using the aforementioned control codeword. For example, the Filter module 3910 could take out the data packets that are after the control codeword (or between a pair of control codewords) as non-scheduled type of service.
  • the FUter module 3910 features 2 output lines. Scheduled packets are moved through one output line 3914 to the alignment subsystem 3500 of the channel on which they have been received. NSDPs are delivered through another output line 3911 to a Routing Module 4000.
  • the block diagram of the alignment subsystems 3500 is shown in FIG. 15; the purpose, the working principles, and the control signals of the alignment subsystems
  • the Routing Module 4000 sorts NSDPs in 16 queues 4030, one for each output port. Packets are sorted according to the output port 3800 form which they have to be forwarded in order to reach their final destination. The output port 3800 to which a packet is directed is determined by the
  • Routing ControUer 4010 based on the pipe identifier (PID) 35C shown in FIG. 6A.
  • PID pipe identifier
  • Other examples of information on which the choice of the output port can be based include, but are not timited to, the IP destination address, the MPLS label, the MAC address.
  • the Routing Controller 4010 devises the queue 4030 the packet should be stored in from information contained in a routing table 4020.
  • the Routing Controller 4010 can use the PID 35C as an index to the routing table 4020.
  • the row corresponding to the PID value contains the number of the output port the packet should be forwarded from, i.e., the queue 4030 the packet should be stored in.
  • Part of the NSDPs can be directed outside the sub-network in which the technology disclosed in this invention is deployed; the Routing Controller 4010 transmits them over the output port 3912. Analogously, NSDPs can enter the subnetwork through input 3913.
  • FIG. 21 shows the connections 3440/4050 between the input port 3900 and the switching fabric 50.
  • the switching fabric 50 can connect any one of the alignment subsystem outputs 3440 and of the routing module outputs 4050 to any of the input lines 3810 of any of the output ports 3800.
  • the switching fabric 50 has 512 inputs 3440/4050 and 256 outputs 3810.
  • a fabric controller 52 establishes the input/output connections through the switching fabric 50. At each time frame the fabric controller 52 connects each line 3440 from the alignment subsystems 3500 to one of the output lines 3810 according to a predefined pattern which repeats itself periodically. The period can be one time cycle, one super-cycle, or any other duration.
  • the content of the aUgnment system's queue 3550 (either TF Queue 1, or TF Queue2, or TF Queue3) selected by the fabric controller 52 through the select-out control signal 3530 is switched to a given output channel 3810.
  • the fabric controller 52 determines through the select-in control signal 3510 the queue 3550 in which all the scheduled data packets received on an optical channel 3430 should be stored.
  • the queue 3550 in which incoming packets are stored is selected according to a predefined pattern that repeats itself periodically. The period can be one time cycle, one super-cycle, or any other duration.
  • the time frame in which scheduled packets are received determines the path of such packets through the network.
  • the alignment subsystem 3500 uses the empty control signal 3450 to notify the fabric controller 52 when the queue 3550 selected through the select-out 3530 signal is empty.
  • the fabric controller 52 programs the switching fabric 50 to connect the idle output channel 3810 to the proper output 4050 of the Routing Module 4000.
  • Such proper output 4050 is the one corresponding to the queue 4030 to the output port 3800 to which the idle channel 3810 belongs.
  • the NSDP queue 4030 that is connected to the idle channel 3810 can be in either the same input port 3900 as the empty scheduled data packet queue 3550, or another input port 3900.
  • the fabric controller 52 knows which NSDP queues 4030 are empty thanks to the full/empty control signals 4040.
  • the fabric controller 52 selects an NSDP queue from which NSDPs are to be retrieved through the read 3921 control signal.
  • the fabric controller 52 is centtalized; however different implementations are possible, consistent with the present invention, that distribute the fabric controller 52 functionality.
  • the switching fabric 50 can be implemented, not excluding other ways, as a crossbar or as a multi-stage network of 2-by-2 or 4-by-4 switching elements, which has lower complexity than a crossbar.
  • All the control signals generated or received by the fabric controller 52 (to control the switching fabric 50, to select the alignment system's queue 3550 for input 3510 and for output 3530, to know whether the queues are empty 3450/4040, etc.) need to be varied with a time scale comparable with the time frame duration.
  • all the control signals are either predetermined according to a repetitive pattern, or can be devised in advance from the state of the system during the preceding time frame.
  • the control signals can be given in the time frame prior the one in which the components are supposed to react to them. This is beneficial when the switch is operated at very high speed and the delay introduced by the control logic and by signal propagation can be limiting.
  • FIGS. 22, 23 and 24 show an alternative implementation of a switch that can route scheduled data packets according to time and NSDPs according to information contained in their header.
  • the input port 4200 comprises an optical demultiplexer 3410 that separates the 16 WDM optical channels 3420 over 16 separate lines 3430 connected to a switching expander module 4300.
  • the purpose of the switching expander module 4300 is to enable the connection of each input channel 3420 to any optical channel 3820 on any output port 4400.
  • a filter 3910 inserted on the outputs 3430 of the demultiplexer 3410 separates NSDPs from the scheduled data packets that are the only ones entering the switching expander module 4300.
  • the filter 3910 (shown in FIG. 22) directs NSDPs to a
  • Routing Module 4000 (not shown in FIG. 22) that routes them according to information contained in the data packet header, as previously described.
  • Both scheduled data packets and NSDPs enter the aUgnment subsystems 4260.
  • Scheduled data packets enter the alignment subsystems 4260 through lines 4231 from the switching expander module 4300;
  • NSDPs enter the alignment subsystems 4260 through lines 4232 from the Routing Module 4000.
  • the alignment subsystem 4260 comprises a multiplicity of queues that are managed as described for the alignment subsystem 3500 shown in FIG. 15. However, the alignment subsystem 4260 handles also NSDPs (not only scheduled data packets). Upon exhaustion of the queue from which data packets are being retrieved for transmission over the line 4330 towards the corresponding output channel 3820, the alignment subsystem 4260 can transmit on line 4330 the NSDPs incoming on line 4232.
  • the alignment subsystem 4260 could store NSDPs incoming from line 4232 in the same queues as scheduled data packets, or the alignment subsystem 4260 could comprise a separate queue for storing NSDPs, or the Routing Module 4000 could comprise such a queue.
  • the switch comprises a distributed Expander Controller that consists of an input part 4210 in each input port 4200 and an output part 4410 in each output port 4400.
  • the distributed Expander ControUer determines the output channel 3820 on which packets received from each input channel 3420 are being forwarded. This is achieved by (1) the input part 4210 of the Expander ControUer (la) configuring the input/output connections of the switching expander 4300 and (lb) enabUng the output 4330 of the proper aUgnment subsystem 4260, and (2) the output part 4410 controlling the selectors 4420 of each channel on every output port 4400.
  • each input 3430 of the switching expander 4300 is connected with one or more (for multicast support) outputs 4231.
  • a subset of the alignment subsystems 4260 is enabled to transmit packets on the lines 4330 towards their correspondent output channel 3820.
  • the output part 4410 of the Expander ControUer determines from which input port 4200 packets should be retrieved for forwarding on each output channel 3820. This is achieved by the output part 4410 of the Expander Controller selecting one of the inputs 4330 of the 16 selectors 4420 contained in the output port 4400, as shown in FIG. 24.
  • the output 3810 of the selectors 4420 are multiplexed by an Optical Multiplexer 3800 and transmitted on the outgoing fiber as separate WDM channels 3820.
  • the control signals generated by the input parts 4210 and the output parts 4410 of the distributed Expander ControUer change with a period comparable to the duration of the time frame.
  • the sequence of control signals is predetermined when SVPs are set up and repeats with a period of one time cycle, or one super-cycle, or any other duration. As a consequence, no communication is required among the different parts of the distributed expander controller in order to devise the control signals they generate.
  • FIG. 23 shows one realization of the switching expander 4300 as a 16 by 256 crossbar.
  • Other topologies including but not limited to, multistage networks of 2-by-2 or 4-by-4 switching elements can be deployed in the realization of the switching expander 4300.
  • Method 4 provides an SVP interface to time frame switching from asynchronous packet switching as shown in FIGS. 25-28.
  • IP/MPLS Internet protocol/multi-protocol label switching
  • SVP Synchronous Virtual Pipe
  • An SVP interface module is required to forward over an SVP packets that have traveled over an asynchronous packet network. As shown in FIG. 27, the SVP interface module is required only for the input Unks connecting multi-protocol SVP time driven switches to asynchronous packet switches; the SVP interface module is not required on links connecting multi-protocol SVP time driven switches, i.e., switches that use the technology disclosed in this invention. Moreover, as shown in FIG. 26B, the SVP interface module 4600 is required only in the inbound direction of the interface of the multi-protocol SVP time driven switch 10, not in the outbound direction.
  • FIG. 25 shows the block diagram of the SVP interface 4500 according to the first alternative.
  • a Packet Scheduling ControUer 4510 processes asynchronous data packets arriving from an input link 4501. Based on information contained in the packet header — such as the PID field 35C (see FIG. 6), or an MPLS label, or the destination address in an IP packet, or the VCI/VPI in an ATM cell, or other header fields — the Packet Scheduling Controller 4510 identifies the SVP to which the asynchronous data packet belongs.
  • the relevant header information is used, for example as a lookup key, to retrieve SVP schedule information from a pre-computed table 4511. Typical schedule information include, but are not limited to, the time frames in which packets belonging to each SVP should be forwarded on the link 41 towards a multi-protocol SVP time-driven switch 10.
  • the Packet Scheduling Controller 4510 Once processed by the Packet Scheduling Controller 4510, data packets are stored in a per time frame queuing system 4540.
  • the per time frame queuing system 4540 comprises a multiplicity of queues 4550. Each queue is associated with one time frame.
  • the Forwarding ControUer 4520 retrieves the packets contained in a specific queue 4550 during the time frame associated to that queue.
  • the Packet Scheduling Controller 4510 stores an incoming packet in the queue 4550 currently associated to one of the time frames reserved for the SVP to which the packet belongs.
  • an SVP interface implementation could feature a per time frame queuing system 4540 that contains one queue for each time frame in the time cycle.
  • the Packet ScheduUng Controller 4510 devises the PID 35C from the data packet header and uses it as a key to the SVP Schedules table 4511 to retrieve the pointers to the queues 4550 in which the data packet should be stored.
  • the Packet Scheduling ControUer 4510 moves the packets to one of the selected queues 4550.
  • the Packet Scheduling ControUer 4510 can choose the specific queue 4550 in which to store the packet.
  • One possible implementation consists in choosing the first queue 4550 that will be served, i.e., the one associated to the next time frame to come.
  • Each queue 4550 can be organized in 3 sub-queues: CBR (Constant Bit Rate),
  • the Packet Scheduling Controller 4510 determines the type of traffic to which incoming data packets belong based on information contained in the header, such as the PID 35C, the Differentiated Services (DS) Field in IP packets, the VPI/VCI fields in ATM cells, or any other (combination of) header fields.
  • the PID 35C the Packet Scheduling Controller 4510 determines the type of traffic to which incoming data packets belong based on information contained in the header, such as the PID 35C, the Differentiated Services (DS) Field in IP packets, the VPI/VCI fields in ATM cells, or any other (combination of) header fields.
  • DS Differentiated Services
  • the Forwarding ControUer 4520 retrieves and forwards on the line 41 towards a multi-protocol SVP time-driven switch data packets stored in the queues 4550 associated to the given time frame.
  • a preferred policy for data packets retrieval is presented; other poticies can be appUed.
  • Data packets contained in the CBR sub-queue are retrieved first, starting at the beginning of the time frame associated to the queue 4550. If the CBR sub-queue becomes empty before the end of the time frame associated to the selected queue 4550, data packets in the VBR sub-queue are retrieved and forwarded. If the VBR sub-queue becomes empty before the end of the time frame associated to the queue 4550, data packets in the "Best effort" sub-queue are retrieved and forwarded.
  • the sub-queues can be ordered in various ways and even logically organized in multiple sub-queues.
  • the Forwarding Controller 4520 can apply a variety of packet scheduling algorithms, such as, FIFO, simple priority, round robin, weighted fair queuing. Also the order in which packets are retrieved from the various sub-queues (i.e., the relative priority of the sub- queues) depends on the adopted queue management policy.
  • Rescheduling ControUer 4530 sorts packets in the different queues 4550 of the per time frame queuing system 4540 simUarly to the Packet Scheduling ControUer 4510.
  • the operation of the Rescheduling Controller 4530 is based (i) on information retrieved from the SVP Schedules table 4511 (for example, using data packet header fields as access key), and/or ( ⁇ ) on the queue in which the packets had been previously stored.
  • the SVP interface can have multiple lower capacity input Unes 4501 that are aggregated on the same higher speed output line 41.
  • data packets are received from multiple input Unes 4501, sorted in the queues 4550 of the same per time frame queuing system 4540 from which the Forwarding Controller 4520 retrieves data packets for transmission on the output line 41.
  • the Forwarding ControUer 4520 can be comprised of a plurality of Forwarding Controllers, each one associated with at least one of the channels 41. There can be a plurality of sets of queues 4540, each set comprising at least one queue 4550, wherein each set 4540 is associated with one of the Forwarding Controllers 4520.
  • FIG. 26 shows the block diagram of the SVP interface 4600 implemented according to the second alternative. Incoming packets are stored in a queuing system that comprises multiple queues 4610. Each queue 4610 is associated to a specific SVP 25; data packets are stored in the queue 4610 corresponding to the SVP 25 they belong to.
  • the SVP to which data packets belong (i.e., the identity of the queue in which they should be stored) is devised through information contained in their header, such as the PID field 35C, the destination address or the DS field in an IP packet or a combination of the two, the MPLS label, the VPI/NCI of an ATM ceU, or any other (combination of) header fields.
  • An SVP Forwarding Controller 4630 retrieves data packets from the queue associated to the SVP 25 for which the current time frame had been reserved.
  • the current time frame is identified in accordance to the Common Time Reference 002.
  • Retrieved packets are transmitted on an output line 41 towards a Multi-protocol SVP Time-driven Switch 10.
  • the SVP Forwarding Controller 4630 possibly changes the queue 4610 from which to retrieve packets.
  • the new queue 4610 is identified by consulting the SVP Schedules database 4640 which contains, among other information, the SVP to which each time frame had been reserved.
  • the SVP Forwarding ControUer 4630 can retrieve packets from more than one queue 4610 and forward them on more than one output line 41.
  • the SVP Schedules database 4640 provides for each time frame, the SVP 25 for which it has been reserved on each of the output Unes 41.
  • each time frame can be reserved for zero (not reserved) to as many SVPs 25 as the number of output lines 41.
  • the SVP Interface 4600 can comprise a plurality of SVP Forwarding ControUer
  • Modules 4620 each associated with at least one of a plurality of asynchronous data streams.

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Abstract

L'invention concerne un procédé et un système de commutation de cadre temporel constitués d'unités de données qui utilisent une référence temporelle commune globale (002) qui se divise en une pluralité de cadres temporels périodiques contigus (G1-G4). Ce système est destiné à fonctionner au moyen de liaisons de multiplexage en longueur d'onde (WDM), c'est-à-dire au moyen de multiples lambdas. La pluralité d'unités de données qui est contenue dans chaque cadre temporel (G1-G4, R1-R4) est retransmise en pipeline via les commutations de réseau et peut être commutée à partir de n'importe quel canal WDM entrant (41-1, 41-k) sur n'importe quel sous-ensemble de canaux WDM sortants (41-1, 41-k) en fonction de la référence temporelle commune globale (002). Le résultat de ce procédé de commutation s'appelle la commutation lambda fractionnelle. Ce système de commutation comprend également un système d'interface pour des flux de paquets de données asynchrones. Ce système d'interface peut regrouper de multiples flux de paquets de données asynchrones en un seul programme de commutation prédéfini via le système de commutation synchronisé.
PCT/US2000/030390 1999-11-09 2000-11-03 Commutation de cadre temporel en fonction d'une reference temporelle commune globale WO2001035587A1 (fr)

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US16443799P 1999-11-09 1999-11-09
US60/164,437 1999-11-09
US09/535,831 2000-03-28
US09/536,948 US6778536B1 (en) 1999-11-09 2000-03-28 Combined wavelength division multiplexing, time division multiplexing, and asynchronous packet switching with common time reference
US09/536,948 2000-03-28
US09/536,811 2000-03-28
US09/536,708 US6674754B1 (en) 1999-11-09 2000-03-28 Wavelength division multiplexing combined with time division multiplexing using a common time reference
US09/535,831 US7426206B1 (en) 1998-06-11 2000-03-28 Switching system and methodology having scheduled connection on input and output ports responsive to common time reference
US09/536,811 US6735199B1 (en) 1999-11-09 2000-03-28 Time frame switching responsive to global common time reference
US09/536,708 2000-03-28

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CN113112028B (zh) * 2021-04-06 2022-07-01 西华大学 一种基于标签设计的机器学习时间同步方法

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