WO2001029818A8 - Operation atomique dans un systeme a acces memoire en mode rafale - Google Patents

Operation atomique dans un systeme a acces memoire en mode rafale

Info

Publication number
WO2001029818A8
WO2001029818A8 PCT/US2000/025746 US0025746W WO0129818A8 WO 2001029818 A8 WO2001029818 A8 WO 2001029818A8 US 0025746 W US0025746 W US 0025746W WO 0129818 A8 WO0129818 A8 WO 0129818A8
Authority
WO
WIPO (PCT)
Prior art keywords
read
buffer
write
requests
memory access
Prior art date
Application number
PCT/US2000/025746
Other languages
English (en)
Other versions
WO2001029818A1 (fr
Inventor
Dong-Ying Kuo
Derek C Chang
Original Assignee
S3 Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S3 Inc filed Critical S3 Inc
Publication of WO2001029818A1 publication Critical patent/WO2001029818A1/fr
Publication of WO2001029818A8 publication Critical patent/WO2001029818A8/fr

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

L'invention concerne une unité de profondeur d'un système graphique à trois dimensions pourvue d'un tampon de lecture et d'un tampon d'écriture. Le tampon de lecture mémorise les demandes de lecture et le tampon d'écriture les demandes d'écriture. Les demandes de lecture et d'écriture correspondent à des opérations atomiques de manipulations de mémoire de profondeur. Dès réception d'une demande de lecture, on compare l'adresse de ladite demande à chacune de ses autres adresses. S'il y a concordance, le tampon de lecture est alors vidé jusqu'à la survenue d'une première demande de lecture avec l'adresse concordante. Le tampon d'écriture est alors vidé et toutes les demandes d'écriture dans le tampon d'écriture sont traitées. Le tampon de lecture est de nouveau vidé jusqu'à ce que toutes les demandes de lecture dans le tampon de lecture soient traitées.
PCT/US2000/025746 1999-10-18 2000-09-20 Operation atomique dans un systeme a acces memoire en mode rafale WO2001029818A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/420,047 US6756986B1 (en) 1999-10-18 1999-10-18 Non-flushing atomic operation in a burst mode transfer data storage access environment
US09/420,047 1999-10-18

Publications (2)

Publication Number Publication Date
WO2001029818A1 WO2001029818A1 (fr) 2001-04-26
WO2001029818A8 true WO2001029818A8 (fr) 2001-09-13

Family

ID=23664860

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/025746 WO2001029818A1 (fr) 1999-10-18 2000-09-20 Operation atomique dans un systeme a acces memoire en mode rafale

Country Status (2)

Country Link
US (2) US6756986B1 (fr)
WO (1) WO2001029818A1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6756986B1 (en) * 1999-10-18 2004-06-29 S3 Graphics Co., Ltd. Non-flushing atomic operation in a burst mode transfer data storage access environment
CA2329287A1 (fr) * 2000-01-21 2001-07-21 Symagery Microsystems Inc. Interface hote pour dispositif d'imagerie
US20030023958A1 (en) * 2001-07-17 2003-01-30 Patel Mukesh K. Intermediate language accelerator chip
US7290080B2 (en) * 2002-06-27 2007-10-30 Nazomi Communications Inc. Application processors and memory architecture for wireless applications
US8081182B2 (en) * 2004-03-03 2011-12-20 Qualcomm Incorporated Depth buffer for rasterization pipeline
US8112584B1 (en) 2004-06-28 2012-02-07 Cisco Technology, Inc Storage controller performing a set of multiple operations on cached data with a no-miss guarantee until all of the operations are complete
US20070052704A1 (en) * 2005-09-08 2007-03-08 Arm Limited 3D graphics image formation
US20070256019A1 (en) * 2006-04-14 2007-11-01 Hirsave Praveen P K Display Sharing Preference System
US8112595B1 (en) 2008-05-01 2012-02-07 Marvell Semiconductor Israel Ltd. Command cancellation channel for read—modify—write operation in a memory
US8838853B2 (en) * 2010-01-18 2014-09-16 Marvell International Ltd. Access buffer
US9058675B2 (en) * 2010-05-29 2015-06-16 Intel Corporation Non-volatile storage for graphics hardware
US9053562B1 (en) 2010-06-24 2015-06-09 Gregory S. Rabin Two dimensional to three dimensional moving image converter
US9245496B2 (en) 2012-12-21 2016-01-26 Qualcomm Incorporated Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations
US9992021B1 (en) 2013-03-14 2018-06-05 GoTenna, Inc. System and method for private and point-to-point communication between computing devices
US10585623B2 (en) 2015-12-11 2020-03-10 Vivante Corporation Software defined FIFO buffer for multithreaded access

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230064A (en) 1991-03-11 1993-07-20 Industrial Technology Research Institute High resolution graphic display organization
US5388207A (en) 1991-11-25 1995-02-07 Industrial Technology Research Institute Architecutre for a window-based graphics system
US5299309A (en) 1992-01-02 1994-03-29 Industrial Technology Research Institute Fast graphics control system capable of simultaneously storing and executing graphics commands
WO1997039437A1 (fr) 1996-04-12 1997-10-23 Intergraph Corporation Tampon de trames video a vitesse elevee utilisant des puces memoires a port unique ou les valeurs d'intensite des pixels destines aux zones d'affichage sont stockees au niveau d'adresses consecutives de blocs memoires
US5852451A (en) 1997-01-09 1998-12-22 S3 Incorporation Pixel reordering for improved texture mapping
US6166743A (en) * 1997-03-19 2000-12-26 Silicon Magic Corporation Method and system for improved z-test during image rendering
US5937204A (en) 1997-05-30 1999-08-10 Helwett-Packard, Co. Dual-pipeline architecture for enhancing the performance of graphics memory
US5945997A (en) 1997-06-26 1999-08-31 S3 Incorporated Block- and band-oriented traversal in three-dimensional triangle rendering
US5948081A (en) 1997-12-22 1999-09-07 Compaq Computer Corporation System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed
US6329997B1 (en) * 1998-12-04 2001-12-11 Silicon Motion, Inc. 3-D graphics chip with embedded DRAM buffers
US6168743B1 (en) 1999-06-15 2001-01-02 Arteva North America S.A.R.L. Method of continuously heat treating articles and apparatus therefor
US6756986B1 (en) 1999-10-18 2004-06-29 S3 Graphics Co., Ltd. Non-flushing atomic operation in a burst mode transfer data storage access environment

Also Published As

Publication number Publication date
WO2001029818A1 (fr) 2001-04-26
US6756986B1 (en) 2004-06-29
US6956578B2 (en) 2005-10-18
US20050007374A1 (en) 2005-01-13

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