WO2001024967A1 - Method for soft soldering of components and a soft soldered device - Google Patents

Method for soft soldering of components and a soft soldered device Download PDF

Info

Publication number
WO2001024967A1
WO2001024967A1 PCT/EP2000/009235 EP0009235W WO0124967A1 WO 2001024967 A1 WO2001024967 A1 WO 2001024967A1 EP 0009235 W EP0009235 W EP 0009235W WO 0124967 A1 WO0124967 A1 WO 0124967A1
Authority
WO
WIPO (PCT)
Prior art keywords
fiber
solder
soldering
soft
components
Prior art date
Application number
PCT/EP2000/009235
Other languages
German (de)
French (fr)
Inventor
Hans-Joachim Krokoszinski
Hans-Joachim Schmutzler
Original Assignee
Abb Research Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Abb Research Ltd. filed Critical Abb Research Ltd.
Priority to AU75217/00A priority Critical patent/AU7521700A/en
Publication of WO2001024967A1 publication Critical patent/WO2001024967A1/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B23K35/025—Pastes, creams, slurries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01043—Technetium [Tc]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0215—Metallic fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/0281—Conductive fibers

Definitions

  • the invention relates to a method for connecting components by means of soft soldering, in particular for connecting lossy components of power electronics to substrates.
  • the invention also relates to soft-soldered arrangements, in particular power electronics.
  • Power electronic arrangements generally require cooling, since the dissipation of lost heat or the operating temperature that is established is decisive for the load-bearing capacity of electronic components in particular.
  • the most common type of cooling of lossy components or assemblies in power electronics is air cooling.
  • the power components are usually grouped into compact modules, which consist of a plastic housing with a ceramic, copper-clad substrate to which IGBTs, MOSFETs, free-wheeling diodes or even just rectifier diodes are soldered. These modules are pressed onto a massive finned aluminum heat sink, which absorbs the heat loss from the module floor and releases it into the ambient air through natural or forced convection via its large surface.
  • the mass and volume of the heat sink determine its thermal resistance R th (cooler) and thus the temperature difference ⁇ T ca , which occurs at maximum power loss W i0Ss between the heat sink surface Tc and the ambient temperature T a :
  • R t h module thermal resistance
  • the heat sink heat resistance must be dimensioned sufficiently small according to:
  • the only manipulated variable left is the surface and thus the volume and mass of the heat sink. If the cost, weight and volume of such a lossy assembly are to be reduced at the same time, the heat sink must be reduced drastically. This means a significant increase in its thermal resistance and thus an increase in the junction temperatures according to equation (2) in the semiconductor components above 125 ° C. According to the manufacturers of semiconductor components, this leads to a drastic reduction in the reliability and service life of the components and thus of the modules.
  • Si components could still be operated, if possible, in addition to the Wire bonds also reliably produce the solder joints against temperature and load changes between 0 ° C and these maximum temperatures, which has so far not been possible with the applied soldering techniques, because the constant thermal alternating loading hardens the solder structure and leads to crack formation and ultimately to the solder joint being torn off.
  • the state of soldering technology using the example of the IGBT modules is:
  • solder foil pieces e.g. the composition Pb95Sn5 (flux-free, liquidus temperature 313 ° C),
  • soldering molds usually made of graphite
  • EP 0 476 734 A1 it is proposed to use a dispersion of 5% by volume of particles from the intermetallic compounds Ni3Sn4 or Cu9NiSn3 in order to harden lead-tin solder.
  • this does not adequately wet the dispersed parts with the respective solder.
  • a deterioration in the elastic expansion range of the solder without crack formation and unfavorable flow and wetting behavior can occur.
  • metallic powders Au
  • JP 09 330 941 A the mixing of granular metal powder into solders is also described.
  • the task to be solved is to specify a soldering process which, on the one hand, offers the usual soldering quality with regard to wetting, freedom from pores, mechanical strength and electrical conductivity, and, on the other hand, permanent use of the arrangements produced thereafter up to junction temperatures of 150 ° C to 175 ° C, even under thermal cycling allowed without cracking and spreading.
  • an arrangement is to be specified that can work in the aforementioned temperature range.
  • Fiber pieces are preferably used which have a surface which is particularly well solderable with Pb-rich solders. Nickel is particularly suitable for this.
  • Fibers are particularly suitable for increasing elasticity.
  • solders can still be applied to the soldering surfaces of the substrates or printed circuit boards using a screen printing process
  • solders can be melted using the same reflow methods with temperature profiles (which may need to be modified slightly).
  • a suitable choice of the fiber material, especially nickel, or coating with nickel ensures good wetting of the individual fibers and thus a cohesive incorporation into the solder structure;
  • the surface temperature of the heat sink could be increased by the same amount (here 30K) from (typically) 85 ° C to 115 ° C. This would double the temperature difference between the heat sink surface and the maximum ambient temperature of 55 ° C from 30K to 60K, thus reducing the surface area, volume, weight and cost of the heat sink by a factor of 0.5.
  • Fig. 2 shows a typical arrangement of a metallized substrate with soldered components
  • Fig. 3 illustrates the practical impact of using a fiber-reinforced solder.
  • 1 shows a solder joint on the left-hand side of the image, a metallization 1 of a substrate, not shown, to which a component 3 is soldered by means of a fiber-reinforced solder 2 being shown.
  • the solder 2 On the right-hand side of FIG. 1, the solder 2 is shown schematically and enlarged. It can be seen that 5 pieces of fiber 4 are embedded in a pasty solder.
  • the fiber pieces 4 are provided with a well-wetting surface coating of nickel 6, or they consist entirely of nickel.
  • FIG. 2 shows a schematic representation of an arrangement with a substrate 7, for example a ceramic substrate made of Al 2 O 3 or AIN, which has metallizations 1 on its top and bottom.
  • a substrate 7 for example a ceramic substrate made of Al 2 O 3 or AIN, which has metallizations 1 on its top and bottom.
  • substrates such as, for example, DCB substrates
  • the semiconductor chips 9 are soldered onto metallizations 1 by means of a fiber-reinforced solder 2. Electrodes of the chips 9 are connected to further metallizations 1 by means of wire bonds 8, for example made of aluminum.
  • FIG. 3 shows which effects can be achieved by comparing a conventional arrangement shown on the left and an arrangement according to the invention shown on the right.
  • an aluminum heat sink 10 provided with fins is shown, to which an arrangement shown, for example, in FIG. 2 is applied with good thermal conductivity.
  • generated in the semiconductor chip 9 is thereby generated 0SS dissipated to the heat sink 10.
  • junction temperature may be higher in the arrangement according to the invention, a smaller heat sink surface is sufficient.
  • other parts for example metallic housing parts, can also be soldered using the fiber-reinforced solder.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to a method for bonding metal parts by soft soldering. A fiber-reinforced solder (2) is used in this invention and produced by mixing a paste-like solder (5) with fiber segments (4). Said fiber segments (4) can be provided with a surface coating (6).

Description

Verfahren zum Weichlöten von Komponenten und weichgelötete AnordnungMethod of soft soldering components and soft soldered assembly
Beschreibungdescription
Die Erfindung bezieht sich auf ein Verfahren zum Verbinden von Komponenten mittels Weichlöten, insbesondere zur Verbindung von verlustbehafteten Bauelementen der Leistungselektronik mit Substraten. Außerdem bezieht sich die Erfindung auf weichgelötete Anordnungen, insbesondere der Leistungselektronik.The invention relates to a method for connecting components by means of soft soldering, in particular for connecting lossy components of power electronics to substrates. The invention also relates to soft-soldered arrangements, in particular power electronics.
Leistungselektronische Anordnungen bedürfen in der Regel einer Kühlung, da die Abfuhr von Verlustwärme, bzw. die sich einstellende Betriebstemperatur maßgeblich ist für die Belastbarkeit insbesondere elektronischer Bauelemente.Power electronic arrangements generally require cooling, since the dissipation of lost heat or the operating temperature that is established is decisive for the load-bearing capacity of electronic components in particular.
Gängigste Art der Kühlung von verlustbehafteten Bauelementen oder Baugruppen der Leistungselektronik ist die Luftkühlung. Die Leistungsbauelemente sind meist gruppiert in kompakten Modulen, die aus einem Kunststoffgehäuse mit einem keramischen kupferkaschierten Substrat bestehen, auf das IGBTs, MOSFETs, Freilaufdioden oder auch nur Gleichrichterdioden aufgelötet sind. Diese Module werden auf einen massiven gefinnten Aluminium-Kühlkörper gepreßt, der die Verlustwärme aus dem Modulboden aufnimmt und über seine große Oberfläche durch natürliche oder forcierte Konvektion an die Umgebungsluft abgibt. Masse und Volumen des Kühlkörpers bestimmen seinen Wärmewiderstand Rth(Kühlk.) und damit die Temperaturdifferenz αTca, die sich bei maximaler Verlustleistung Wi0Ss zwischen der Kühlkörperoberfläche Tc und der Umgebungstemperatur Ta einstellt:The most common type of cooling of lossy components or assemblies in power electronics is air cooling. The power components are usually grouped into compact modules, which consist of a plastic housing with a ceramic, copper-clad substrate to which IGBTs, MOSFETs, free-wheeling diodes or even just rectifier diodes are soldered. These modules are pressed onto a massive finned aluminum heat sink, which absorbs the heat loss from the module floor and releases it into the ambient air through natural or forced convection via its large surface. The mass and volume of the heat sink determine its thermal resistance R th (cooler) and thus the temperature difference αT ca , which occurs at maximum power loss W i0Ss between the heat sink surface Tc and the ambient temperature T a :
Tc - Ta = ΔTca = Rtn(Kühlk.) * W|0SS (1 )T c - T a = ΔTca = Rtn (refrigerator) * W | 0SS (1)
Auf die Kühleroberflächentemperatur muß noch die vom Modulwärmewiderstand Rth(Modul) bestimmte Temperaturdifferenz ΔTjc = Tj - Tc = Rtrl(Modul) * W|0SS aufaddiert werden, um die Sperrschichttemperatur Tj zu erhalten. Diese wird von den Bauelemente-Herstellern meist mit maximal 125°C angegeben. Tjmax = 125°C = - Tc + (Tc - Ta) + Ta (2)The temperature difference ΔT jc = Tj - T c = R trl (module) * W |. Determined by the module thermal resistance R t h (module) must also be added to the cooler surface temperature 0SS can be added to obtain the junction temperature T j . The component manufacturers usually state this at a maximum of 125 ° C. T jmax = 125 ° C = - T c + (T c - T a ) + T a (2)
= (Rth(Modul) + Rth(Kühlk.) ) * W|0SS = (R th (module) + R th (refrigerator)) * W | 0SS
Daraus ist ableitbar, daß bei vorgegebenen Verlusten und gleichbleibendem Modulaufbau (d.h. Modulwärmewiderstand) zur Begrenzung der Sperrschichttemperatur der Kühlkörperwärmewiderstand hinreichend klein dimensioniert sein muß gemäß:From this it can be deduced that with given losses and constant module structure (i.e. module heat resistance) to limit the junction temperature, the heat sink heat resistance must be dimensioned sufficiently small according to:
Rtt, (Kühlk.) = 1/(αA) (3)Rt t , (refrigerator) = 1 / (αA) (3)
= 125°C / Wioss - Rth(Modul) mit α = therm. Übergangskoeffizient= 125 ° C / Wioss - Rt h (module) with α = thermal transition coefficient
A = KühlkörperoberflächeA = heat sink surface
Bei Vorgabe des thermischen ÜbergangskoeffizientenIf the thermal transition coefficient is specified
• natürliche Konvektion + Strahlung α = 8 - 10 W/m2K forcierte Luftbewegung + Strahlung α = 10 - 35 W/m2K• natural convection + radiation α = 8 - 10 W / m 2 K forced air movement + radiation α = 10 - 35 W / m 2 K
bleibt als Stellgröße nur noch die Oberfläche und damit das Volumen und die Masse des Kühlkörpers. Wenn Kosten, Gewicht und Volumen einer solchen verlustbehafteten Baugruppe gleichzeitig verringert werden sollen, muß der Kühlkörper drastisch verkleinert werden. Das bedeutet eine deutliche Erhöhung seines Wärmewiderstandes und damit eine Anhebung der Sperrschichttemperaturen gemäß Gleichung (2) in den Halbleiterbauelementen über 125°C hinaus. Das führt aber laut Aussage der Hersteller von Halbleiterbauelementen zu einer drastischen Verringerung der Zuverlässigkeit und Lebensdauer der Bauelemente und damit der Module.the only manipulated variable left is the surface and thus the volume and mass of the heat sink. If the cost, weight and volume of such a lossy assembly are to be reduced at the same time, the heat sink must be reduced drastically. This means a significant increase in its thermal resistance and thus an increase in the junction temperatures according to equation (2) in the semiconductor components above 125 ° C. According to the manufacturers of semiconductor components, this leads to a drastic reduction in the reliability and service life of the components and thus of the modules.
Anwender von serienmäßigen Halbleitermodulen halten sich deshalb an die oben dargestellte Kühlkörperdimensionierung.Users of standard semiconductor modules therefore adhere to the heat sink dimensions shown above.
Dabei ist zunächst nicht ganz klar, ob die Festkörpereigenschaften der Silizium- Bauelemente allein oder/und eher deren Verlötung mit dem Moduisubstrat die Drahtbonds sowie die verwendeten Gehäusematerialien die obere Grenztemperatur bestimmen. Laut Literatur stehen bis zu Temperaturen von 175°C vornehmlich diese „Packaging"-Probleme im Vordergrund, während darüber erst der Verlust der Sperrfähigkeit der Silizium-Bauelemente aufgrund des Anstiegs der intrinsischen Ladungsträgerdichte hinzukommt. Bis 150°C oder gar 175°C könnte man Si- Bauelemente noch betreiben, wenn es gelänge, neben den Drahtbonds auch die Lötstellen zuverlässig gegen Temperatur- und Lastwechsel zwischen 0°C und diesen Maximaltemperaturen herzustellen. Das ist mit den angewandten Löttechniken bisher nicht gelungen, weil die ständige thermische Wechselbelastung das Lotgefüge verhärtet und zu Rissbildung und letztlich zum Abriß der Lötstelle führt.It is initially not entirely clear whether the solid-state properties of the silicon components alone or / and rather their soldering to the module substrate determine the wire bonds and the housing materials used determine the upper limit temperature. According to the literature, these are mainly up to temperatures of 175 ° C "Packaging" problems in the foreground, while the loss of the blocking capacity of the silicon components due to the increase in the intrinsic charge density is added. Up to 150 ° C or even 175 ° C, Si components could still be operated, if possible, in addition to the Wire bonds also reliably produce the solder joints against temperature and load changes between 0 ° C and these maximum temperatures, which has so far not been possible with the applied soldering techniques, because the constant thermal alternating loading hardens the solder structure and leads to crack formation and ultimately to the solder joint being torn off.
Stand der Löttechnik am Beispiel der IGBT-Module ist:The state of soldering technology using the example of the IGBT modules is:
• Anwendung von Lötfolienstücken (sog. Preforms) z.B. der Zusammensetzung Pb95Sn5 (flussmittelfrei, Liquidustemperatur 313°C),• Use of solder foil pieces (so-called preforms) e.g. the composition Pb95Sn5 (flux-free, liquidus temperature 313 ° C),
• Verwendung von Lötformen (meist aus Graphit) zur Positionierung der Bauelemente und der Löt-Preforms zueinander,Use of soldering molds (usually made of graphite) to position the components and the soldering preforms relative to one another,
• Reflow-Lötung in einem Wasserstoff-gefluteten Durchlaufofen bei ca. 330°C.• Reflow soldering in a hydrogen-flooded continuous furnace at approx. 330 ° C.
Lote mit Schmelztemperatur >300°C können im Prinzip bis =200°C betrieben werden.In principle, solders with a melting temperature> 300 ° C can be operated up to = 200 ° C.
Selbst wenn es gelingt, Halbleiterbauelemente mit hinreichend zuverlässiger Funktion bei Dauerbetriebstemperaturen oberhalb von 125°C zu finden, kann der Einspareffekt nicht ausgenutzt werden, wenn die Lötstellen nach kurzer Zeit der Wechselbeanspruchung durch Rissbildung und -ausbreitung defekt werden.Even if it is possible to find semiconductor components with a sufficiently reliable function at continuous operating temperatures above 125 ° C, the savings effect cannot be exploited if the solder joints become defective after a short period of alternating stress due to crack formation and propagation.
In der EP 0 476 734 A1 wird vorgeschlagen, eine Dispersion von 5Vol% Partikeln aus den intermetallischen Verbindungen Ni3Sn4 oder Cu9NiSn3 zu verwenden, um Blei-Zinn-Lot zu härten. Allerdings hat sich gezeigt, daß damit keine ausreichende Benetzung der dispergierten Teile mit dem jeweiligen Lot erreicht wird. Außerdem kann eine Verschlechterung des elastischen Dehnungsbereichs des Lots ohne Rissbildung sowie ein ungünstiges Fließ- und Benetzungsverhalten eintreten. In EP 0 110 307 A2 werden metallische Pulver (Ag, Au) in Blei-Zinn-Lote eingemischt, und in JP 09 330 941 A wird ebenfalls die Einmischung von granulärem Metallpulver in Lote beschrieben.In EP 0 476 734 A1 it is proposed to use a dispersion of 5% by volume of particles from the intermetallic compounds Ni3Sn4 or Cu9NiSn3 in order to harden lead-tin solder. However, it has been shown that this does not adequately wet the dispersed parts with the respective solder. In addition, a deterioration in the elastic expansion range of the solder without crack formation and unfavorable flow and wetting behavior can occur. In EP 0 110 307 A2 metallic powders (Ag, Au) are mixed into lead-tin solders, and in JP 09 330 941 A the mixing of granular metal powder into solders is also described.
Die zu lösende Aufgabe besteht darin, ein Lötverfahren anzugeben, das einerseits die übliche Lötqualität bezüglich Benetzung, Porenfreiheit, mechanische Festigkeit und elektrische Leitfähigkeit bietet, und andererseits eine dauerhafte Anwendung danach hergestellter Anordnungen bis zu Sperrschichttemperaturen von 150°C bis 175°C auch unter Temperaturwechselbeanspruchung erlaubt, ohne daß Rissbildung und -ausbreitung auftreten. Außerdem soll eine Anordnung angegeben werden, die im vorgenannten Temperaturbereich arbeiten kann.The task to be solved is to specify a soldering process which, on the one hand, offers the usual soldering quality with regard to wetting, freedom from pores, mechanical strength and electrical conductivity, and, on the other hand, permanent use of the arrangements produced thereafter up to junction temperatures of 150 ° C to 175 ° C, even under thermal cycling allowed without cracking and spreading. In addition, an arrangement is to be specified that can work in the aforementioned temperature range.
Diese Aufgabe wird durch ein Lötverfahren mit den im Anspruch 1 angegebenen Merkmalen gelöst. Vorteilhafte Ausgestaltungen und eine Anordnung sind in weiteren Ansprüchen angegeben.This object is achieved by a soldering process with the features specified in claim 1. Advantageous refinements and an arrangement are specified in further claims.
Mit dem erfindungsgemäßen Verfahren wird vorgeschlagen, kurze Faserstücke durch Verrühren in einem als Paste vorliegenden Lot zu verteilen und durch anschließendes Aufschmelzen im Gefüge einzulagern. Vorzugsweise werden Faserstücke verwendet, die eine mit Pb-reichen Loten besonders gut lötfähige Oberfläche besitzen. Dazu eignet sich Nickel besonders.With the method according to the invention, it is proposed to distribute short pieces of fiber by stirring in a solder present as a paste and to store them in the structure by subsequent melting. Fiber pieces are preferably used which have a surface which is particularly well solderable with Pb-rich solders. Nickel is particularly suitable for this.
Das Verfahren und damit hergestellte Produkte weisen eine Reihe von Vorteilen auf:The process and the products it produces have a number of advantages:
• Fasern eignen sich besonders für die Erhöhung der Elastizität.• Fibers are particularly suitable for increasing elasticity.
• Es können weiterhin kommerzielle bleireiche Lote verwendet werden, sofern sie in Pastenform erhältlich sind (keine Sonderanfertigung);• Commercial lead-rich solders can continue to be used, provided they are available in paste form (not custom-made);
• Die Lote können nach der Einmischung des Feststoffes nach wie vor mit einem Siebdruckverfahren auf die Lötflächen der Substrate oder Leiterplatten aufgetragen werden;• After the solid has been mixed in, the solders can still be applied to the soldering surfaces of the substrates or printed circuit boards using a screen printing process;
• Die Lote können trotz ihres Fremdstoffgehalts mit den gleichen Reflowverfahren mit (möglicherweise unwesentlich zu modifizierenden) Temperaturprofilen aufgeschmolzen werden. • Durch geeignete Wahl des Fasermaterials, speziell Nickel, oder Beschichtung mit Nickel wird eine gute Benetzung der einzelnen Fasern und damit eine stoffschlüssige Einlagerung in das Lotgefüge sichergestellt;• In spite of their foreign matter content, the solders can be melted using the same reflow methods with temperature profiles (which may need to be modified slightly). • A suitable choice of the fiber material, especially nickel, or coating with nickel ensures good wetting of the individual fibers and thus a cohesive incorporation into the solder structure;
• Bei Verwendung von Nickel als Fremdstoff wird der gesamte Zinngehalt des Lotes nach langer Zeit an der Partikeloberfläche in N.3Sn4 umgesetzt. Damit wird die Versprödung der Lot/Substrat-Grenzfläche verhindert.• If nickel is used as a foreign substance, the entire tin content of the solder is converted into N. 3 Sn4 after a long time on the particle surface. This prevents embrittlement of the solder / substrate interface.
• Durch Variation der Parameter „Fremdstoffmaterial" oder „Fremdstoffanteil in Vol% oder Gew%", „Faserlänge", „Korn- oder Faserdurchmesser", „Beschich- tungsmaterial", „Beschichtungsdicke" sind so viele Optimierungsmöglichkeiten gegeben, daß für alle Lotpasten und Anwendungsfälle die geeignete Werkstoffkombination ermittelt werden kann;• By varying the parameters "foreign matter material" or "foreign matter content in% or weight%", "fiber length", "grain or fiber diameter", "coating material", "coating thickness" there are so many optimization options that for all solder pastes and Use cases the suitable material combination can be determined;
• Durch Verwendung von Fasern wird außer der Behinderung von Kornwachstum und Rissausbreitung noch eine erhebliche Vergrößerung der Elastizität und Bruchdehnung erreicht;• By using fibers, in addition to preventing grain growth and crack propagation, a considerable increase in elasticity and elongation at break is achieved;
• Wenn beispielsweise durch Verbesserung der mechanischen Eigenschaften der Lötstellen bei gleichbleibender Zuverlässigkeit der Bauelementfunktion die Sperrschichttemperatur der aufgelöteten Halbleiterbauelemente von 125°C auf z.B. 155°C erhöht werden kann, dann könnte die Oberflächentemperatur des Kühlkörpers um den gleichen Betrag (hier 30K) von (typisch) 85°C auf 115°C erhöht werden. Damit würde die Temperaturdifferenz zwischen Kühlkörperoberfläche und maximaler Umgebungstemperatur von 55°C von 30K auf 60K verdoppelt und somit eine Reduktion der Oberfläche, des Volumens, des Gewichts und der Kosten des Kühlkörpers um etwa einen Faktor 0,5 erreicht werden.If, for example, by improving the mechanical properties of the solder joints while maintaining the reliability of the component function, the junction temperature of the soldered semiconductor components from 125 ° C to e.g. 155 ° C, the surface temperature of the heat sink could be increased by the same amount (here 30K) from (typically) 85 ° C to 115 ° C. This would double the temperature difference between the heat sink surface and the maximum ambient temperature of 55 ° C from 30K to 60K, thus reducing the surface area, volume, weight and cost of the heat sink by a factor of 0.5.
Zur weiteren Erläuterung der Erfindung werden nachstehend Ausführungs- und Anwendungsbeispiele anhand von Zeichnungsfiguren für Faserverstärkung beschrieben.To further explain the invention, exemplary embodiments and application examples are described below with reference to drawing figures for fiber reinforcement.
Es zeigen:Show it:
Fig. 1 eine Lötstelle mit einem faserverstärkten Lot,1 shows a solder joint with a fiber-reinforced solder,
Fig. 2 eine typische Anordnung eines metallisierten Subtrats mit aufgelöteten Bauelemente, undFig. 2 shows a typical arrangement of a metallized substrate with soldered components, and
Fig. 3 eine Darstellung der praktischen Auswirkung der Verwendung eines faserverstärkten Lots. Fig. 1 zeigt auf der linken Bildseite eine Lötstelle, wobei eine Metallisierung 1 eines nicht dargestellten Substrats gezeigt ist, auf das ein Bauelement 3 mittels eines faserverstärkten Lots 2 verlötet ist. Auf der rechten Bildseite der Fig. 1 ist das Lot 2 schematisiert und vergrößert dargestellt. Es ist ersichtlich, daß in ein pastenförmiges Lot 5 Faserstücke 4 eingebettet sind. Die Faserstücke 4 sind mit einer gut benetzenden Oberflächenbeschichtung aus Nickel 6 versehen, oder sie bestehen vollständig aus Nickel.Fig. 3 illustrates the practical impact of using a fiber-reinforced solder. 1 shows a solder joint on the left-hand side of the image, a metallization 1 of a substrate, not shown, to which a component 3 is soldered by means of a fiber-reinforced solder 2 being shown. On the right-hand side of FIG. 1, the solder 2 is shown schematically and enlarged. It can be seen that 5 pieces of fiber 4 are embedded in a pasty solder. The fiber pieces 4 are provided with a well-wetting surface coating of nickel 6, or they consist entirely of nickel.
Fig. 2 zeigt in einer schematisierten Darstellung eine Anordnung mit einem Substrat 7, z.B. einem Keramiksubstrat aus Al203 oder AIN, das auf seiner Ober- und Unterseite Metallisierungen 1 aufweist. Es versteht sich, daß auch andere Substrate, wie z.B. DCB-Substrate geeignet sind. Auf Metallisierungen 1 sind Halbleiterchips 9, wie z.B. Silizium-IGBTs, Silizium-MOSFETs, Silizium-Dioden, Siliziumkarbid-Dioden oder SiC-Transistoren aufgelötet. Die Halbleiterchips 9 sind mittels einem faserverstärkten Lot 2 auf Metallisierungen 1 aufgelötet. Elektroden der Chips 9 sind mittels Drahtbonds 8, z.B. aus Aluminium mit weiteren Metallisierungen 1 verbunden.2 shows a schematic representation of an arrangement with a substrate 7, for example a ceramic substrate made of Al 2 O 3 or AIN, which has metallizations 1 on its top and bottom. It goes without saying that other substrates, such as, for example, DCB substrates, are also suitable. Semiconductor chips 9, such as silicon IGBTs, silicon MOSFETs, silicon diodes, silicon carbide diodes or SiC transistors, are soldered onto metallizations 1. The semiconductor chips 9 are soldered onto metallizations 1 by means of a fiber-reinforced solder 2. Electrodes of the chips 9 are connected to further metallizations 1 by means of wire bonds 8, for example made of aluminum.
Fig. 3 zeigt anhand einer Gegenüberstellung einer auf der linken Seite dargestellten konventionellen Anordnung und einer auf der rechten Seite dargestellten erfindungsgemäßen Anordnung, welche Effekte erzielbar sind. Es ist dabei jeweils ein mit Finnen versehener Aluminium-Kühlkörper 10 dargestellt, auf den eine beispielsweise in Fig. 2 gezeigte Anordnung gut wärmeleitend aufgebracht ist. Es wird dabei eine im Halbleiterchip 9 erzeugt Verlustwärme W|0SS zum Kühlkörper 10 hin abgeführt.FIG. 3 shows which effects can be achieved by comparing a conventional arrangement shown on the left and an arrangement according to the invention shown on the right. In each case, an aluminum heat sink 10 provided with fins is shown, to which an arrangement shown, for example, in FIG. 2 is applied with good thermal conductivity. A heat loss W | generated in the semiconductor chip 9 is thereby generated 0SS dissipated to the heat sink 10.
Im dargestellten Beispiel wird bei der konventionellen Anordnung eine Sperrschichttemperatur Tji = 125°C zugelassen, bei der erfindungsgemäßen Anordnung eine Sperrschichttemperatur Tj2 = 155°C; und zwar dauerhaft und auch bei wechselnder Temperatur, z.B. bedingt durch wechselnde Umgebungstemperatur oder Lastwechsel.In the example shown, a junction temperature Tji = 125 ° C. is permitted in the conventional arrangement, and a junction temperature Tj 2 = 155 ° C. in the arrangement according to the invention; and that permanently and also at changing temperatures, for example due to changing ambient temperatures or load changes.
Da die Sperrschichttemperatur bei der erfindungsgemäßen Anordnung höher sein darf, genügt eine kleinere Kühlkörperoberfläche. Anstelle von Bauelementen und Substraten können unter Verwendung des faserverstärkten Lots auch andere Teile, z.B. metallische Gehäuseteile verlötet werden. Since the junction temperature may be higher in the arrangement according to the invention, a smaller heat sink surface is sufficient. Instead of components and substrates, other parts, for example metallic housing parts, can also be soldered using the fiber-reinforced solder.

Claims

Patentansprüche claims
1. Verfahren zum Auflöten von ungekapselten Halbleiterchips (9) oder gekapselten Halbleiterbauelementen oder anderen elektronischen Bauelementen mittels Weichlot auf metallisierte Oberflächen (1 ) von Keramiksubstraten (7) oder von Leiterplatten oder zum Verlöten von metallischen Gehäuseteilen, wobei a) ein Lotmaterial (5) in pastöser Form bereitgestellt und mit Faserabschnitten als Fremdstoff (4) zu einem weichen Lotpastenmaterial (2) vermischt wird, wobei der Volumenprozentsatz des Faserabschnittes (4) etwa 1 bis 10 Volumenprozent beträgt, b) das so mit Fasern vermischte Lotpastenmaterial (2) mittels eines geeigneten Verfahrens, wie Siebdruckverfahren oder mittels Dispenser auf die zu verlötenden Flächen wenigstens eines der Fügepartner (1 , 3) aufgetragen wird, c) auf die mit noch weichem Lotpastenmaterial (2) beschichteten Flächen (1 ) zu verbindende Teile (3) aufgesetzt werden, und d) die positionierten Teile (3) in einem Reflowofen in einer geeigneten Gasatmosphäre einem geeigneten Temperaturzyklus unterzogen werden, der zum Aufschmelzen und Fließen des Lotpastenmaterials (2) unter gleichzeitiger Einlagerung der Faserabschnitte (4) führt.1. A method for soldering unencapsulated semiconductor chips (9) or encapsulated semiconductor components or other electronic components by means of soft solder on metallized surfaces (1) of ceramic substrates (7) or of printed circuit boards or for soldering metallic housing parts, with a) a solder material (5) in provided pasty form and mixed with fiber sections as foreign matter (4) to form a soft solder paste material (2), the volume percentage of the fiber section (4) being about 1 to 10 volume percent, b) the solder paste material (2) mixed with fibers by means of a suitable Method, such as a screen printing method or by means of a dispenser, at least one of the joining partners (1, 3) is applied to the surfaces to be soldered, c) are placed on the parts (3) to be connected, which are coated with still soft solder paste material (2), and d) the positioned parts (3) in a reflow oven in a suitable gas atmosphere be subjected to a suitable temperature cycle which leads to the melting and flowing of the solder paste material (2) with simultaneous incorporation of the fiber sections (4).
2. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, daß die Faserabschnitte (4) aus Nickel bestehen oder aber aus Nickel-beschichteten Kohlenstoff, Aramid, Bor, Glasfiber oder Quarz bestehen.2. The method according to claim 1, characterized in that the fiber sections (4) consist of nickel or consist of nickel-coated carbon, aramid, boron, glass fiber or quartz.
3. Verfahren nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß der Faserdurchmesser im Bereich 5 μm bis 50 μm liegt und die Länge der Faserabschnitte (4) im Bereich von etwa 0,1 mm bis 1 mm liegt.3. The method according to any one of the preceding claims, characterized in that the fiber diameter is in the range 5 microns to 50 microns and the length of the fiber sections (4) is in the range of about 0.1 mm to 1 mm.
4. Anordnung eines mit metallisierten Oberflächen (1 ) versehenen Substrats (7), auf das mittels Weichlöten Bauelemente (3, 9) aufgebracht sind, wobei das verwendete Lotmaterial (2) eingelagerte Faserabschnitte (4) enthält.4. Arrangement of a substrate (7) provided with metallized surfaces (1) onto which components (3, 9) are applied by means of soft soldering, the used solder material (2) contains embedded fiber sections (4).
5. Anordnung nach Anspruch 4, dadurch gekennzeichnet, daß der Volumenanteil der Fasern (4) 1 bis 10 Volumenprozent beträgt.5. Arrangement according to claim 4, characterized in that the volume fraction of the fibers (4) is 1 to 10 volume percent.
6. Anordnung nach Anspruch 4 oder 5, dadurch gekennzeichnet, daß die Faserabschnitte (4) aus Nickel oder Nickel-beschichteten nichtmetallischen Stoffen bestehen.6. Arrangement according to claim 4 or 5, characterized in that the fiber sections (4) consist of nickel or nickel-coated non-metallic substances.
7. Anordnung nach einem der Ansprüche 4 bis 6, dadurch gekennzeichnet, daß der Faserdurchmesser zwischen 5 μm und 50 μm liegt, bzw. die Länge der Faserabschnitte (4) etwa 0,1 mm bis 1 mm beträgt. 7. Arrangement according to one of claims 4 to 6, characterized in that the fiber diameter is between 5 microns and 50 microns, or the length of the fiber sections (4) is about 0.1 mm to 1 mm.
PCT/EP2000/009235 1999-10-06 2000-09-21 Method for soft soldering of components and a soft soldered device WO2001024967A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU75217/00A AU7521700A (en) 1999-10-06 2000-09-21 Method for soft soldering of components and a soft soldered device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19947914A DE19947914A1 (en) 1999-10-06 1999-10-06 Method of soft soldering components and soft soldered assembly
DE19947914.3 1999-10-06

Publications (1)

Publication Number Publication Date
WO2001024967A1 true WO2001024967A1 (en) 2001-04-12

Family

ID=7924543

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2000/009235 WO2001024967A1 (en) 1999-10-06 2000-09-21 Method for soft soldering of components and a soft soldered device

Country Status (3)

Country Link
AU (1) AU7521700A (en)
DE (1) DE19947914A1 (en)
WO (1) WO2001024967A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10204960A1 (en) * 2002-02-06 2003-08-14 Endress & Hauser Gmbh & Co Kg Solder and solder connection
DE102006039339A1 (en) * 2006-08-24 2008-03-06 Bayerische Motoren Werke Ag Hard solder joining components in solid oxide fuel cells used e.g. in electric vehicles, contains ceramic particles, fibers or intermediate layer with reduced coefficient of thermal expansion

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0164906A1 (en) * 1984-05-14 1985-12-18 RAYCHEM CORPORATION (a Delaware corporation) Solder composition
US5008998A (en) * 1988-12-05 1991-04-23 Sony Corporation Method of mounting flat coil
US5056706A (en) * 1989-11-20 1991-10-15 Microelectronics And Computer Technology Corporation Liquid metal paste for thermal and electrical connections
US5089356A (en) * 1990-09-17 1992-02-18 The Research Foundation Of State Univ. Of New York Carbon fiber reinforced tin-lead alloy as a low thermal expansion solder preform
US5127969A (en) * 1990-03-22 1992-07-07 University Of Cincinnati Reinforced solder, brazing and welding compositions and methods for preparation thereof
USH1306H (en) * 1993-01-21 1994-05-03 The United States Of America As Represented By The Secretary Of The Army Method of using an improved solder to bridge a nonmetallic gap between metallic surfaces, said improved solder, and an improved solder connection to bridge a nonmetallic gap between metallic surfaces

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3467765A (en) * 1965-10-04 1969-09-16 Contemporary Research Inc Solder composition
US4219448A (en) * 1978-06-08 1980-08-26 Bernd Ross Screenable contact structure and method for semiconductor devices
US4487638A (en) * 1982-11-24 1984-12-11 Burroughs Corporation Semiconductor die-attach technique and composition therefor
FR2555188B1 (en) * 1983-11-18 1986-10-31 Electricite De France METHOD FOR MANUFACTURING A COMPOSITE MATERIAL COMPRISING A CROSSLINKED POLYMERIC MATRIX AND FINELY DIVIDED ELECTRICALLY CONDUCTIVE CHARGES
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system
DE3924225C2 (en) * 1988-07-22 1994-01-27 Mitsubishi Electric Corp Method for producing a ceramic-metal composite substrate and ceramic-metal composite substrate
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
US5066544A (en) * 1990-08-27 1991-11-19 U.S. Philips Corporation Dispersion strengthened lead-tin alloy solder
JP2730357B2 (en) * 1991-11-18 1998-03-25 松下電器産業株式会社 Electronic component mounted connector and method of manufacturing the same
JPH06232188A (en) * 1993-01-29 1994-08-19 Nec Corp Manufacture of solder material

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0164906A1 (en) * 1984-05-14 1985-12-18 RAYCHEM CORPORATION (a Delaware corporation) Solder composition
US5008998A (en) * 1988-12-05 1991-04-23 Sony Corporation Method of mounting flat coil
US5056706A (en) * 1989-11-20 1991-10-15 Microelectronics And Computer Technology Corporation Liquid metal paste for thermal and electrical connections
US5127969A (en) * 1990-03-22 1992-07-07 University Of Cincinnati Reinforced solder, brazing and welding compositions and methods for preparation thereof
US5089356A (en) * 1990-09-17 1992-02-18 The Research Foundation Of State Univ. Of New York Carbon fiber reinforced tin-lead alloy as a low thermal expansion solder preform
USH1306H (en) * 1993-01-21 1994-05-03 The United States Of America As Represented By The Secretary Of The Army Method of using an improved solder to bridge a nonmetallic gap between metallic surfaces, said improved solder, and an improved solder connection to bridge a nonmetallic gap between metallic surfaces

Also Published As

Publication number Publication date
DE19947914A1 (en) 2001-04-12
AU7521700A (en) 2001-05-10

Similar Documents

Publication Publication Date Title
DE60034418T2 (en) Use of a soldering material and method of making an electrical or electronic device
DE102005008491B4 (en) Power semiconductor device and method for its manufacture
DE112009005537B3 (en) Method of manufacturing a semiconductor device
DE112015006049T5 (en) SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT
DE102007019523B4 (en) Semiconductor power module
US20080272180A1 (en) Method of manufacturing heat spreader module
DE4110373C2 (en) Electronic circuitry and method of making the same
DE69824522T2 (en) Conductive paste with high thermal conductivity and electronic parts containing them
DE102016206542B4 (en) Method of manufacturing a semiconductor device
DE69736144T2 (en) Part for aluminum nitride substrate material semiconductors and its manufacturing method
DE102006002452A1 (en) Semiconductor device and method for its production
EP0931346A1 (en) Microelectronic component with a sandwich design
DE112017000184T5 (en) solder
DE112016000614T5 (en) Solder material for semiconductor elements
DE102009026480A1 (en) Module with a sintered joint
DE102017004626A1 (en) Lead-free solder foil for diffusion soldering
DE102011013172A1 (en) Paste for joining components of electronic power modules, system and method for applying the paste
DE112016007464B4 (en) Semiconductor device
EP3698400A1 (en) Heat sink for an electronic component, electronic subassembly with a heat sink of this kind and method for producing a heat sink of this kind
EP0535414A2 (en) Electronic circuit device
DE102008011265B4 (en) Method for producing a substrate for bonding devices with a solder layer
DE102015114521A1 (en) Method for soldering an insulating substrate onto a carrier
DE102018115509A1 (en) Heat dissipation device, semiconductor packaging system and method of manufacturing the same
DE102011076774A1 (en) Semiconductor component for use in e.g. power electronic area, has solderable layers formed at surfaces of carrier and cooling body, respectively, where surfaces of carrier and body face body and carrier, respectively
WO2001024967A1 (en) Method for soft soldering of components and a soft soldered device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP