WO2001024014A1 - Systeme d'ordinateur integre et procede avec une interface de memoire flash - Google Patents

Systeme d'ordinateur integre et procede avec une interface de memoire flash Download PDF

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Publication number
WO2001024014A1
WO2001024014A1 PCT/US2000/025430 US0025430W WO0124014A1 WO 2001024014 A1 WO2001024014 A1 WO 2001024014A1 US 0025430 W US0025430 W US 0025430W WO 0124014 A1 WO0124014 A1 WO 0124014A1
Authority
WO
WIPO (PCT)
Prior art keywords
flash memory
disk drive
drive interface
interface
bios update
Prior art date
Application number
PCT/US2000/025430
Other languages
English (en)
Inventor
Raymond Brinks
Kaido Kevvai
Andrus Aaslaid
Jüri-Henrik PÕLDRE
Gustav Poola
Original Assignee
Zf Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zf Micro Devices, Inc. filed Critical Zf Micro Devices, Inc.
Publication of WO2001024014A1 publication Critical patent/WO2001024014A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4406—Loading of operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Definitions

  • This invention pertains generally to embedded computer systems and, more particularly, to an interface and method for connecting a flash memory to a central processing unit (CPU) in an embedded system.
  • CPU central processing unit
  • U.S. Patent 5,742,844 discloses an embedded computer module in a package the size of an integrated circuit, with the functionality of a desktop computer.
  • the module includes an Intel X86 processor, serial and parallel interfaces, drive controllers, a keyboard interface, a DRAM interface and flash memory.
  • a more recently developed system includes a complete processor and peripheral subsystem on a single chip, with the only external components being a clock, SDRAM and a flash memory containing system start-up code (BIOS) and/or application software.
  • the start-up code can be loaded into the flash memory either from an external source, or from information stored on the chip itself. Loading the start-up code from the chip can be a problem if all of the external peripheral interfaces of the system are otherwise allocated.
  • a central processing unit a disk drive interface, a BIOS update memory are all included in a single chip package, a flash memory containing system startup information is located externally of the chip and connected to system via the disk drive interface.
  • Data can be transferred from the BIOS update memory to the flash memory via the disk drive interface, and the system can be booted either from the BIOS update memory or from the flash memory.
  • Figure 1 is a block diagram of one embodiment of an embedded computer system with a flash memory interface incorporating the invention.
  • Figure 2 is an ideal data transfer timing diagram for a connector interface according to the invention.
  • Figure 3 is a data transfer timing diagram for a connector interface according to the invention when the source device speed is unknown.
  • FIG. 4 is a diagram of one embodiment of an interface access chipset register for use in the invention.
  • the embedded computer system illustrated in Figure 1 is constructed on a single chip 10 packaged in a 35 mm, 388 pin ball grid array (not shown).
  • the system includes a processor core 1 1 which in one embodiment comprises a standard X86 processor (e.g., Intel 386) with an integrated floating point co-processor and 8K bytes of write-back level 1 cache.
  • the system also includes a north bridge system controller 12 with a frontside PCI interface and an SDRAM interface, and a south bridge controller 13 having a frontside PCI interface to the north bridge controller and a backside PCI system interface.
  • the south bridge controller also has an enhanced ICE controller which supports two devices on a single channel, a USB controller with two hub ports, a real time clock, a floppy disk controller, serial ports, an access bus, a keyboard and mouse controller, a parallel port, general purpose programmable l/O's and counters, PC/AT system components, and power management.
  • the PC/AT system components include DMA controllers, interrupt controllers, a system timer, and an ISA bus interface.
  • a logic module 14 is connected internally to the ISA bus and uses external pads on the chip to control external devices.
  • This module includes general purpose and specific chip selects, a watchdog timer, and a flash controller.
  • a BIOS update ROM (BUR) 16 on the chip contains the minimal necessary code to read data into the chip and to update an externally connected flash memory device 17.
  • the connection between the chip and the flash memory device can be made either via a serial port or via a connection interface which is described hereinafter in detail.
  • the serial connection utilizes a standard UART1 embedded in the chip, and allows a remote PC with special host software or to access the flash device to do the update. This approach can be used only in applications where the serial port is not hardwired to an external device and where access to the serial port is physically possible.
  • connection interface utilizes a multiplexer 18 and the pins of the floppy disk drive (FDD) interface and appears when the FDD select signal is not active.
  • the communication protocol is compatible with standard serial EEPROM devices, thus allowing the serial EEPROM to be connected directly to the interface as a source media. ln the presently preferred embodiment, the interface connector has the following pinout configuration:
  • CLK, RST and DATA signals are asychronous serial interface signals used in EEPROM's. The use of these signals is illustrated in the timing diagram of Figure 2.
  • the ACK signal is a loopback from the CLK signal and is useful in situations where the source media response speed is unknown (i.e., emulation through a PC parallel interface).
  • the ACK signal can be either the CLK signal if the source media speed is considered to be faster than the chip clocking (i.e., the data bit will be set fast enough after the CLK rising edge appears) or specially created after the data bit is set by the source media.
  • LED1 and LED2 are general purpose output bits that are used to provide progress or status information when the BIOS update ROM is updating the flash memory.
  • JP1 is a 5 volt tolerant jumper input that enables the internal BIOS update ROM when connected to GND.
  • RST S is tied to the chip master reset input and is used during manufacturing to create system resets when multiple flash programming cycles or different test applications are necessary within one testing phase, most likely with different flash images.
  • Vcc and GND are connected to the digital power source for the chip.
  • Data transfer is accomplished in accordance with the timing diagram shown in Figure 2.
  • Data bit latching must occur at a rising edge of the CLK signal.
  • the source device sets the ACK signal when it has received the CLK edge and latched the data to the
  • the target then reads a bit and resets the CLK signal. After that, the target starts reading the ACK signal again and waiting for it to become low. When ACK becomes low, the cycle will be repeated for the next data bit.
  • the bit stream following the reset deactivation is a continuous 8-bit character bit stream with no control bits, byte separators or addressing information, and the software implements a packet header for determining the addressing and other control information.
  • the connector interface access is done via an 8-bit logic register which is illustrated in Figure 4.
  • the ACK, LED2, LED1 , DATA, RST and CLOCK bits serve the functions discussed above.
  • the JP1 bit is latched in accordance with an external pull-down jumper and represents the JP1 position at startup. When written, it will enable the connector interface signals on the FDD pins when the drive select bit is high, or unconditionally disable the connector interface signals on the FDD pins when the drive select bit is low. Writing this bit does not affect the logic flash chip selects or the appearance of the BIOS update ROM in the system memory space.
  • Operation and use of the connector interface, and therein the method of the invention, is as follows.
  • JP1 On normal boot, JP1 is not connected to GND, and the chip boots from the flash memory.
  • the system boots from the BIOS update ROM.
  • the BIOS update ROM programs the flash memory, using data from the connector interface or the UART interface.
  • the connector interface is used to update ROM devices in the BIOS update mode.
  • the FDD interface signals are connected to the data register in the connector interface when TRRO and DRVO are not asserted, and the FDD multiplexer is controlled with the bit in the interface register. The process is transparent to the user.
  • the data register has four input bits and four output bits, with each interface line being connected to one of the FDD lines as illustrated in the following table:
  • the interface control register multiplexes the FDD lines to the interface data register in accordance with the following table:
  • the FDD WGATE, MTRO and DRVO signals are set to a logical "1 " to insure that the FDD does not interfere with the interface data.
  • the host computer is connected to the serial port on the chip, and the update is done with software on that computer.
  • the invention has a number of important features and advantages. It is useful not only when the BIOS needs to be upgraded, but also when the entire flash memory needs to be written.
  • the update can be done without special cables or external host computers in the field. In automated manufacturing tests, several flash memory reprogrammings can be done with test software without human interaction.

Abstract

L'invention concerne un système d'ordinateur intégré et un procédé. Dans ce système une unité de traitement centrale (11), une interface de lecteur de disque, une mémoire de mise à jour du système BIOS (16) sont placés dans un seul boîtier de circuits intégrés (10), une mémoire flash (17) contenant des informations de mise en route du système est placée à l'extérieur de la puce et connectée au système via l'interface d'unité de disque. Les données peuvent être transférées à partir de la mémoire de mise à jour du système BIOS (16) à la mémoire flash (17) via l'interface d'unité de disque. Ce système peut être initialisé à partir de la mémoire de mise à jour du système BIOS (16) ou à partir de la mémoire flash (17).
PCT/US2000/025430 1999-09-27 2000-09-14 Systeme d'ordinateur integre et procede avec une interface de memoire flash WO2001024014A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40504599A 1999-09-27 1999-09-27
US09/405,045 1999-09-27

Publications (1)

Publication Number Publication Date
WO2001024014A1 true WO2001024014A1 (fr) 2001-04-05

Family

ID=23602068

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/025430 WO2001024014A1 (fr) 1999-09-27 2000-09-14 Systeme d'ordinateur integre et procede avec une interface de memoire flash

Country Status (1)

Country Link
WO (1) WO2001024014A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6701403B2 (en) 2001-10-01 2004-03-02 International Business Machines Corporation Service processor access of non-volatile memory
WO2004025484A1 (fr) * 2002-09-16 2004-03-25 Patrick Cameron Systeme de fixation de dispositif ata
CN100351797C (zh) * 2003-08-19 2007-11-28 华为技术有限公司 一种单片机在线升级方法和装置
CN100442228C (zh) * 2006-11-17 2008-12-10 迈普（四川）通信技术有限公司 嵌入式设备引导方法
TWI463310B (zh) * 2009-07-28 2014-12-01 Mediatek Inc 嵌入式系統及其管理方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537627A (en) * 1993-09-08 1996-07-16 Hilevel Technology, Inc. Microprogrammable processor capable of accessing unused portions of control store as fast data memory
US5734816A (en) * 1993-03-11 1998-03-31 International Business Machines Corporation Nonvolatile memory with flash erase capability
US6038663A (en) * 1995-11-29 2000-03-14 Zf Microsystems, Inc. IBM PC compatible multi-chip module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734816A (en) * 1993-03-11 1998-03-31 International Business Machines Corporation Nonvolatile memory with flash erase capability
US5537627A (en) * 1993-09-08 1996-07-16 Hilevel Technology, Inc. Microprogrammable processor capable of accessing unused portions of control store as fast data memory
US6038663A (en) * 1995-11-29 2000-03-14 Zf Microsystems, Inc. IBM PC compatible multi-chip module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6701403B2 (en) 2001-10-01 2004-03-02 International Business Machines Corporation Service processor access of non-volatile memory
WO2004025484A1 (fr) * 2002-09-16 2004-03-25 Patrick Cameron Systeme de fixation de dispositif ata
CN100351797C (zh) * 2003-08-19 2007-11-28 华为技术有限公司 一种单片机在线升级方法和装置
CN100442228C (zh) * 2006-11-17 2008-12-10 迈普（四川）通信技术有限公司 嵌入式设备引导方法
TWI463310B (zh) * 2009-07-28 2014-12-01 Mediatek Inc 嵌入式系統及其管理方法

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