WO2001022250A3 - Plurality of memory busses arranged in a multiprocessor system - Google Patents

Plurality of memory busses arranged in a multiprocessor system Download PDF

Info

Publication number
WO2001022250A3
WO2001022250A3 PCT/DE2000/003298 DE0003298W WO0122250A3 WO 2001022250 A3 WO2001022250 A3 WO 2001022250A3 DE 0003298 W DE0003298 W DE 0003298W WO 0122250 A3 WO0122250 A3 WO 0122250A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
multiprocessor system
memory busses
central
memory
Prior art date
Application number
PCT/DE2000/003298
Other languages
German (de)
French (fr)
Other versions
WO2001022250A2 (en
Inventor
Franz Hechfellner
Horst Kuske
Original Assignee
Siemens Ag
Franz Hechfellner
Horst Kuske
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Franz Hechfellner, Horst Kuske filed Critical Siemens Ag
Priority to EP00975783A priority Critical patent/EP1214664A2/en
Publication of WO2001022250A2 publication Critical patent/WO2001022250A2/en
Publication of WO2001022250A3 publication Critical patent/WO2001022250A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

The invention relates to a data processing device for inputting, outputting, storing and processing data. The inventive device comprises a first and a second central unit (1a, 1b) for processing the data, a central working memory (3) for storing the data, a first memory bus (2a) for transmitting data between the central working memory (3) and the first central unit (1a), and a second memory bus (2b) for transmitting data between the central working memory (3) and the second central unit (1b).
PCT/DE2000/003298 1999-09-21 2000-09-21 Plurality of memory busses arranged in a multiprocessor system WO2001022250A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00975783A EP1214664A2 (en) 1999-09-21 2000-09-21 Plurality of memory busses arranged in a multiprocessor system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19945142 1999-09-21
DE19945142.7 1999-09-21

Publications (2)

Publication Number Publication Date
WO2001022250A2 WO2001022250A2 (en) 2001-03-29
WO2001022250A3 true WO2001022250A3 (en) 2002-03-21

Family

ID=7922726

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/003298 WO2001022250A2 (en) 1999-09-21 2000-09-21 Plurality of memory busses arranged in a multiprocessor system

Country Status (2)

Country Link
EP (1) EP1214664A2 (en)
WO (1) WO2001022250A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175841A (en) * 1987-03-13 1992-12-29 Texas Instruments Incorporated Data processing device with multiple on-chip memory buses
US5860120A (en) * 1996-12-09 1999-01-12 Intel Corporation Directory-based coherency system using two bits to maintain coherency on a dual ported memory system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175841A (en) * 1987-03-13 1992-12-29 Texas Instruments Incorporated Data processing device with multiple on-chip memory buses
US5860120A (en) * 1996-12-09 1999-01-12 Intel Corporation Directory-based coherency system using two bits to maintain coherency on a dual ported memory system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LIBERMAN S ET AL: "THE MOTOROLA DSP96002 IEEE FLOATING POINT DIGITAL SIGNAL PROCESSOR", PROCEEDINGS OF THE CONFERENCE OF ELECTRICAL AND ELECTRONICS ENGINEERS IN ISRAEL. TEL AVIV, MAR. 7 - 9, 1989, NEW YORK, IEEE, US, vol. CONF. 16, 7 March 1989 (1989-03-07), pages 1 - 3, XP000077635 *
SHIN-ICHI NAKAGAWA ET AL: "A 24-B 50-NS DIGITAL IMAGE SIGNAL PROCESSOR", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 25, no. 6, 1 December 1990 (1990-12-01), pages 1484 - 1492, XP000176579, ISSN: 0018-9200 *

Also Published As

Publication number Publication date
WO2001022250A2 (en) 2001-03-29
EP1214664A2 (en) 2002-06-19

Similar Documents

Publication Publication Date Title
EP0614143A3 (en) Data processing system with power-fail protected memory module.
EP0603801A3 (en) Generalized shared memory in a cluster architecture for a computer system.
GB2345170A (en) Memory transactions on a low pin count bus
TW331637B (en) Semiconductor memory device, semiconductor device, data processing device and computer system
HUP0104536A3 (en) Interrupt architecture for a non-uniform memory access (numa) data processing system
GB2328045B (en) Data processing system diagnostics
SG91873A1 (en) Interconnected procesing nodes configurable as at least one non-uniform memory access (numa) data processing system
IL134870A0 (en) Device for processing data transfers in a computer system
AU5159900A (en) Memory management in distributed computer system
EP0811451A3 (en) Integrated control system for a work robot
CA2280125A1 (en) Non-uniform memory access (numa) data processing system that speculatively issues requests on a node interconnect
HK1028459A1 (en) Direct memory access (dma) transactions on a low pin count bus.
AU2003246991A1 (en) Improved inter-processor communication system for communication between processors
EP0388300A3 (en) Controller for direct memory access
WO2000013185A3 (en) Memory system
EP0902367A3 (en) Data processing unit with debug capabilities
HK1024067A1 (en) Data processing system.
ZA973613B (en) Data processing system.
CA2385079A1 (en) Parallel computer architecture, and information processing unit using the architecture
DE59709682D1 (en) Swiveling decentralized input / output module for a data bus
IL131031A0 (en) Non-uniform memory access (numa) data processing
DE69406922D1 (en) EXTENDABLE, DIVIDIBLE DATA PROCESSING SYSTEM AT LOW COST COST
UA73002C2 (en) Smart card
EP0881644A3 (en) Semiconductor memory device with multibank configuration
WO2001022250A3 (en) Plurality of memory busses arranged in a multiprocessor system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2000975783

Country of ref document: EP

AK Designated states

Kind code of ref document: A3

Designated state(s): CN US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWP Wipo information: published in national office

Ref document number: 2000975783

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2000975783

Country of ref document: EP