WO2001016738A3 - Efficient page ownership control - Google Patents

Efficient page ownership control Download PDF

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Publication number
WO2001016738A3
WO2001016738A3 PCT/US2000/024150 US0024150W WO0116738A3 WO 2001016738 A3 WO2001016738 A3 WO 2001016738A3 US 0024150 W US0024150 W US 0024150W WO 0116738 A3 WO0116738 A3 WO 0116738A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory page
ownership
control
systems
page
Prior art date
Application number
PCT/US2000/024150
Other languages
French (fr)
Other versions
WO2001016738A2 (en
WO2001016738A8 (en
WO2001016738A9 (en
Inventor
Karlon K West
Chris Miller
Original Assignee
Times N Systems Inc
Karlon K West
Chris Miller
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Times N Systems Inc, Karlon K West, Chris Miller filed Critical Times N Systems Inc
Priority to AU69496/00A priority Critical patent/AU6949600A/en
Publication of WO2001016738A2 publication Critical patent/WO2001016738A2/en
Publication of WO2001016738A8 publication Critical patent/WO2001016738A8/en
Publication of WO2001016738A3 publication Critical patent/WO2001016738A3/en
Publication of WO2001016738A9 publication Critical patent/WO2001016738A9/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/457—Communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/52—Indexing scheme relating to G06F9/52
    • G06F2209/523—Mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)

Abstract

Methods, systems and devices are described for efficient page ownership control. A method includes: providing a centrally-available record showing that a first process owns a memory page; recording in the centrally-available record a second process as owning the memory page; requesting ownership of the memory page by signaling the first process with the second process; then relinquishing control of the memory page by the first process by marking the memory page as not-owned in at least one control block that is private to the first process; then signaling the second process with the first process that ownership of the memory page is transferred; and then modifying the memory page with the second process. The methods, systems and devices provide advantages because the speed and scalability of parallel processor systems is enhanced.
PCT/US2000/024150 1999-08-31 2000-08-31 Efficient page ownership control WO2001016738A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU69496/00A AU6949600A (en) 1999-08-31 2000-08-31 Efficient page ownership control

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US15215199P 1999-08-31 1999-08-31
US60/152,151 1999-08-31
US22097400P 2000-07-26 2000-07-26
US22074800P 2000-07-26 2000-07-26
US60/220,974 2000-07-26
US60/220,748 2000-07-26

Publications (4)

Publication Number Publication Date
WO2001016738A2 WO2001016738A2 (en) 2001-03-08
WO2001016738A8 WO2001016738A8 (en) 2001-05-03
WO2001016738A3 true WO2001016738A3 (en) 2001-10-04
WO2001016738A9 WO2001016738A9 (en) 2002-09-12

Family

ID=27387201

Family Applications (9)

Application Number Title Priority Date Filing Date
PCT/US2000/024147 WO2001016737A2 (en) 1999-08-31 2000-08-31 Cache-coherent shared-memory cluster
PCT/US2000/024248 WO2001016742A2 (en) 1999-08-31 2000-08-31 Network shared memory
PCT/US2000/024210 WO2001016740A2 (en) 1999-08-31 2000-08-31 Efficient event waiting
PCT/US2000/024150 WO2001016738A2 (en) 1999-08-31 2000-08-31 Efficient page ownership control
PCT/US2000/024298 WO2001016743A2 (en) 1999-08-31 2000-08-31 Shared memory disk
PCT/US2000/024217 WO2001016741A2 (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory
PCT/US2000/024039 WO2001016760A1 (en) 1999-08-31 2000-08-31 Switchable shared-memory cluster
PCT/US2000/024216 WO2001016761A2 (en) 1999-08-31 2000-08-31 Efficient page allocation
PCT/US2000/024329 WO2001016750A2 (en) 1999-08-31 2000-08-31 High-availability, shared-memory cluster

Family Applications Before (3)

Application Number Title Priority Date Filing Date
PCT/US2000/024147 WO2001016737A2 (en) 1999-08-31 2000-08-31 Cache-coherent shared-memory cluster
PCT/US2000/024248 WO2001016742A2 (en) 1999-08-31 2000-08-31 Network shared memory
PCT/US2000/024210 WO2001016740A2 (en) 1999-08-31 2000-08-31 Efficient event waiting

Family Applications After (5)

Application Number Title Priority Date Filing Date
PCT/US2000/024298 WO2001016743A2 (en) 1999-08-31 2000-08-31 Shared memory disk
PCT/US2000/024217 WO2001016741A2 (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory
PCT/US2000/024039 WO2001016760A1 (en) 1999-08-31 2000-08-31 Switchable shared-memory cluster
PCT/US2000/024216 WO2001016761A2 (en) 1999-08-31 2000-08-31 Efficient page allocation
PCT/US2000/024329 WO2001016750A2 (en) 1999-08-31 2000-08-31 High-availability, shared-memory cluster

Country Status (4)

Country Link
EP (3) EP1214651A2 (en)
AU (9) AU6949700A (en)
CA (3) CA2382728A1 (en)
WO (9) WO2001016737A2 (en)

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US6999998B2 (en) 2001-10-04 2006-02-14 Hewlett-Packard Development Company, L.P. Shared memory coupling of network infrastructure devices
US6920485B2 (en) 2001-10-04 2005-07-19 Hewlett-Packard Development Company, L.P. Packet processing in shared memory multi-computer systems
US7254745B2 (en) 2002-10-03 2007-08-07 International Business Machines Corporation Diagnostic probe management in data processing systems
JP2008046969A (en) * 2006-08-18 2008-02-28 Fujitsu Ltd Method and apparatus for monitoring access to shared memory
US7685381B2 (en) 2007-03-01 2010-03-23 International Business Machines Corporation Employing a data structure of readily accessible units of memory to facilitate memory access
US7899663B2 (en) 2007-03-30 2011-03-01 International Business Machines Corporation Providing memory consistency in an emulated processing environment
US9442780B2 (en) * 2011-07-19 2016-09-13 Qualcomm Incorporated Synchronization of shader operation
US9064437B2 (en) 2012-12-07 2015-06-23 Intel Corporation Memory based semaphores
JP6089349B2 (en) 2013-05-28 2017-03-08 ▲ホア▼▲ウェイ▼技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． Method and system for supporting resource separation in a multi-core architecture
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Also Published As

Publication number Publication date
WO2001016738A2 (en) 2001-03-08
AU7108500A (en) 2001-03-26
WO2001016760A1 (en) 2001-03-08
WO2001016741A3 (en) 2001-09-20
WO2001016750A2 (en) 2001-03-08
WO2001016761A2 (en) 2001-03-08
AU7108300A (en) 2001-03-26
WO2001016750A3 (en) 2002-01-17
AU7110000A (en) 2001-03-26
WO2001016737A2 (en) 2001-03-08
CA2382929A1 (en) 2001-03-08
WO2001016742A2 (en) 2001-03-08
AU7100700A (en) 2001-03-26
WO2001016743A2 (en) 2001-03-08
WO2001016738A8 (en) 2001-05-03
WO2001016740A2 (en) 2001-03-08
WO2001016742A3 (en) 2001-09-20
AU7112100A (en) 2001-03-26
WO2001016761A3 (en) 2001-12-27
EP1214651A2 (en) 2002-06-19
WO2001016743A8 (en) 2001-10-18
EP1214653A2 (en) 2002-06-19
WO2001016743A3 (en) 2001-08-09
WO2001016741A2 (en) 2001-03-08
AU6949600A (en) 2001-03-26
WO2001016737A3 (en) 2001-11-08
WO2001016738A9 (en) 2002-09-12
CA2382927A1 (en) 2001-03-08
AU6949700A (en) 2001-03-26
EP1214652A2 (en) 2002-06-19
AU7474200A (en) 2001-03-26
WO2001016740A3 (en) 2001-12-27
CA2382728A1 (en) 2001-03-08
AU7113600A (en) 2001-03-26

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