WO2001013562A3 - Architecture de demodulateur numerique en rafale grande vitesse - Google Patents

Architecture de demodulateur numerique en rafale grande vitesse Download PDF

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Publication number
WO2001013562A3
WO2001013562A3 PCT/US2000/017873 US0017873W WO0113562A3 WO 2001013562 A3 WO2001013562 A3 WO 2001013562A3 US 0017873 W US0017873 W US 0017873W WO 0113562 A3 WO0113562 A3 WO 0113562A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
demodulator
rate
high speed
digital demodulator
Prior art date
Application number
PCT/US2000/017873
Other languages
English (en)
Other versions
WO2001013562A2 (fr
Inventor
Soheil I Sayegh
James R Thomas
Original Assignee
Comsat Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Comsat Corp filed Critical Comsat Corp
Publication of WO2001013562A2 publication Critical patent/WO2001013562A2/fr
Publication of WO2001013562A3 publication Critical patent/WO2001013562A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20—Repeater circuits; Relay circuits
    • H04L25/22—Repeaters for converting two wires to four wires; Repeaters for converting single current to double current
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Cette invention concerne une structure unique en son genre de dispositif de démodulation qui permet d'accroître la fiabilité du traitement de données numériques à des vitesses élevées tout en réduisant dans certains cas le volume de matériels devant être mis en oeuvre pour de telles structures. Grâce à des trajets de données parallèles au sein de plusieurs fonctions communes de l'ensemble de démodulation, il est possible de ramener le débit de traitement des données dans chacun des trajets à une valeur inférieure au débit de réception des données. Ultérieurement, les données peuvent être transférées au débit de réception d'origine ou bien être traitées à un débit plus faible. Grâce aux réductions obtenues en termes de masse, de taille et de puissance pour le démodulateur, ce dernier peut travailler à des vitesses qui, sinon, ne pourraient pas être atteintes.
PCT/US2000/017873 1999-08-13 2000-08-01 Architecture de demodulateur numerique en rafale grande vitesse WO2001013562A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37371199A 1999-08-13 1999-08-13
US09/373,711 1999-08-13

Publications (2)

Publication Number Publication Date
WO2001013562A2 WO2001013562A2 (fr) 2001-02-22
WO2001013562A3 true WO2001013562A3 (fr) 2002-01-10

Family

ID=23473543

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/017873 WO2001013562A2 (fr) 1999-08-13 2000-08-01 Architecture de demodulateur numerique en rafale grande vitesse

Country Status (1)

Country Link
WO (1) WO2001013562A2 (fr)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9395953B2 (en) 2006-12-05 2016-07-19 Altera Corporation Large multiplier for programmable logic device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6556044B2 (en) * 2001-09-18 2003-04-29 Altera Corporation Programmable logic device including multipliers and configurations thereof to reduce resource utilization
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US8244789B1 (en) 2008-03-14 2012-08-14 Altera Corporation Normalization of floating point operations in a programmable integrated circuit device
US8886696B1 (en) 2009-03-03 2014-11-11 Altera Corporation Digital signal processing circuitry with redundancy and ability to support larger multipliers
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9379687B1 (en) 2014-01-14 2016-06-28 Altera Corporation Pipelined systolic finite impulse response filter
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
CN114338304B (zh) * 2021-12-29 2023-08-15 中国工程物理研究院电子工程研究所 一种用于高速通信的并行基带解调器系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5454009A (en) * 1994-01-13 1995-09-26 Scientific-Atlanta, Inc. Method and apparatus for providing energy dispersal using frequency diversity in a satellite communications system
US5459524A (en) * 1991-11-18 1995-10-17 Cooper; J. Carl Phase modulation demodulator apparatus and method
US5867400A (en) * 1995-05-17 1999-02-02 International Business Machines Corporation Application specific processor and design method for same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459524A (en) * 1991-11-18 1995-10-17 Cooper; J. Carl Phase modulation demodulator apparatus and method
US5454009A (en) * 1994-01-13 1995-09-26 Scientific-Atlanta, Inc. Method and apparatus for providing energy dispersal using frequency diversity in a satellite communications system
US5867400A (en) * 1995-05-17 1999-02-02 International Business Machines Corporation Application specific processor and design method for same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9395953B2 (en) 2006-12-05 2016-07-19 Altera Corporation Large multiplier for programmable logic device
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding

Also Published As

Publication number Publication date
WO2001013562A2 (fr) 2001-02-22

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