WO2001013229A3 - System and method for data exchange - Google Patents

System and method for data exchange Download PDF

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Publication number
WO2001013229A3
WO2001013229A3 PCT/US2000/022701 US0022701W WO0113229A3 WO 2001013229 A3 WO2001013229 A3 WO 2001013229A3 US 0022701 W US0022701 W US 0022701W WO 0113229 A3 WO0113229 A3 WO 0113229A3
Authority
WO
WIPO (PCT)
Prior art keywords
writers
readers
data
buffer
read
Prior art date
Application number
PCT/US2000/022701
Other languages
French (fr)
Other versions
WO2001013229A2 (en
Inventor
Myron Zimmerman
Paul A Blanco
Thomas Scott
Original Assignee
Venturcom Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Venturcom Inc filed Critical Venturcom Inc
Publication of WO2001013229A2 publication Critical patent/WO2001013229A2/en
Publication of WO2001013229A3 publication Critical patent/WO2001013229A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

Using a lockless protocol, readers and writers exchange data of arbitrary size without using operating system services other than to initially establish a region of global shared memory. The readers and writers may be in interrupt context, process context and/or thread context. Multiple readers and writers are permitted, on the same or on separate processors sharing a global memory. Writers own a set of buffers in global shared memory. The buffers are re-used by their owner using an LRU algorithm. New data is made available to readers by atomically writing the buffer ID of the most recently written buffer into a shared location. Readers use this shared location to find the most recently written data. If a reader does not have sufficient priority to read the data in the buffer before a writer must re-use the buffer for subsequent data, the reader restarts its read. Buffers contain sequence numbers maintained by the writers to allow the readers to detect this 'slow read' situation and to restart its read using the most recently written buffer. Provisions are provided for data time stamps and for resolving ambiguity in the execution order of multiple writers that could cause time stamps to retrogress.
PCT/US2000/022701 1999-08-19 2000-08-18 System and method for data exchange WO2001013229A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14983199P 1999-08-19 1999-08-19
US60/149,831 1999-08-19

Publications (2)

Publication Number Publication Date
WO2001013229A2 WO2001013229A2 (en) 2001-02-22
WO2001013229A3 true WO2001013229A3 (en) 2001-12-20

Family

ID=22531977

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/022701 WO2001013229A2 (en) 1999-08-19 2000-08-18 System and method for data exchange

Country Status (1)

Country Link
WO (1) WO2001013229A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9529731B1 (en) * 2014-06-12 2016-12-27 Emc Corporation Contention-free approximate LRU for multi-threaded access
US9460025B1 (en) 2014-06-12 2016-10-04 Emc Corporation Maintaining a separate LRU linked list for each thread for multi-threaded access
US10560542B2 (en) 2014-09-15 2020-02-11 Ge Aviation Systems Llc Mechanism and method for communicating between a client and a server by accessing message data in a shared memory
US9794340B2 (en) * 2014-09-15 2017-10-17 Ge Aviation Systems Llc Mechanism and method for accessing data in a shared memory
CN107704325B (en) * 2016-08-08 2021-08-27 北京百度网讯科技有限公司 Method and device for transmitting messages between processes
WO2019127244A1 (en) 2017-12-28 2019-07-04 SZ DJI Technology Co., Ltd. System and method for supporting low latency in a movable platform environment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551242A2 (en) * 1992-01-10 1993-07-14 Digital Equipment Corporation Multiprocessor buffer system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551242A2 (en) * 1992-01-10 1993-07-14 Digital Equipment Corporation Multiprocessor buffer system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"COPYLESS AND LOCKLESS DATA SEPARATION", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 37, no. 2A, 1 February 1994 (1994-02-01), pages 351, XP000433360, ISSN: 0018-8689 *
S. J. YOUNG: "INTER-PROCESS COMMUNICATION PRIMITIVES FOR DSM MULTIPROCESSORS", IMPLEMENTING FUNCTIONS: MICROPROCESSORS AND FIRMWARE, PROCEEDINGS OF THE SEVENTH EUROMICRO SYMPOSIUM ON MICROPROCESSING AND MICROPROGRAMMING, NORTH HOLLAND PUBLISHING COMPAGNY, 8 September 1981 (1981-09-08) - 10 September 1981 (1981-09-10), Paris, France, pages 327 - 332, XP002166142 *
SIMPSON H R: "NEW ALGORITHMS FOR ASYNCHRONOUS COMMUNICATION", IEE PROCEEDINGS: COMPUTERS AND DIGITAL TECHNIQUES,IEE,GB, vol. 144, no. 4, 1 July 1997 (1997-07-01), pages 227 - 231, XP000734489, ISSN: 1350-2387 *

Also Published As

Publication number Publication date
WO2001013229A2 (en) 2001-02-22

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