WO2001008192A1 - Insulated-gate electron field emission devices and their fabrication processes - Google Patents

Insulated-gate electron field emission devices and their fabrication processes Download PDF

Info

Publication number
WO2001008192A1
WO2001008192A1 PCT/US2000/020144 US0020144W WO0108192A1 WO 2001008192 A1 WO2001008192 A1 WO 2001008192A1 US 0020144 W US0020144 W US 0020144W WO 0108192 A1 WO0108192 A1 WO 0108192A1
Authority
WO
WIPO (PCT)
Prior art keywords
emitter
anode
gate electrode
insulating layer
gate
Prior art date
Application number
PCT/US2000/020144
Other languages
French (fr)
Inventor
Michael D. Potter
Original Assignee
Advanced Vision Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Vision Technologies, Inc. filed Critical Advanced Vision Technologies, Inc.
Priority to KR1020017003710A priority Critical patent/KR20010075311A/en
Priority to CA002355660A priority patent/CA2355660A1/en
Priority to EP00948927A priority patent/EP1116255A1/en
Priority to JP2001512613A priority patent/JP2003505843A/en
Publication of WO2001008192A1 publication Critical patent/WO2001008192A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J21/00—Vacuum tubes
    • H01J21/02—Tubes with a single discharge path
    • H01J21/06—Tubes with a single discharge path having electrostatic control means only
    • H01J21/10—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode
    • H01J21/105—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode with microengineered cathode and control electrodes, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes

Definitions

  • This invention relates generally to microelectronic devices and their fabrication processes, and more particularly to insulated-gate field emission microelectronic devices having a gate electrode disposed outside a chamber containing an emitter and an anode.
  • gate and "gate electrode” are used interchangeably throughout the present specification and the appended claims to mean any electrode other than an emitter or anode of an electron field-emission device, whether the gate is to be used as a control electrode or extraction electrode or performs some other function.
  • the microelectronic device may have more than one gate, and physically distinct gates may be electrically independent or may have related electrical potentials applied.
  • lateral refers generally to a direction parallel to a substrate on which an electronic device is formed.
  • a “lateral field-emission device” refers to a field-emission device formed on a substrate and formed with a structure such that an anode is spaced apart from a field emitter along at least a direction parallel to the substrate.
  • lateral emitter refers to a field emitter made substantially parallel to the substrate of a lateral device, whereby emission of electrons toward the anode occurs generally parallel to the substrate. Examples of such lateral emitters formed of thin films are known in the related art.
  • substrate refers to any of the following: a simple base substrate consisting of a single material, or a composite substrate consisting of a base substrate on which one or more layers of a different material have been added, or the top layer of such a composite substrate.
  • field-emission device structures including diodes, triodes, and tetrodes, have been developed for use in electronic circuits. Some of the field-emission devices have been adapted specifically for use in displays. In such displays, each pixel cell uses one or more field-emission devices. Field-emission displays are considered an attractive alternative and replacement for flat-panel liquid crystal displays, because of their lower manufacturing cost and lower complexity, lower power consumption, higher brightness, and improved range of viewing angles. There is a continuing need for improved microelectronic device structures and fabrication processes, especially for flat panel displays.
  • microelectronic field-emission devices in the related art have had gate electrodes exposed to the same vacuum or gas-filled environment as the emitter, thus exposing the gate electrode to direct current of electrons from the field-emission cathode and allowing secondary emission to occur from the surface of the gate electrode.
  • a lateral-emitter field emission device has a gate that is separated by an insulating layer from a vacuum- or gas-filled environment containing other elements of the device.
  • the gate may be disposed external to a microchamber.
  • the insulating layer is disposed such that there is no vacuum- or gas-filled path to the gate for electrons that are emitted from a lateral emitter.
  • the insulating layer disposed between the emitter and the gate preferably comprises a material having a dielectric constant greater than one.
  • the insulating layer also preferably has a low secondary electron yield over the device's operative range of electron energies.
  • the insulating layer is preferably transparent. Emitted electrons are confined to the microchamber containing their emitter.
  • the gate current component of the emitter current consists of displacement current only, and direct electron current from the emitter to the gate is prevented.
  • An array of the devices comprises an array of microchambers, so that electron current from each emitter can reach only the anode in the same microchamber, even for diode devices lacking a gate electrode.
  • a fabrication process is specially adapted for fabricating the device and arrays of such devices, including formation in situ of a vacuum microchamber.
  • FIGS. 1 - 13 show a series of side-elevation cross-sectional views illustrating overall fabrication of a confined-electron device made in accordance with the invention.
  • FIG. 14 shows a flow chart illustrating an overall fabrication process performed in accordance with the invention.
  • FIGS. 15 - 27 show a series of side-elevation, cross-sectional views illustrating fabrication of an insulated-gate electron field emission device made in accordance with the invention. Modes for Carrying Out the Invention
  • CMOS complementary metal-oxide-semiconductor
  • PMOS complementary metal-oxide-semiconductor
  • Bipolar Bipolar-CMOS
  • the new device may also be used for a display element or as a display system. It may incorporate integrated luminescent materials or may be used in conjunction with luminescent materials on a separate subassembly. It may also have integrated display driver circuitry.
  • FIGS. 1 - 11 show side elevation, cross-sectional views illustrating various stages in an overall process of making a device in accordance with the invention.
  • FIG. 14 is a flow chart illustrating a first overall process for making a device in accordance with the invention.
  • a conducting substrate 15 is used, a first insulating layer is deposited on the conducting substrate 15 to form an insulating substrate 20. If an insulating substrate 20 is used, as shown in FIG. 1, this step is omitted.
  • a conducting gate material 30 is deposited and patterned onto the first insulating layer (FIG. 1).
  • a second insulating layer 40 is deposited over the gate layer 30 (FIG. 2).
  • a conducting emitter layer 50 is deposited and patterned onto the second insulating layer 40 (FIG. 3).
  • a third insulating layer 60 is deposited over the emitter layer 50 (FIG. 4).
  • a trench 70 is formed (FIG. 5) which removes a portion of the third insulating layer 60 down to the emitter layer 50.
  • the emitter material in the trench-defined area is removed (FIG. 6), leaving at least an emitting edge 80 on emitter layer 50.
  • a portion of the second insulating layer 40 may be removed. However, a portion of the second insulating layer 40 remains which eliminates any vacuum path and prevents DC current between the emitter 50 and the gate 30.
  • Conventional contact holes, inter-layer studs, etc. are provided for by conventional semiconductor fabrication means.
  • the structure made by this process may form a subassembly for various systems such as flat panel displays.
  • a separate faceplate 100 coated with luminescent material is placed above the trench area (FIG. 7), forming a chamber 110.
  • a focusing grid (not shown) may be inserted between the emitter 50 (i.e., emitter edge 80) and the faceplate 100.
  • the faceplate may be replaced with a conducting material to act as an anode. Spacer columns 90 and/or sealing may also be used.
  • FIG. 6 The structure described above (FIGS. 1 -6) may be a part of an integrated device.
  • This integrated device may be an active triode or a display element.
  • a sacrificial material 120 is deposited and patterned (FIG. 8), which completely fills at least the trench- defined area 70.
  • a conducting anode 130 is deposited onto the third insulating layer 60 and the sacrificial layer 120 combination (FIG. 9). This conducting anode 130 may be patterned if desired.
  • An access hole 140 is made through the anode-conducting layer 130 by means of standard semiconductor fabrication techniques (FIG. 10).
  • the sacrificial material 120 is removed through the access hole 140, leaving empty chamber 160.
  • a sealant material 150, 155 is deposited in a vacuum system (FIG. 11).
  • the vacuum level is defined to be sufficient for the operation of the triode device.
  • the sealant material 150, 155 may be re-flowed in situ if required.
  • the sealant material 150, 155 may be patterned if required.
  • a sacrificial material 120 is deposited and patterned, which completely fills at least the trench- defined area 70. (See FIG. 8)
  • a luminescent anode material 135 is deposited onto the third insulating layer 60 and the sacrificial layer 120 combination. This luminescent anode material layer 135 may be patterned if desired. A fourth transparent insulating layer (not shown) may be deposited over the luminescent material layer 135 if needed. An access hole 140 is made through the anode material layer 135 by means of standard semiconductor fabrication techniques. The sacrificial material 120 is removed through the access hole 140. (See FIG. 10.)
  • a sealant material 150, 155 is deposited in a vacuum system (FIG. 13).
  • the vacuum level provided is to be sufficient for the operation of the display element.
  • the sealant material 150, 155 may be re-flowed in situ if required.
  • the sealant material 150, 155 may be patterned to remove it over the display element light emitting area. This layer 150, 155 may be left intact if it is a transparent material.
  • S9 Enclose chamber (S9a) and perform steps Sll, S12, S13, S14, and S15
  • FIG. 14 is a flow chart illustrating this overall fabrication process, with the various process steps designated by reference numerals SI, S2, ... , S17. For each of these steps, the act performed is listed in Table I (previous page).
  • Part II Described in the following description is a new insulated-gate electron field emission device.
  • the structure has no vacuum path between the emitter and the gate of the device.
  • This new structure eliminates any possible DC gate current, thereby making the device behave as a purely ballistic electron field effect transistor. It may have integrated circuitry made of similar device structures, solid state device structures such as silicon or III-V materials including CMOS, NMOS, PMOS, Bipolar, Bi-CMOS, etc.
  • the new device is particularly useful for high frequency applications including wireless communication systems.
  • Part II The first case described in this section (Part II) is for a common gate structure for process simplification.
  • the preferred embodiment is the second case described in this section (Part II).
  • a conducting substrate 15 is used, and a first insulating layer 25 is deposited on the conducting substrate 15, thus forming an insulating substrate.
  • a second insulating layer 40 is deposited on the first insulating layer.
  • the first insulating layer 25 and the second insulating layer 40 are distinguished from each other by having different etch characteristics for an etchant used later in the process.
  • a conducting emitter material layer 50 is deposited on the second insulating layer and patterned (FIG. 16).
  • a third insulating layer 60 (also shown in FIG. 16) is deposited on the emitter layer 50.
  • the third insulating layer 60 is patterned (FIG. 17) by etching to form openings 65 and 75 for the emitter contact stud and the anode member respectively. This etching process stops on the emitter layer 50 and on the first insulator layer 25, as shown in FIG. 17.
  • the openings 65 and 75 are filled (FIG. 18) with a conducting material to form respectively an emitter contact stud 85 and an anode 95) and planarized by using conventional chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • a trench 70 is etched (FIG. 19) which exposes at least a portion of the emitter layer 50, leaving an emitting edge 80 on emitter layer 50, and exposes at least a portion of anode 95. The etch will stop on the first insulating layer 25, as shown in FIG. 19.
  • a sacrificial layer 120 is deposited on the third insulating layer 60, the emitter contact stud 85, and the anode 95 (FIG. 20).
  • the sacrificial layer is patterned as shown in FIG. 20.
  • a fourth insulating layer 165 is deposited (FIG. 21) on the third insulating layer 60 and the sacrificial layer 120.
  • Access holes 170 and 180 are patterned and etched through the fourth insulating layer 165, and the sacrificial material 120 is removed (FIG. 22) through access holes 170 and 180, leaving opening 70 empty.
  • the access holes 170 and 180 are disposed so that at least a portion of each access hole is aligned with an underlying element, one (170) aligned over the emitter contact stud 85 and the other (180) aligned over the anode 95, as shown in FIG. 22.
  • a material 190 such as a metal, is deposited on the fourth insulator 165 in a vacuum (FIG. 23).
  • the material 190 is re-flowed in situ to seal the access holes 170 and 180.
  • the sealing material 190 is patterned to leave material substantially over access holes 170 and 180, thus sealing them.
  • the chamber body is thus fabricated in situ as a vacuum chamber 160.
  • the sealing plugs formed by material 190 may further provide conductive electrical contacts to the emitter and the anode (FIG. 23).
  • a structure for a non-common gate is disclosed below that significantly reduces the gate to emitter and gate to anode capacitance.
  • the reduced capacitance maximizes the switching speed and overall performance of the device.
  • a conducting substrate 15 is used, a first insulator 25 is deposited to isolate the device. If an insulating substrate 20 is used, an additional first insulating layer 25 may not be required.
  • the process for an insulating substrate 20 case is described below.
  • a gate trench 200 is patterned and etched into the insulating substrate (FIG. 24).
  • a first conducting gate layer 210 is deposited on the insulating substrate and planarized to a level that fills the trenches (FIG. 25) to form a gate electrode 30. The process from this point is the same as the preceding description from the point of depositing the first insulating layer through depositing the third insulating layer (FIGS. 15 - 16).
  • a third opening (not shown) is provided that will act as the gate conducting contact for contacting gate electrode 30.
  • An etch that etches to the gate conducting layer 210 is performed to provide for the gate contact. (The gate contact, being outside of the cross-section plane of FIGS. 26 and 27, is not shown).
  • the anode 95 is at least partially composed of a luminescent material.
  • a bi-directional device can be fabricated by replacing the anode with a mirror image of the emitter member 50 and gate member 30, as shown in FIG. 27.
  • a gate 30 can be shared between two emitters 50, or a separate gate 30 can control each emitter 50.
  • Conventional contact holes, inter-layer studs, etc. are provided for by conventional semiconductor fabrication means.
  • the invention is useful in fabrication of field emission devices and is especially useful for field emission displays that consist of an array of field emission devices, since each device in the array may have a separate microchamber containing an emitter and a cathodoluminescent anode responsive only to electrons from its own emitter. If made with a gate electrode separated from each microchamber by an insulating layer, each microelectronic device has improved performance.
  • the preferred fabrication process is specially adapted for simultaneous fabrication of many devices in such an array.
  • the invention eliminates or greatly reduces direct current flowing from the emitter to the gate of an electron field-emission microelectronic device.
  • the invention can also reduce undesirable secondary electron emission without requiring introduction of an additional electrode for secondary-electron-emission suppression. Secondary electron emission from a gate electrode could otherwise adversely affect control of anode current by the gate electrode.
  • crosstalk between pixels is eliminated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Cold Cathode And The Manufacture (AREA)

Abstract

A lateral-emitter field emission device has a gate (30) that is separated by an insulating layer (40) from a vacuum- or gas-filled environment containing other elements of the device. For example, the gate may be disposed external to a microchamber (110). The insulating layer is disposed such that there is no vacuum- or gas-filled path to the gate for electrons that are emitted from a lateral emitter. The insulating layer disposed between the emitter and the gate preferably comprises a material having a dielectric constant greater than one. The insulating layer also preferably has a low secondary electron yield over the device's operative range of electron energies. For display applications, the insulating layer is preferably transparent. Emitted electrons are confined to the microchamber containing their emitter. Thus, the gate current component of the emitter current consists of displacement current only, and direct electron current from the emitter to the gate is prevented. An array of the devices comprises an array of microchamber, so that electron current from each emitter can reach only the anode in the same microchamber, even for diode devices lacking a gate electrode. A fabrication process is specially adapted for fabricating the device and arrays of such devices, including formation in situ of a vacuum microchamber.

Description

Title of Invention
INSULATED-GATE ELECTRON FIELD EMISSION DEVICES
AND THEIR FABRICATION PROCESSES
Description
Technical Field
This invention relates generally to microelectronic devices and their fabrication processes, and more particularly to insulated-gate field emission microelectronic devices having a gate electrode disposed outside a chamber containing an emitter and an anode.
Notations And Nomenclature
The terms "gate" and "gate electrode" are used interchangeably throughout the present specification and the appended claims to mean any electrode other than an emitter or anode of an electron field-emission device, whether the gate is to be used as a control electrode or extraction electrode or performs some other function. The microelectronic device may have more than one gate, and physically distinct gates may be electrically independent or may have related electrical potentials applied.
The term "lateral" refers generally to a direction parallel to a substrate on which an electronic device is formed. Thus, a "lateral field-emission device" refers to a field-emission device formed on a substrate and formed with a structure such that an anode is spaced apart from a field emitter along at least a direction parallel to the substrate. Similarly, the term "lateral emitter" refers to a field emitter made substantially parallel to the substrate of a lateral device, whereby emission of electrons toward the anode occurs generally parallel to the substrate. Examples of such lateral emitters formed of thin films are known in the related art.
The term "substrate" refers to any of the following: a simple base substrate consisting of a single material, or a composite substrate consisting of a base substrate on which one or more layers of a different material have been added, or the top layer of such a composite substrate.
Background Art
Many field-emission device structures, including diodes, triodes, and tetrodes, have been developed for use in electronic circuits. Some of the field-emission devices have been adapted specifically for use in displays. In such displays, each pixel cell uses one or more field-emission devices. Field-emission displays are considered an attractive alternative and replacement for flat-panel liquid crystal displays, because of their lower manufacturing cost and lower complexity, lower power consumption, higher brightness, and improved range of viewing angles. There is a continuing need for improved microelectronic device structures and fabrication processes, especially for flat panel displays.
Many field-emission device structures are known, of which it appears that a majority have been generally of the Spindt type, as described for example in U.S. Pat. No. 3,755,704. The following U.S. patents describe various field emission devices having lateral field emitters and/or their fabrication processes: Lambe 4,728,851; Lee et al. 4,827,177; Jones et al., 5,144,191; Cronin et al. 5,233,263 and 5,308,439; Xie et al. 5,528,099 and 5,445,550; Mandelman et al. 5,629,580; and Potter 5,616,061, 5,618,216, 5,628,663, 5,630,741, 5,644,188, 5,644,190, 5,647,998, 5,666,019, 5,669,802, 5,691,599, 5,700,176, 5,703,380, 5,811,929, 5,831,384, 5,850,123, 5,872,421, 5,920,148, 5,965,192, 6,004,830, 6,005,335, 6,015,324, 6,015,326, 6,017,257, 6,037,708, and 6,071,633.
Heretofore, microelectronic field-emission devices in the related art (including both Spindt type devices and lateral-emitter type devices) have had gate electrodes exposed to the same vacuum or gas-filled environment as the emitter, thus exposing the gate electrode to direct current of electrons from the field-emission cathode and allowing secondary emission to occur from the surface of the gate electrode.
Disclosure of Invention
A lateral-emitter field emission device has a gate that is separated by an insulating layer from a vacuum- or gas-filled environment containing other elements of the device. For example, the gate may be disposed external to a microchamber. The insulating layer is disposed such that there is no vacuum- or gas-filled path to the gate for electrons that are emitted from a lateral emitter. The insulating layer disposed between the emitter and the gate preferably comprises a material having a dielectric constant greater than one. The insulating layer also preferably has a low secondary electron yield over the device's operative range of electron energies. For display applications, the insulating layer is preferably transparent. Emitted electrons are confined to the microchamber containing their emitter. Thus, the gate current component of the emitter current consists of displacement current only, and direct electron current from the emitter to the gate is prevented. An array of the devices comprises an array of microchambers, so that electron current from each emitter can reach only the anode in the same microchamber, even for diode devices lacking a gate electrode. A fabrication process is specially adapted for fabricating the device and arrays of such devices, including formation in situ of a vacuum microchamber.
Part I - "Inverted" Confined Electron Field Emission Devices and Display Elements
The entire disclosure of the following documents is incorporated herein by reference: U.S. patent applications Serial Nos. 09/020,547 and 09/020,548 filed Feb. 9, 1998 (both abandoned), U.S. patent applications Serial Nos. 09/276,198 and 09/276,200 filed March 25, 1999, U.S. Pat. No. 6,004,830 issued Dec. 21, 1999, and international patent application PCT/US99/02609 filed Feb. 6, 1999.
Brief Description of Drawings
FIGS. 1 - 13 show a series of side-elevation cross-sectional views illustrating overall fabrication of a confined-electron device made in accordance with the invention.
FIG. 14 shows a flow chart illustrating an overall fabrication process performed in accordance with the invention.
FIGS. 15 - 27 show a series of side-elevation, cross-sectional views illustrating fabrication of an insulated-gate electron field emission device made in accordance with the invention. Modes for Carrying Out the Invention
Described herein is a new inverted confined electron field emission device. The structure has no vacuum path between the emitter and the gate of the device. This new structure eliminates any possible DC gate current thereby making the device behave as a purely ballistic electron field effect transistor. It may have integrated circuitry made of similar device structures, solid state device structures such as silicon or m-V materials including CMOS, NMOS, PMOS, Bipolar, Bi-CMOS, etc. The new device may also be used for a display element or as a display system. It may incorporate integrated luminescent materials or may be used in conjunction with luminescent materials on a separate subassembly. It may also have integrated display driver circuitry.
FIGS. 1 - 11 show side elevation, cross-sectional views illustrating various stages in an overall process of making a device in accordance with the invention. FIG. 14 is a flow chart illustrating a first overall process for making a device in accordance with the invention.
If a conducting substrate 15 is used, a first insulating layer is deposited on the conducting substrate 15 to form an insulating substrate 20. If an insulating substrate 20 is used, as shown in FIG. 1, this step is omitted.
A conducting gate material 30 is deposited and patterned onto the first insulating layer (FIG. 1). A second insulating layer 40 is deposited over the gate layer 30 (FIG. 2). A conducting emitter layer 50 is deposited and patterned onto the second insulating layer 40 (FIG. 3). A third insulating layer 60 is deposited over the emitter layer 50 (FIG. 4). A trench 70 is formed (FIG. 5) which removes a portion of the third insulating layer 60 down to the emitter layer 50. The emitter material in the trench-defined area is removed (FIG. 6), leaving at least an emitting edge 80 on emitter layer 50. A portion of the second insulating layer 40 may be removed. However, a portion of the second insulating layer 40 remains which eliminates any vacuum path and prevents DC current between the emitter 50 and the gate 30.
Conventional contact holes, inter-layer studs, etc. (not shown) are provided for by conventional semiconductor fabrication means. The structure made by this process may form a subassembly for various systems such as flat panel displays. In this case a separate faceplate 100 coated with luminescent material is placed above the trench area (FIG. 7), forming a chamber 110. In a particular embodiment a focusing grid (not shown) may be inserted between the emitter 50 (i.e., emitter edge 80) and the faceplate 100. In another embodiment, the faceplate may be replaced with a conducting material to act as an anode. Spacer columns 90 and/or sealing may also be used.
The structure described above (FIGS. 1 -6) may be a part of an integrated device. This integrated device may be an active triode or a display element. In the case of an active triode element, after the trench 70 is formed a sacrificial material 120 is deposited and patterned (FIG. 8), which completely fills at least the trench- defined area 70.
A conducting anode 130 is deposited onto the third insulating layer 60 and the sacrificial layer 120 combination (FIG. 9). This conducting anode 130 may be patterned if desired.
An access hole 140 is made through the anode-conducting layer 130 by means of standard semiconductor fabrication techniques (FIG. 10). The sacrificial material 120 is removed through the access hole 140, leaving empty chamber 160.
A sealant material 150, 155 is deposited in a vacuum system (FIG. 11). The vacuum level is defined to be sufficient for the operation of the triode device. The sealant material 150, 155 may be re-flowed in situ if required. The sealant material 150, 155 may be patterned if required.
Conventional contact holes, inter-layer studs, etc. (not shown) are provided for by conventional semiconductor fabrication means.
In the case of a display element, after the trench 70 is formed a sacrificial material 120 is deposited and patterned, which completely fills at least the trench- defined area 70. (See FIG. 8)
A luminescent anode material 135 is deposited onto the third insulating layer 60 and the sacrificial layer 120 combination. This luminescent anode material layer 135 may be patterned if desired. A fourth transparent insulating layer (not shown) may be deposited over the luminescent material layer 135 if needed. An access hole 140 is made through the anode material layer 135 by means of standard semiconductor fabrication techniques. The sacrificial material 120 is removed through the access hole 140. (See FIG. 10.)
A sealant material 150, 155 is deposited in a vacuum system (FIG. 13). The vacuum level provided is to be sufficient for the operation of the display element. The sealant material 150, 155 may be re-flowed in situ if required. The sealant material 150, 155 may be patterned to remove it over the display element light emitting area. This layer 150, 155 may be left intact if it is a transparent material.
SI Provide substrate
51 a If needed, deposit insulating layer
52 Deposit and pattern gate electrode S3 Deposit insulating layer covering gate electrode
54 Deposit and pattern emitter
55 Deposit insulating layer over emitter
56 Form opening through insulating layer without exposing gate electrode
57 Form emitting edge on emitter S8 Provide and dispose anode
S9 Enclose chamber (S9a) and perform steps Sll, S12, S13, S14, and S15
S9a Enclose chamber
S10 (Combination of steps S8 and S9a performed simultaneously)
SI 1 Deposit and pattern sacrificial material S12 Deposit covering layer
513 Form access opening through covering layer
514 Remove sacrificial material through access opening
515 Plug access opening, sealing the chamber
516 Provide means for applying bias voltages S17 Provide means for applying control signals
TABLE I. Process steps of FIG. 14 FIG. 14 is a flow chart illustrating this overall fabrication process, with the various process steps designated by reference numerals SI, S2, ... , S17. For each of these steps, the act performed is listed in Table I (previous page).
Part II - Insulated-Gate Electron Field Emission Devices and Processes
Described in the following description (Part II) is a new insulated-gate electron field emission device. The structure has no vacuum path between the emitter and the gate of the device. This new structure eliminates any possible DC gate current, thereby making the device behave as a purely ballistic electron field effect transistor. It may have integrated circuitry made of similar device structures, solid state device structures such as silicon or III-V materials including CMOS, NMOS, PMOS, Bipolar, Bi-CMOS, etc. The new device is particularly useful for high frequency applications including wireless communication systems.
The first case described in this section (Part II) is for a common gate structure for process simplification. The preferred embodiment is the second case described in this section (Part II).
As shown in FIG. 15, a conducting substrate 15 is used, and a first insulating layer 25 is deposited on the conducting substrate 15, thus forming an insulating substrate. A second insulating layer 40 is deposited on the first insulating layer. The first insulating layer 25 and the second insulating layer 40 are distinguished from each other by having different etch characteristics for an etchant used later in the process.
A conducting emitter material layer 50 is deposited on the second insulating layer and patterned (FIG. 16). A third insulating layer 60 (also shown in FIG. 16) is deposited on the emitter layer 50.
The third insulating layer 60 is patterned (FIG. 17) by etching to form openings 65 and 75 for the emitter contact stud and the anode member respectively. This etching process stops on the emitter layer 50 and on the first insulator layer 25, as shown in FIG. 17.
The openings 65 and 75 are filled (FIG. 18) with a conducting material to form respectively an emitter contact stud 85 and an anode 95) and planarized by using conventional chemical mechanical polishing (CMP). A trench 70 is etched (FIG. 19) which exposes at least a portion of the emitter layer 50, leaving an emitting edge 80 on emitter layer 50, and exposes at least a portion of anode 95. The etch will stop on the first insulating layer 25, as shown in FIG. 19.
A sacrificial layer 120 is deposited on the third insulating layer 60, the emitter contact stud 85, and the anode 95 (FIG. 20). The sacrificial layer is patterned as shown in FIG. 20. A fourth insulating layer 165 is deposited (FIG. 21) on the third insulating layer 60 and the sacrificial layer 120. Access holes 170 and 180 are patterned and etched through the fourth insulating layer 165, and the sacrificial material 120 is removed (FIG. 22) through access holes 170 and 180, leaving opening 70 empty. The access holes 170 and 180 are disposed so that at least a portion of each access hole is aligned with an underlying element, one (170) aligned over the emitter contact stud 85 and the other (180) aligned over the anode 95, as shown in FIG. 22.
A material 190, such as a metal, is deposited on the fourth insulator 165 in a vacuum (FIG. 23). The material 190 is re-flowed in situ to seal the access holes 170 and 180. The sealing material 190 is patterned to leave material substantially over access holes 170 and 180, thus sealing them. The chamber body is thus fabricated in situ as a vacuum chamber 160. The sealing plugs formed by material 190 may further provide conductive electrical contacts to the emitter and the anode (FIG. 23).
In a second case (and preferred embodiment), a structure for a non-common gate is disclosed below that significantly reduces the gate to emitter and gate to anode capacitance. The reduced capacitance maximizes the switching speed and overall performance of the device.
If a conducting substrate 15 is used, a first insulator 25 is deposited to isolate the device. If an insulating substrate 20 is used, an additional first insulating layer 25 may not be required. The process for an insulating substrate 20 case is described below. A gate trench 200 is patterned and etched into the insulating substrate (FIG. 24). A first conducting gate layer 210 is deposited on the insulating substrate and planarized to a level that fills the trenches (FIG. 25) to form a gate electrode 30. The process from this point is the same as the preceding description from the point of depositing the first insulating layer through depositing the third insulating layer (FIGS. 15 - 16).
For the step of patterning and etching the third insulating layer for openings for the emitter contact stud and the anode (as in FIG. 17), a third opening (not shown) is provided that will act as the gate conducting contact for contacting gate electrode 30. An etch that etches to the gate conducting layer 210 is performed to provide for the gate contact. (The gate contact, being outside of the cross-section plane of FIGS. 26 and 27, is not shown).
If it is desired to make a display device, the anode 95 is at least partially composed of a luminescent material.
A bi-directional device can be fabricated by replacing the anode with a mirror image of the emitter member 50 and gate member 30, as shown in FIG. 27. A gate 30 can be shared between two emitters 50, or a separate gate 30 can control each emitter 50. Conventional contact holes, inter-layer studs, etc. are provided for by conventional semiconductor fabrication means.
INDUSTRIAL APPLICABILITY
The invention is useful in fabrication of field emission devices and is especially useful for field emission displays that consist of an array of field emission devices, since each device in the array may have a separate microchamber containing an emitter and a cathodoluminescent anode responsive only to electrons from its own emitter. If made with a gate electrode separated from each microchamber by an insulating layer, each microelectronic device has improved performance. The preferred fabrication process is specially adapted for simultaneous fabrication of many devices in such an array.
The invention eliminates or greatly reduces direct current flowing from the emitter to the gate of an electron field-emission microelectronic device. The invention can also reduce undesirable secondary electron emission without requiring introduction of an additional electrode for secondary-electron-emission suppression. Secondary electron emission from a gate electrode could otherwise adversely affect control of anode current by the gate electrode. In display devices, where at least a portion of the anode of each pixel is comprised of a phosphor, crosstalk between pixels is eliminated.
Although specific embodiments of the present invention have been illustrated in the accompanying drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the particular embodiments described herein. As is apparent from the foregoing description, the invention is capable of being embodied with various alterations and modifications which may differ particularly from those that have been described. For example, the order of performing steps may be changed, and functionally equivalent materials may be substituted. For another example, further gate electrodes (not shown), similarly isolated, may also be employed to provide three or more gate electrodes in a multi- gate device chamber. The following claims are intended to encompass all such modifications. Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their legal equivalents.
What is claimed is:

Claims

1. An insulated-gate electron field emission device, comprising:
a) an insulating substrate;
b) a conductive gate electrode contiguous with said insulating substrate;
c) a chamber coextensive with at least a portion of said gate electrode;
d) an anode disposed to receive electrons emitted into said chamber; and
e) an electron emitter having an emitting edge disposed to emit electrons into and through said chamber to said anode,
said device being characterized by having
f) an insulating layer disposed between said chamber and said portion of said gate electrode, whereby direct current of electrons from said electron emitter to said gate electrode is prevented.
2. An insulated-gate electron field emission device, comprising:
a) an insulating substrate;
b) a conductive gate electrode contiguous with said insulating substrate;
c) a chamber coextensive with at least a portion of said gate electrode;
d) an insulating layer disposed between said chamber and said portion of said gate electrode;
e) an anode disposed to receive electrons emitted into said chamber; and
f) an electron emitter having an emitting edge disposed to emit electrons into and through said chamber to said anode.
3. A device as in claim 1, wherein said insulating substrate (a) comprises:
i) a base substrate selected from a conductor and a semiconductor, and
ii) an insulating layer covering said base substrate.
4. A device as recited in claim 1, further comprising a plurality of gate electrodes.
5. A device as in claim 1, wherein said insulating substrate (a) comprises a material selected from the list consisting of glass, ceramic material, silicon oxide, silicon nitride, aluminum oxide, boron nitride, and diamond.
6. A device as in claim 1, wherein said insulating substrate (a) comprises a substantially transparent substrate.
7. A device as in claim 1, further comprising:
g) means for applying bias voltages to said emitter and said anode, said voltages being effective to cause field emission current of electrons from said emitting edge to said anode.
8. A device as in claim 7, further comprising:
h) means for applying a control voltage to said gate electrode for controlling said current.
9. A device as recited in claim 1, further comprising means for applying an extraction voltage to said gate electrode.
10. A device as recited in claim 1, wherein said insulating film comprises a material having a secondary-electron emission yield of less than one for incident electron energies within an operative range.
11. A device as recited in claim 1 , wherein said insulating film comprises
a material having electric permittivity greater than about four.
12. A device as recited in claim 1, wherein said insulating film comprises first and second layers, wherein
i) said first layer is of a material selected for higher electric permittivity relative to said second layer, and
ii) said second layer is of a material selected for lower secondary-electron yield relative to said first layer, said second layer being disposed to form an inner surface of said chamber.
13. A device as recited in claim 12, wherein said first layer has electric permittivity greater than about four, and said second layer has a secondary-electron emission yield of less than one for incident electron energies within an operative range.
14. A device as recited in claim 12, comprising a plurality of said gate electrodes.
15. A device as recited in claim 1, wherein said insulating film comprises a substance selected from the group consisting of silicon nitride, aluminum oxide, titanium carbide, tungsten carbide, vanadium diboride, titanium diboride, barium titanate, strontium titanate, barium strontium titanate, and tantalum oxide.
16. A device as recited in claim 1, wherein said insulating film is substantially transparent.
17. A device as recited in claim 1, said chamber having an interior surface, wherein said insulating film is disposed between said interior surface of said chamber and said gate electrode.
18. A device as recited in claim 1, said chamber having an interior surface, wherein said insulating film forms at least a portion of said interior surface of said chamber.
19. A device as recited in claim 1, wherein said anode comprises a phosphor for forming a display device.
20. A device as recited in claim 1, wherein said gate electrode comprises substantially transparent conductive material.
21. A device as recited in claim 1, wherein said gate electrode comprises transparent conductive material selected from the group consisting of indium oxide, tin oxide, and indium-tin oxide.
2. A method for fabricating a field emission device, comprising the steps of:
a) providing an insulating substrate;
b) depositing and patterning a conductive substance to form a gate electrode;
c) depositing a first insulating layer, covering said gate electrode;
d) depositing and patterning a conductive substance to form an emitter;
e) depositing a second insulating layer over said emitter;
f) forming an opening through said second insulating layer, exposing a portion of said emitter without exposing said gate electrode;
g) forming an emitting edge of said exposed portion of said emitter; and
h) providing an anode.
23. An insulated-gate electron field emission device fabricated by the method of claim 22.
24. A method as in claim 22, wherein said insulating-substrate-providing step (a) is performed by:
i) providing a conductive substrate, and
ii) depositing a third insulating layer on said conductive substrate to form said insulating substrate.
5. A method as in claim 22, wherein said emitting-edge-forming step (g) is performed by: removing at least part of said exposed portion of said emitter to form an emitting edge.
26. A method as in claim 22, further comprising the step of removing a portion of said first insulating layer while leaving a quantity of said first insulating layer covering all of said gate electrode.
27. A method as in claim 26, wherein said quantity of said first insulating layer covering all of said gate electrode has a predetermined thickness.
28. A method as in claim 22, further comprising the step of covering said opening to enclose a chamber containing said emitting edge and said anode.
29. A method as in claim 28, further comprising the step of evacuated said chamber.
30. A method as in claim 22, further comprising the step of:
providing means for applying bias voltages to said emitter and said anode, said bias voltages being effective to cause field emission current of electrons from said emitting edge to said anode.
31. A method as in claim 30, further comprising the step of:
providing means for applying a control voltage to said gate electrode for controlling said current.
32. A method as in claim 30, further comprising the step of:
providing means for applying an extraction voltage to said gate electrode for extracting said electrons.
33. A method as in claim 22, wherein said conductive-substance-depositing-and- patterning step (b) is performed by patterning said conductive substance to form a plurality of gate electrodes.
34. A method as in claim 22, wherein said anode-providing step (h) is performed by disposing an anode plate spaced apart from said emitter.
35. A method as in claim 34, wherein said anode-providing step (h) is performed by disposing at least one spacer between said anode plate and said second insulating layer.
36. A method as in claim 34, wherein said anode-providing step (h) is performed by disposing an anode plate coated with luminescent material.
37. A method as in claim 22, further comprising the step of:
disposing a grid between said emitter and said anode.
38. A method as in claim 28, wherein said opening-covering step is preformed by performing the substeps of:
i) depositing and patterning a sacrificial material into said opening, at least filling said opening; ii) depositing a covering layer over said sacrificial material and said second insulating layer, said covering layer being a material selected from a conductor and a luminescent material;
iii) forming an access opening through said covering layer to said sacrificial material;
iv) removing said sacrificial material through said access opening; and
v) providing an effective vacuum environment while depositing a sealant into said access opening to plug said opening,
thereby enclosing a chamber containing said emitting edge and said anode.
39. A method as in claim 38, further comprising the step of:
vi) patterning said sealant.
40. A method as in claim 38, wherein said effective vacuum environment contains a quantity of inert gas.
41. A method as in claim 38, wherein said effective vacuum environment has a residual gas pressure, said residual gas pressure being sufficiently low to allow operation of said device.
42. A method as in claim 38, wherein said selected covering layer material is selected from a transparent conductor and a transparent luminescent material.
3. A method for fabricating a field emission device, comprising the steps of:
a) providing an insulating substrate;
b) depositing and patterning a conductive substance to form a gate electrode;
c) depositing a first insulating layer, covering said gate electrode;
d) depositing and patterning a conductive substance to form an emitter;
e) depositing a second insulating layer over said emitter;
f) forming an opening through said second insulating layer, exposing a portion of said emitter without exposing said gate electrode;
g) removing at least part of said exposed portion of said emitter to form an emitting edge of said exposed portion of said emitter;
h) providing an anode while covering said opening to enclose a chamber containing said emitting edge and said anode;
j) providing means for applying bias voltages to said emitter and said anode, said bias voltages being effective to cause field emission current of electrons from said emitting edge to said anode; and
k) providing means for applying a control voltage to said gate electrode for controlling said current.
44. A method as in claim 43, wherein said anode-providing and opening-covering step (h) is performed by performing the substeps of:
i) depositing and patterning a sacrificial material into said opening, at least filling said opening;
ii) depositing a covering layer over said sacrificial material and said second insulating layer, said covering layer being a material selected from a conductor and a luminescent material; iii) forming an access opening through said covering layer to said sacrificial material;
iv) removing said sacrificial material through said access opening; and
v) providing an effective vacuum environment while depositing a sealant into said access opening to plug said opening,
thereby enclosing a chamber containing said emitting edge and said anode.
45. A method as in claim 22, wherein said opening-forming step (f) includes disposing
said opening in at least partial alignment with at least one of said emitter and said anode.
46. A method as in claim 45, wherein said opening- forming step (f) includes disposing at least two openings in at least partial alignment with said emitter and said anode respectively.
PCT/US2000/020144 1999-07-26 2000-07-24 Insulated-gate electron field emission devices and their fabrication processes WO2001008192A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020017003710A KR20010075311A (en) 1999-07-26 2000-07-24 Insulated-gate electron field emission devices and their fabrication processes
CA002355660A CA2355660A1 (en) 1999-07-26 2000-07-24 Insulated-gate electron field emission devices and their fabrication processes
EP00948927A EP1116255A1 (en) 1999-07-26 2000-07-24 Insulated-gate electron field emission devices and their fabrication processes
JP2001512613A JP2003505843A (en) 1999-07-26 2000-07-24 Insulated gate electron field emission device and manufacturing process thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14557099P 1999-07-26 1999-07-26
US60/145,570 1999-07-26

Publications (1)

Publication Number Publication Date
WO2001008192A1 true WO2001008192A1 (en) 2001-02-01

Family

ID=22513686

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/020144 WO2001008192A1 (en) 1999-07-26 2000-07-24 Insulated-gate electron field emission devices and their fabrication processes

Country Status (6)

Country Link
EP (1) EP1116255A1 (en)
JP (1) JP2003505843A (en)
KR (1) KR20010075311A (en)
CN (1) CN1319246A (en)
CA (1) CA2355660A1 (en)
WO (1) WO2001008192A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008007928A1 (en) * 2006-07-13 2008-01-17 Photegra Corporation Photocathode lighting device, method for manufacturing the same and exposure apparatus using photocathode lighting device
US10089930B2 (en) 2012-11-05 2018-10-02 University Of Florida Research Foundation, Incorporated Brightness compensation in a display

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2635913A1 (en) * 1988-08-31 1990-03-02 Saint Louis Inst FIELD EMISSION DIODE
EP0406886A2 (en) * 1989-07-07 1991-01-09 Matsushita Electric Industrial Co., Ltd. Field-emission type switching device and method of manufacturing it
EP0444670A2 (en) * 1990-03-01 1991-09-04 Matsushita Electric Industrial Co., Ltd. Planar type cold cathode with sharp tip ends and manufacturing method therefor
DE4010909A1 (en) * 1990-04-04 1991-10-10 Siemens Ag Cold-emission protection diode - has air-isolated electrodes with micrometric separation to prevent electrical discharge
US5289086A (en) * 1992-05-04 1994-02-22 Motorola, Inc. Electron device employing a diamond film electron source
WO1995017762A1 (en) * 1993-12-22 1995-06-29 Microelectronics And Computer Technology Corporation Lateral field emitter device and method of manufacturing same
EP0668603A1 (en) * 1994-02-22 1995-08-23 Motorola, Inc. Microelectronic field emission device with breakdown inhibiting insulated gate electrode and method for realization
WO1996036061A1 (en) * 1995-05-08 1996-11-14 Advanced Vision Technologies, Inc. Field emission display cell structure and fabrication process
WO1996042113A1 (en) * 1995-06-13 1996-12-27 Advanced Vision Technologies, Inc. Laminar composite lateral field-emission cathode and fabrication process
WO1997002586A1 (en) * 1995-07-05 1997-01-23 Advanced Vision Technologies, Inc. Direct electron injection field-emission display device and fabrication process
US5604399A (en) * 1995-06-06 1997-02-18 International Business Machines Corporation Optimal gate control design and fabrication method for lateral field emission devices
WO1997009733A1 (en) * 1995-09-06 1997-03-13 Advanced Vision Technologies, Inc. High-frequency field-emission device and fabrication process
US5629580A (en) * 1994-10-28 1997-05-13 International Business Machines Corporation Lateral field emission devices for display elements and methods of fabrication
US5663608A (en) * 1993-03-11 1997-09-02 Fed Corporation Field emission display devices, and field emisssion electron beam source and isolation structure components therefor
US5920148A (en) * 1995-05-08 1999-07-06 Advanced Vision Technologies, Inc. Field emission display cell structure
WO1999040604A1 (en) * 1998-02-09 1999-08-12 Advanced Vision Technologies, Inc. Confined electron field emission device and fabrication process
WO1999049520A1 (en) * 1998-03-25 1999-09-30 Korea Advanced Institute Of Science & Technology Vacuum field transistor
WO1999049492A1 (en) * 1998-03-21 1999-09-30 Korea Advanced Institute Of Science & Technology Line field emitter display

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2635913A1 (en) * 1988-08-31 1990-03-02 Saint Louis Inst FIELD EMISSION DIODE
EP0406886A2 (en) * 1989-07-07 1991-01-09 Matsushita Electric Industrial Co., Ltd. Field-emission type switching device and method of manufacturing it
EP0444670A2 (en) * 1990-03-01 1991-09-04 Matsushita Electric Industrial Co., Ltd. Planar type cold cathode with sharp tip ends and manufacturing method therefor
DE4010909A1 (en) * 1990-04-04 1991-10-10 Siemens Ag Cold-emission protection diode - has air-isolated electrodes with micrometric separation to prevent electrical discharge
US5289086A (en) * 1992-05-04 1994-02-22 Motorola, Inc. Electron device employing a diamond film electron source
US5663608A (en) * 1993-03-11 1997-09-02 Fed Corporation Field emission display devices, and field emisssion electron beam source and isolation structure components therefor
WO1995017762A1 (en) * 1993-12-22 1995-06-29 Microelectronics And Computer Technology Corporation Lateral field emitter device and method of manufacturing same
EP0668603A1 (en) * 1994-02-22 1995-08-23 Motorola, Inc. Microelectronic field emission device with breakdown inhibiting insulated gate electrode and method for realization
US5629580A (en) * 1994-10-28 1997-05-13 International Business Machines Corporation Lateral field emission devices for display elements and methods of fabrication
US5736810A (en) * 1994-10-28 1998-04-07 International Business Machines Corporation Non-evacuated lateral fed employing emitter-anode spacing less than mean free path distance of an electron in air
WO1996036061A1 (en) * 1995-05-08 1996-11-14 Advanced Vision Technologies, Inc. Field emission display cell structure and fabrication process
US5920148A (en) * 1995-05-08 1999-07-06 Advanced Vision Technologies, Inc. Field emission display cell structure
US5604399A (en) * 1995-06-06 1997-02-18 International Business Machines Corporation Optimal gate control design and fabrication method for lateral field emission devices
WO1996042113A1 (en) * 1995-06-13 1996-12-27 Advanced Vision Technologies, Inc. Laminar composite lateral field-emission cathode and fabrication process
WO1997002586A1 (en) * 1995-07-05 1997-01-23 Advanced Vision Technologies, Inc. Direct electron injection field-emission display device and fabrication process
WO1997009733A1 (en) * 1995-09-06 1997-03-13 Advanced Vision Technologies, Inc. High-frequency field-emission device and fabrication process
WO1999040604A1 (en) * 1998-02-09 1999-08-12 Advanced Vision Technologies, Inc. Confined electron field emission device and fabrication process
WO1999049492A1 (en) * 1998-03-21 1999-09-30 Korea Advanced Institute Of Science & Technology Line field emitter display
WO1999049520A1 (en) * 1998-03-25 1999-09-30 Korea Advanced Institute Of Science & Technology Vacuum field transistor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LEGG J D ET AL: "IMPROVED MONOLITHIC VACUUM FIELD EMISSION DIODES", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B,US,AMERICAN INSTITUTE OF PHYSICS. NEW YORK, VOL. 12, NR. 2, PAGE(S) 666-671, 00-03-1994, ISSN: 0734-211X, XP000442751 *
PARK C -M ET AL: "A NOVEL LATERAL FIELD EMITTER TRIODE WITH INSITU VACUUM ENCAPSULATION", INTERNATIONAL ELECTRON DEVICES MEETING (IEDM),US,NEW YORK, IEEE, PAGE(S) 305-308, 08-12-1996, ISBN: 0-7803-3394-2, XP000753768 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008007928A1 (en) * 2006-07-13 2008-01-17 Photegra Corporation Photocathode lighting device, method for manufacturing the same and exposure apparatus using photocathode lighting device
US7944146B2 (en) 2006-07-13 2011-05-17 Photegra Corporation Photocathode lighting device, method for manufacturing the same and exposure apparatus using photocathode lighting device
US10089930B2 (en) 2012-11-05 2018-10-02 University Of Florida Research Foundation, Incorporated Brightness compensation in a display

Also Published As

Publication number Publication date
JP2003505843A (en) 2003-02-12
CN1319246A (en) 2001-10-24
CA2355660A1 (en) 2001-02-01
KR20010075311A (en) 2001-08-09
EP1116255A1 (en) 2001-07-18

Similar Documents

Publication Publication Date Title
US5663608A (en) Field emission display devices, and field emisssion electron beam source and isolation structure components therefor
US5587623A (en) Field emitter structure and method of making the same
US5371431A (en) Vertical microelectronic field emission devices including elongate vertical pillars having resistive bottom portions
US5666019A (en) High-frequency field-emission device
US7710014B2 (en) Electron emission device, electron emission display device using the same and method of manufacturing the same
CA2221443C (en) Fabrication process for hermetically sealed chamber in substrate
US6004830A (en) Fabrication process for confined electron field emission device
US5628663A (en) Fabrication process for high-frequency field-emission device
US5703380A (en) Laminar composite lateral field-emission cathode
WO2001008192A1 (en) Insulated-gate electron field emission devices and their fabrication processes
US6005335A (en) Self-gettering electron field emitter
WO1996018206A1 (en) Vertical field emission devices and methods of fabrication with applications to flat panel displays
US6017257A (en) Fabrication process for self-gettering electron field emitter
EP1055248A1 (en) Confined electron field emission device and fabrication process
EP0827626A1 (en) Field emission display cell structure and fabrication process
US5811929A (en) Lateral-emitter field-emission device with simplified anode
JP4507557B2 (en) Method for manufacturing electron-emitting device and method for manufacturing display device
WO1996042113A1 (en) Laminar composite lateral field-emission cathode and fabrication process
WO1997002586A1 (en) Direct electron injection field-emission display device and fabrication process
CA2221378A1 (en) Lateral-emitter field-emission device with simplified anode and fabrication thereof
WO1999031698A1 (en) Self-gettering electron field emitter and fabrication process

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 00801523.6

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): CA CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

ENP Entry into the national phase

Ref document number: 2355660

Country of ref document: CA

Ref document number: 2355660

Country of ref document: CA

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020017003710

Country of ref document: KR

ENP Entry into the national phase

Ref document number: 2001 512613

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2000948927

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2000948927

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2000948927

Country of ref document: EP