WO2001005123A1 - Appareil et procede de minimisation de perte de donnees entrantes - Google Patents

Appareil et procede de minimisation de perte de donnees entrantes Download PDF

Info

Publication number
WO2001005123A1
WO2001005123A1 PCT/US2000/018976 US0018976W WO0105123A1 WO 2001005123 A1 WO2001005123 A1 WO 2001005123A1 US 0018976 W US0018976 W US 0018976W WO 0105123 A1 WO0105123 A1 WO 0105123A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
data structure
pointer
queue
frames
Prior art date
Application number
PCT/US2000/018976
Other languages
English (en)
Inventor
Dean Schmaltz
Mark Travaglio
Original Assignee
Alteon Web Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alteon Web Systems, Inc. filed Critical Alteon Web Systems, Inc.
Priority to AU60897/00A priority Critical patent/AU6089700A/en
Publication of WO2001005123A1 publication Critical patent/WO2001005123A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload

Definitions

  • the invention relates to the processing and management of data flowing through a computer network switch. More particularly, the invention relates to an apparatus and method for minimizing incoming data loss in output queuing.
  • Computer networks are constructed by tying together a plurality of switching units.
  • the switching units receive data from various sources in a quantum known as frame.
  • frame a quantum known as frame.
  • switching units must be able to route an ever-increasing bandwidth of data. As the bandwidth increases, switching units must be able to handle a greater number of data frames per given unit of time.
  • frame rate increased the hardware foundation of the switching unit would be taxed to such an extent that some frames would inevitably be lost. These lost frames are known as dropped frames.
  • Switches built from these switching units could tolerate dropped frames by using higher-level transport protocols that guarantee the delivery of data.
  • the technology used in switching units has traditionally provided only the lower levels of networking services. In terms of the ISO Stack, switching units would provide only Level 1 and Level 2 services. In the case of dropped frames, the computers using the network would be required to provide thejiigher level services of the ISO Stack in order to ensure delivery of the data frame.
  • Level 3 and Level 4 protocols are used to provide a feature called web cache redirection.
  • a web cache may be located off one port of the switch while an actual web page that is being cached may exist off a different port. If a frame containing a request for the given web page comes into the switch, a layer-2 switch would always forward the request to the port where the actual web page is located, it does not understand the concept of a web cache and never looks deep enough into the frame to determine that it is a web page request. A properly configured layer-4 switch would route the frame to the web cache.
  • the web cache is generally located closer to the requestors than the actual web pages within the global network, which results in an overall reduction in network traffic and faster response time to the client.
  • the switch is configured for client ports and server ports.
  • the clients make requests for a given service that may be satisfied b y any one of a group of physical servers.
  • the switch balances the requests across the servers according to an algorithm selected by the user. Examples include round robin and least connections.
  • This layer-4 feature improves response time to the clients by making more efficient use of a bank of servers. It does not, however, reduce overall network traffic.
  • Relegating the Level 3 and Level 4 services embodied in these types of features to the switching units is highly desirous because the amount of data traffic in the overall network can be reduced. This result is achieved because dropped frames can be handled directly between the two switching units that are effecting the data connection rather than between two client computers and the expanse of the entire network.
  • the methods and apparatus described herein implement a novel and unique facility that provides for the management of data frames arriving at a switching unit.
  • the switching unit uses header buffers to coordinate the routing of data frames to the proper output queue.
  • the new switching unit creates data structures in external memory and stores newly arriving data frames in the external memory whenever there are no header buffers available. As header buffers are freed, the new switching unit reads the header portion of the data frames stored in external memory and writes the header portion into an available header buffer.
  • Fig. 1 is a block diagram that depicts a typical network topology and is used to place the present invention into context;
  • Fig. 2 is a data flow diagram that depicts the data flow of data frames flowing through a switch unit
  • Fig. 3 is a data structure diagram that illustrates the method used to create expanded storage for data frames when header buffers are not available;
  • Fig. 4 is a functional block diagram that presents a block diagram of a queue switch according to the invention.
  • the invention is a method and an apparatus that minimizes the loss of data flowing through a switching unit.
  • the apparatus is preferably embodied as a queue switch.
  • Fig. 1 depicts the interconnection of a plurality of switching units 5 through the use of communication ports 10 from each switching unit to other switching units. By connecting these switching units to each other in this manner, a wide area network 15 is realized.
  • Other clusters of switching units, or lower capability hubs and routers can be interconnected to create local area networks 20. Attached to these local area networks 20 are a plurality of network clients.
  • a sender 25 and a receiver 30 constitute two of a vast potential of network clients that can be connected to disperse local area networks that are then connected together by the wide area network.
  • the sender 25 can send frames of data to any other client connected to any appendage of the local or extended network.
  • the switching units 5 play a pivotal role in routing the data frames dispatched by the sender 25.
  • the function provided by the switching units 5 is to determine, on a frame by frame basis, where to direct the frame so as to ensure delivery to the receiver 30.
  • each switching unit 5 normally receive data from the sender 25 on one physical port, however this does not need to be the case. What is also apparent is that each switching unit 5 has a plurality of ports, each capable of receiving inputs of data frames.
  • Fig. 2 depicts how data frames flow through each switching unit 5.
  • data frames arrive via a plurality of input ports.
  • Each input port is serviced by a corresponding first-in-first-out (FIFO) buffer 35.
  • the input FIFO's 35 receive data frames from external network connections and provide the elasticity needed to assimilate the aggregate data throughput arriving at the port.
  • a forwarding process is executed that examines each data frame and determines to which output queue 45 it is to be directed. Once the data frame is directed to an output queue 45, it is scheduled to be transmitted to the next switching unit, or router in the case of a connection to a local area network.
  • the source of routing information that the forwarding process 40 uses to determine the queue each data frame must be delivered is stored in tabular databases.
  • the forwarding process 40 creates and maintains a dynamic map, referred to herein as a forwarding database 50.
  • the forwarding process 40 derives knowledge about the entire network, both the wide area and the plurality of local networks, as it seeks to optimize connection and routing tables. This activity requires significant processing resources to achieve.
  • Another source of routing information is a static map that is referred to herein as a switch configuration database 55.
  • the switch configuration 55 is developed through apriori knowledge of the network configuration and is entered directly into the switching unit 5.
  • the forwarding process 40 uses sophisticated algorithms to learn about the topology of the extended network to maintain the forwarding data base 50. All layer-2 switches have a learning algorithm for layer-2 network addresses, and maintain a layer-2 forwarding database. Switches that perform layer-3 and layer-4 functions maintain extra tables that track TCP/IP sessions and include client and server information.
  • the switch When a frame arrives from the input FIFO of a layer-2 switch, the switch searches the database for the given destination address. If successful, the search returns the output port for the frame and the switch places the frame on the associated output queue. If unsuccessful the switch floods the frame to all ports except the one it came in on.
  • Prior art includes switches that perform this simple forwarding algorithm at full wire speed.
  • the forwarding engine When a frame arrives from the input FIFO of a layer-4 switch, the forwarding engine has a much larger job. If a client frame indicates the start of a new TCP/IP session, the switch must choose an appropriate server and augment the layer-4 database to include the new session before placing the frame onto the selected output queue. The server selection is based on the switch configuration and in some cases server loading information also kept by the switch. Both web cache redirection and server load balancing, discussed above, require this type of processing.
  • the forwarding process 40 uses these complex algorithms to determine to which output queue each frame must be directed.
  • these algorithms enable the forwarding process 40 to anticipate the load on network servers that source the data frames and to track the utilization of communication channels that interconnect the plurality of switching units and routers that form the extended network. These algorithms work collectively to make the extended network as efficient as possible.
  • the forwarding algorithms have become so complex that the forwarding process 40 can not be executed for each arriving frame in real time. As a result, data frames can not be routed and are consequently dropped.
  • Incoming data frames are split into a header and a payload.
  • the header contains most of the information required to forward the frame.
  • the payload contains the remainder of the frame.
  • Prior art switching units rely on a series of header buffers that temporarily store incoming frame headers while the forwarding process executes. These header buffers receive data frames from a plurality of input FIFOs 35 and present the data frames to the forwarding process 40.
  • the availability of header buffers is limited and their parallel and high-speed nature precludes mass replication of this resource. As the rate of incoming data frames peaks, the forwarding process 40 can not free header buffers fast enough to accommodate newly arriving data frames.
  • Fig. 3 illustrates one of the main novelties of the invention.
  • the present switching unit provides for storage of data frames in an external memory element 55 and the ability to read the frame headers back when header buffers eventually become free.
  • the plurality of header buffers 60 are actually internal to an application specific integrated circuit (ASIC) referred to herein as a network engine 65.
  • the network engine 65 further comprises a forwarding engine 67 that performs the forwarding process 40.
  • Specialized hardware embodied in the network engine 65, manages the creation of data structures in the external memory 55. Each time a data frame arrives, it is forwarded to one of the plurality of header buffers 60. In the preferred embodiment of the invention, a data structure is also created in the external memory 55 and the incoming data frame stored therein as well. This is optional. What is important, though, is that when a header buffer is not available, the external data structure must be created and the incoming data frame must be stored therein to preclude its loss.
  • the specialized hardware manages data structures in a traditional chained link- list form.
  • the first data structure When the first data structure is created it is identified by it's address and that address is stored in an overflow FIFO head-pointer referred to herein a chain head-pointer 75.
  • Each data structure 77 is comprised of three major fields: a queue descriptor 80, a frame data 85, and a next data structure pointer 90.
  • the queue descriptor 80 is used in identifying and managing the routing of the data frame.
  • Frame data 85 are used to store the data from the incoming data frame.
  • the next data structure pointer 90 is used to identify the next data structure in the chain.
  • the next data structure pointer of the last data structure in the chain is set to a null value as an indication that that particular data structure is the last in the chain.
  • the specialized hardware that manages the creation of new data structures in the external memory 55 also monitors the availability of header buffers 60. When a header buffer becomes available, the specialized hardware transfers the frame data from the first data structure in the chain to that buffer. It does so by using a chain head pointer 75 to identify the first data structure in the chain and then it transfers the contents of the header portion of the frame data field
  • the specialized hardware reads the value of next data structure pointer 90 from the first data structure and stores that value in the chain head-pointer 75. This makes the next data structure, pointed to by the next pointer, the first data structure in the chain.
  • the data structure that is used as the source of data for an available header buffer is not immediately destroyed. It is retained in the external memory and the address of this data structure is then used to point to the frame data when it is assigned to an output queue.
  • Fig. 4 depicts the preferred embodiment of the method of the invention implemented as a hardware apparatus.
  • a network engine 65 and the external memory 55 collectively comprise an output queuing switch 135.
  • the network engine 65 comprises a network receiver circuit 100, a wire input FIFO 105, a forwarding engine 110, a queue linker 120, a switch queue 125, a switch media access controller (MAC) 130, and a memory arbiter 115.
  • the external memory 55 is preferably a high-speed random access memory, such as a synchronous dynamic random access memory (SDRAM).
  • SDRAM synchronous dynamic random access memory
  • the network receive circuit 100 interfaces with the actual communication channel that accepts data frames from an external source. This could be an Ethernet connection, a fiber optic receiver, or a modem or the like.
  • the network receive circuit 100 accepts the data frames and presents them to a wire-input FIFO.
  • the wire input FIFO 105 receives data frames from the network receive circuit 100 and immediately attempts to transfer the data to a header buffer.
  • Header buffers are depicted in Fig. 4 as a header buffer stack 106.
  • the wire input FIFO 105 comprises the specialized hardware that manages the creation of data structures in external memory as discussed above.
  • the wire input FIFO 105 creates a data structure in the external memory 55 according to the method of the invention disclosed herein. Once the data structure is created, the data frame is stored in the data structure until a header buffer becomes available. Once a header buffer becomes available, wire input FIFO 105 reads the first data frame from external memory 55 and transfers it to the available header buffer.
  • the forwarding engine 110 reads the information in the data frame, including source and destination addresses and IP protocol data that it needs to forward the data frame. Results of the forwarding process are delivered by the forwarding engine 110 back to the wire input FIFO 105.
  • the wire input FIFO 105 sends the pointer to the data frame, located in external memory, to the queue linker 120.
  • the queue linker 120 reads a descriptor 80 to determine to which output queue the data frame is to be routed and initiates the switch queue 125.
  • the queue linker 120 uses information in the descriptor 80 to determine which output queue to link the frame to.
  • the queue linker 120 performs the link operation and notifies the switch queue 125 by means of an initiation signal that the output queue is no longer empty.
  • the switch queue After receiving an initiation signal from the queue linker 120, the switch queue
  • the switch 125 de-links frames from non-empty output queues and retrieves the data frame from the external memory 55.
  • the switch queue 125 then directs the data frame to the switch media access controller 130.
  • the switch media access controller 130 then forwards the data frame to one of a plurality of output FIFOs that it maintains and manages.
  • the switch media access controller 130 then delivers the queues to a switch port that puts the data frames, now queued in a plurality of output FIFOs, out onto a communication channel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Comme des autocommutateurs informatisés présentent des capacités supplémentaires, y compris une gestion des niveaux 3 et 4 et des transferts de données, les bases de matériel sur lesquelles ils reposent sont dépassées par la quantité constamment croissante de données qu'elles doivent acheminer. Comme une unité de commutation reçoit des trames de données, un processus de réacheminement est utilisé pour acheminer les trames d'un des nombreux canaux de sortie. Des niveaux plus élevés de services de protocole exigent des ressources informatiques supplémentaires. Avec une augmentation du volume de données, le processus de réacheminement ne peut pas être réalisé en temps réel. Avec la défaillance dudit processus, des trames de données ne peuvent pas être acheminées et sont écartées du flux. La disponibilité des tampons d'en-têtes constitue un facteur prédominant dans le nombre de trames écartées par unité de temps. L'appareil décrit dans la présente invention contrôle la disponibilité desdits tampons. Lorsque ceux-ci ne sont pas disponibles, des trames de données entrantes sont stockées dans une mémoire externe. A mesure que les tampons d'en-têtes sont libérés par le processus de réacheminement, du matériel spécial déplace la partie d'en-tête des trames de données stockées dans la mémoire externe dans un tampon d'en-tête disponible.
PCT/US2000/018976 1999-07-13 2000-07-12 Appareil et procede de minimisation de perte de donnees entrantes WO2001005123A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU60897/00A AU6089700A (en) 1999-07-13 2000-07-12 Apparatus and method to minimize incoming data loss

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14344699P 1999-07-13 1999-07-13
US60/143,446 1999-07-13

Publications (1)

Publication Number Publication Date
WO2001005123A1 true WO2001005123A1 (fr) 2001-01-18

Family

ID=22504116

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/018976 WO2001005123A1 (fr) 1999-07-13 2000-07-12 Appareil et procede de minimisation de perte de donnees entrantes

Country Status (2)

Country Link
AU (1) AU6089700A (fr)
WO (1) WO2001005123A1 (fr)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6389479B1 (en) 1997-10-14 2002-05-14 Alacritech, Inc. Intelligent network interface device and system for accelerated communication
US6427173B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Intelligent network interfaced device and system for accelerated communication
US6427171B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6434620B1 (en) 1998-08-27 2002-08-13 Alacritech, Inc. TCP/IP offload network interface device
US6591302B2 (en) 1997-10-14 2003-07-08 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US6658480B2 (en) 1997-10-14 2003-12-02 Alacritech, Inc. Intelligent network interface system and method for accelerated protocol processing
US6687758B2 (en) 2001-03-07 2004-02-03 Alacritech, Inc. Port aggregation for network connections that are offloaded to network interface devices
US6697868B2 (en) 2000-02-28 2004-02-24 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6751665B2 (en) 2002-10-18 2004-06-15 Alacritech, Inc. Providing window updates from a computer to a network interface device
US6757746B2 (en) 1997-10-14 2004-06-29 Alacritech, Inc. Obtaining a destination address so that a network interface device can write network data without headers directly into host memory
US6807581B1 (en) 2000-09-29 2004-10-19 Alacritech, Inc. Intelligent network storage interface system
US6965941B2 (en) 1997-10-14 2005-11-15 Alacritech, Inc. Transmit fast-path processing on TCP/IP offload network interface device
WO2006015911A1 (fr) * 2004-08-05 2006-02-16 Robert Bosch Gmbh Procede et dispositif permettant d'acceder a des donnees d'une memoire de messages d'un module de communication
US7042898B2 (en) 1997-10-14 2006-05-09 Alacritech, Inc. Reducing delays associated with inserting a checksum into a network message
US7237036B2 (en) 1997-10-14 2007-06-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding a TCP connection
US7284070B2 (en) 1997-10-14 2007-10-16 Alacritech, Inc. TCP offload network interface device
US8019901B2 (en) 2000-09-29 2011-09-13 Alacritech, Inc. Intelligent network storage interface system
US8893159B1 (en) 2008-04-01 2014-11-18 Alacritech, Inc. Accelerating data transfer in a virtual computer system with tightly coupled TCP connections
US9055104B2 (en) 2002-04-22 2015-06-09 Alacritech, Inc. Freeing transmit memory on a network interface device prior to receiving an acknowledgment that transmit data has been received by a remote device
US9306793B1 (en) 2008-10-22 2016-04-05 Alacritech, Inc. TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies
US9413788B1 (en) 2008-07-31 2016-08-09 Alacritech, Inc. TCP offload send optimization

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398245A (en) * 1991-10-04 1995-03-14 Bay Networks, Inc. Packet processing method and apparatus
US5634015A (en) * 1991-02-06 1997-05-27 Ibm Corporation Generic high bandwidth adapter providing data communications between diverse communication networks and computer system
EP0853404A2 (fr) * 1997-01-14 1998-07-15 Digital Vision Laboratories Corporation Procédé et dispositif pour relais de données

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5634015A (en) * 1991-02-06 1997-05-27 Ibm Corporation Generic high bandwidth adapter providing data communications between diverse communication networks and computer system
US5398245A (en) * 1991-10-04 1995-03-14 Bay Networks, Inc. Packet processing method and apparatus
EP0853404A2 (fr) * 1997-01-14 1998-07-15 Digital Vision Laboratories Corporation Procédé et dispositif pour relais de données

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
RUTSCHE E: "THE ARCHITECTURE OF A GB/S MULTIMEDIA PROTOCOL ADAPTER", COMPUTER COMMUNICATIONS REVIEW,US,ASSOCIATION FOR COMPUTING MACHINERY. NEW YORK, vol. 23, no. 3, 1 July 1993 (1993-07-01), pages 59 - 68, XP000412143, ISSN: 0146-4833 *

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8447803B2 (en) 1997-10-14 2013-05-21 Alacritech, Inc. Method and apparatus for distributing network traffic processing on a multiprocessor computer
US6757746B2 (en) 1997-10-14 2004-06-29 Alacritech, Inc. Obtaining a destination address so that a network interface device can write network data without headers directly into host memory
US7042898B2 (en) 1997-10-14 2006-05-09 Alacritech, Inc. Reducing delays associated with inserting a checksum into a network message
US8856379B2 (en) 1997-10-14 2014-10-07 A-Tech Llc Intelligent network interface system and method for protocol processing
US6591302B2 (en) 1997-10-14 2003-07-08 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US6658480B2 (en) 1997-10-14 2003-12-02 Alacritech, Inc. Intelligent network interface system and method for accelerated protocol processing
US8782199B2 (en) 1997-10-14 2014-07-15 A-Tech Llc Parsing a packet header
US9009223B2 (en) 1997-10-14 2015-04-14 Alacritech, Inc. Method and apparatus for processing received network packets on a network interface for a computer
US7284070B2 (en) 1997-10-14 2007-10-16 Alacritech, Inc. TCP offload network interface device
US8131880B2 (en) 1997-10-14 2012-03-06 Alacritech, Inc. Intelligent network interface device and system for accelerated communication
US6427173B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Intelligent network interfaced device and system for accelerated communication
US8631140B2 (en) 1997-10-14 2014-01-14 Alacritech, Inc. Intelligent network interface system and method for accelerated protocol processing
US6965941B2 (en) 1997-10-14 2005-11-15 Alacritech, Inc. Transmit fast-path processing on TCP/IP offload network interface device
US7237036B2 (en) 1997-10-14 2007-06-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding a TCP connection
US6427171B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6389479B1 (en) 1997-10-14 2002-05-14 Alacritech, Inc. Intelligent network interface device and system for accelerated communication
US6434620B1 (en) 1998-08-27 2002-08-13 Alacritech, Inc. TCP/IP offload network interface device
US6697868B2 (en) 2000-02-28 2004-02-24 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6807581B1 (en) 2000-09-29 2004-10-19 Alacritech, Inc. Intelligent network storage interface system
US8019901B2 (en) 2000-09-29 2011-09-13 Alacritech, Inc. Intelligent network storage interface system
US6687758B2 (en) 2001-03-07 2004-02-03 Alacritech, Inc. Port aggregation for network connections that are offloaded to network interface devices
US6938092B2 (en) 2001-03-07 2005-08-30 Alacritech, Inc. TCP offload device that load balances and fails-over between aggregated ports having different MAC addresses
US9055104B2 (en) 2002-04-22 2015-06-09 Alacritech, Inc. Freeing transmit memory on a network interface device prior to receiving an acknowledgment that transmit data has been received by a remote device
US6751665B2 (en) 2002-10-18 2004-06-15 Alacritech, Inc. Providing window updates from a computer to a network interface device
US8095740B2 (en) 2004-08-05 2012-01-10 Robert Bosch Gmbh Method and apparatus for accessing data of a message memory of a communication module
KR100970300B1 (ko) * 2004-08-05 2010-07-15 로베르트 보쉬 게엠베하 통신 모듈의 메시지 메모리의 데이터를 액세스하기 위한 방법 및 장치
WO2006015911A1 (fr) * 2004-08-05 2006-02-16 Robert Bosch Gmbh Procede et dispositif permettant d'acceder a des donnees d'une memoire de messages d'un module de communication
US8893159B1 (en) 2008-04-01 2014-11-18 Alacritech, Inc. Accelerating data transfer in a virtual computer system with tightly coupled TCP connections
US9667729B1 (en) 2008-07-31 2017-05-30 Alacritech, Inc. TCP offload send optimization
US9413788B1 (en) 2008-07-31 2016-08-09 Alacritech, Inc. TCP offload send optimization
US9306793B1 (en) 2008-10-22 2016-04-05 Alacritech, Inc. TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies

Also Published As

Publication number Publication date
AU6089700A (en) 2001-01-30

Similar Documents

Publication Publication Date Title
WO2001005123A1 (fr) Appareil et procede de minimisation de perte de donnees entrantes
US6246680B1 (en) Highly integrated multi-layer switch element architecture
US6731631B1 (en) System, method and article of manufacture for updating a switching table in a switch fabric chipset system
US6804731B1 (en) System, method and article of manufacture for storing an incoming datagram in switch matrix in a switch fabric chipset system
US6424621B1 (en) Software interface between switching module and operating system of a data packet switching and load balancing system
US6847645B1 (en) Method and apparatus for controlling packet header buffer wrap around in a forwarding engine of an intermediate network node
US6246684B1 (en) Method and apparatus for re-ordering data packets in a network environment
CN113728315A (zh) 促进网络接口控制器(nic)中的有效消息匹配的系统和方法
US6510164B1 (en) User-level dedicated interface for IP applications in a data packet switching and load balancing system
US6272136B1 (en) Pseudo-interface between control and switching modules of a data packet switching and load balancing system
EP1782602B1 (fr) Appareil et procede de support de mise en place de connexion dans un dechargement de traitement de protocole de reseau
JP4068166B2 (ja) 高性能多層スイッチ要素用探索エンジン・アーキテクチャ
EP1546843B1 (fr) Traitement de protocole de maintien d'état à débit binaire élevé
EP1784735B1 (fr) Appareil et procede permettant de prendre en charge la gestion de memoire dans le dechargement de traitement de protocole de reseau
US8874797B2 (en) Network interface for use in parallel computing systems
US6604147B1 (en) Scalable IP edge router
US20020061022A1 (en) Network switch using network processor and methods
US5418781A (en) Architecture for maintaining the sequence of packet cells transmitted over a multicast, cell-switched network
US7406083B2 (en) Method for preserving the order of data packets processed along different processing paths
US20030115350A1 (en) System and method for efficient handling of network data
WO2000030322A2 (fr) Systeme informatique de commutation de paquets a equilibrage des charges utilisant une architecture multiprocesseurs a usages multiples
WO1999000939A1 (fr) Gestion de memoire partagee dans un element de reseau commute
US7346067B2 (en) High efficiency data buffering in a computer network device
US8099515B2 (en) Context switched route look up key engine
US6724759B1 (en) System, method and article of manufacture for transferring a packet from a port controller to a switch fabric in a switch fabric chipset system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP