WO2001001648A1

WO2001001648A1 - Chirp waveform decoding system

Info

Publication number: WO2001001648A1
Application number: PCT/GB2000/001830
Authority: WO
Inventors: Richard L. Anglin
Original assignee: Powell, Stephen, David
Priority date: 1999-06-25
Filing date: 2000-05-12
Publication date: 2001-01-04
Also published as: GB2367465A; GB0130960D0; AU5082300A

Abstract

Before information is extracted from incoming chirp radio frequency waveforms (28), they are subjected to noise removal, e.g. by a Kalman fitter (40), amplitude normalization and synchronization. The nature of the information-extraction step depends upon the particular form of chirp waveform (28) received. In one method, fo is subtracted from the waveform (28) to down convert it to a series of Up and Down pulses, or alternatively Up-Down and Down-Up pulses, which are supplied to a frequency-to-voltage converter (56); the output of the converter is in the form of triangular pulses which are then differentiated (60) to produce positive or negative square pulses. In another proposed method the information-extraction step involves determining the zero crossings of received chirp radio frequency waveforms; an alternative method involves integrating and a further method involves a delay of the received chirp signal.

Description

Chirp Waveform Decoding System

TECHNICAL FIELD

The present invention relates to the field of digital communications. More particularly, this invention provides novel methods and apparatus for detecting a transmitted waveform which utilizes frequency chirps to create a binary or alphanumeric or special character data structure. Utilization of the present invention will enable efficient high bandwidth digital wireless communications leading to new markets for interactive wireless communications services, including voice, data, image, compressed video and Internet access.

BACKGROUND ART

Wireless communication systems such as cellular, Personal Communication System ("PCS") and satellite systems such as Iridium and American Mobile Satellite Corporation ("AMSC") have all been implemented and deployed to enable mobile voice communications. Technologies for these systems, whether analog or digital, have evolved from the voice handling requirements of the Public Switch Telephone Network ("PSTN"). Virtually all of these systems are narrowband because of the limited radio frequency ("RF") spectrum available to each service. The channels are sized to the minimum bandwidth required to support "acceptable" voice communications. "Acceptability" means intelligibility and clarity, not necessarily the "toll" quality of the PSTN. All of these systems are symmetric, that is, two channels of equal size are required to support full-duplex voice communications. The system parameters that are required to deliver voice services make handling digital data communications difficult. All of these systems accommodate wireless digital data communications, but the data throughput rates are very low and the additional equipment required can be complex because of the network switching requirements.

The advent of the Internet has ushered a fundamental paradigm shift in the way in which information is collected, stored, displayed, accessed and distributed. The Internet has taken over, with the

Web browser rapidly becoming the user template for communications, information and even entertainment. This feature-rich multimedia environment has led to bandwidth demands which traditional wireline telecommunications networks struggle today to meet.

For example, information formerly presented in catalogs resides in World Wide Web ("WWW" or "Web") sites and is available for viewing via a Web browser, printing to a local printer or downloading as a file to a local personal computer ("PC"). Electronic mail ("e-mail") has become the de rigeur for business and is widely used by consumers. The historical model of centralized corporate information databases has been replaced by dispersed local servers interconnected via high-speed telecommunications networks. The increasing mobility and globalization of business requires virtually instantaneous access to this information wherever it may reside. Mobile workers are expected to have the same access as workers in fixed locations. Go to any major airport in the world and observe countless travelers toting laptop PCs. In seeking to make waiting time productive they are constantly looking for data ports to plug in their laptops to access the Internet.

Wireless communications carriers, terrestrial and satellite, are today seeking technologies to support this major paradigm shift to the Internet. They are constrained, however, by the narrowband, low speed, symmetrical character of deployed wireless communication systems.

Eavesdrop on any conversation about the Internet and the topic of access speed invariably comes up. The great majority of people are talking about access speed at their business or home. Access speed is addictive. Once having access to higher Internet speeds, users resist, often to the point of avoidance, lower speed technologies (even for just e-mail). When it comes to wireless Internet access there are no high speed alternatives.

Consider a typical mobile Internet session. The user logs onto the Internet and first requests download of his or her e-mail messages. The request to the electronic mail server is a very small message. The download can be quick if there are only a few messages and the messages themselves are small. However, if there are a large number of messages or the messages contain a large amount of text, downloading can take a very long time. Downloads are even slower if the messages have files appended to them, and slower still if the files are graphic images or video.

This user is a corporate salesperson and needs to download a product brochure. Again, the request to the database server is a small message, but the download file is large. The download process maybe extremely slow if the file contains embedded images in color. There is a tremendous and rapidly increasing need for a wireless communication system to support high speed mobile digital data communications. The desired system should be asymmetric; providing high bandwidth for downloading information and small bandwidth for uploading message requests and electronic mail. However, high bandwidth should also be available if the user needs to upload a large file. Thus, the desired wireless digital data communications system should be able to dynamically allocate bandwidth to users to accommodate their particular requirements at any given point in time. DISCLOSURE OF THE INVENTION

The present invention includes an antenna and an RF receiver for receiving a transmitted chiφ RF waveform signal. The received chiφ RF waveform contains noise which must be separated from the signal to extract useful information. In one embodiment of the invention, the RF noise is removed from the received chiφ RF waveform using a Kalman filter. This filtering process results in a filtered RF waveform. At this point, useful information is extracted from the filtered waveform by employing one of several novel alternative detection methods. In one embodiment of the disclosed invention, after the detection step is complete, the filtered RF waveform is converted to a series of intermediate frequency ("IF") pulses that correlate with the original chiφs that were transmitted to the RF receiver. The IF pulses are then conditioned to a series of square wave signals, yielding a digital output which conveys intelligible information; the same information that was transmitted.

An appreciation of the other aims and objectives of the present invention and a more complete and comprehensive understanding of this invention may be obtained by studying the following description of preferred and alternative embodiments, and by referring to the accompanying drawings.

A BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a linear frequency up-chiφ and a down-chiφ.

Figure 2 shows a linear frequency up-down-chiφ and a down-up-chiφ.

Figure 3 shows a linear frequency plus-chiφ and a linear frequency minus-up-chiφ.

Figure 4 shows a functional block diagram of the Chiφing Digital Wireless System. Figure 5 shows a functional block diagram of a chiφing receiver system.

Figure 6 shows linear frequency chiφ waveforms.

Figure 7 shows an embodiment of the disclosed invention comprising frequency-to-voltage detection for up-chiφs and down-chiφs.

Figure 8 shows an embodiment of the disclosed invention comprising frequency-to-voltage detection for up-down-chiφs and down-up-chiφs.

Figure 9 shows an embodiment of the disclosed invention comprising a digital method of detection by comparing patterns of zero crossings of waveforms.

Figure 10 shows an embodiment of the disclosed invention comprising an analog method of detection by comparing patterns of zero crossings of waveforms. Figure 1 1 shows an embodiment of the disclosed invention comprising a digital method of detection by comparing the shortest and longest zero crossing intervals of waveforms.

Figure 12 shows an embodiment of the disclosed invention comprising an analog method of detection by comparing the shortest and longest zero crossing intervals of waveforms.

Figure 13 shows an embodiment of the disclosed invention comprising integration of the waveforms. Figure 14 shows an embodiment of the disclosed invention comprising rectification and integration of the waveforms.

Figure 15 shows an embodiment of the disclosed invention comprising subtractive integration and comparison to known waveform. Figure 16 shows an embodiment of the disclosed invention comprising subtractive integration and comparison to known waveform using a complementary output pulse.

Figure 17 shows an embodiment of the disclosed invention comprising additive integration and comparison to known waveform.

Figure 18 shows an embodiment of the disclosed invention comprising additive integration and comparison to known waveform using a complementary output pulse.

Figure 19 shows an embodiment of the disclosed invention comprising out of phase chiφs.

Figure 20 shows an embodiment of the disclosed invention comprising time phased reception.

Figure 21 shows an embodiment of the disclosed invention for very short chiφ waveforms.

Figure 22 shows an embodiment of the disclosed invention comprising multiple frequency down shifting.

Figure 23 shows an embodiment of the disclosed invention comprising a sloped filter for detecting up-chiφs and down-chiφs.

Figure 24 shows an embodiment of the disclosed invention comprising a sloped filter for detecting up-down-chiφs and down-up-chiφs. Figure 25 shows an embodiment of the disclosed invention comprising delay elements to detect up-chiφs and down-chiφs.

Figure 26 shows an embodiment of the disclosed invention comprising delay elements for detecting up-down-chiφs and down-up-chiφs.

BEST MODE FOR CARRYING OUT THE INVENTION

An Overview of the Invention

A "chiφ" is generally defined as a waveform or propagated signal which may be characterized by a mathematical function. In one embodiment of the invention, the mathematical function is a relationship between the frequency of the chiφ and time. The chiφ interval ("T") is defined as the time between the beginning of one chiφ and the beginning of the succeeding chiφ. The chiφ period ("t") is defined as the duration of a chiφ.

Impression of a digital structure to such a signal can be accomplished by defining a binary one ( 1 ) to be an up-chiφ and a binary zero (0) to be a down-chiφ, vice versa, or combination thereof. A digital signal can then be sent using a stream of up- and down-chiφs. The data rate for the digital stream is determined by the time interval between the start of successive chiφs. Very high data rates can be achieved with today's semiconductor technology. The receiver of the information has a priori knowledge of the transmitted waveform. This means that a great deal of dispersion and noise can be tolerated in conjunction with the signal.

One of the principal advantages of the chiφing technology is that the digital information is encoded continuously across the chiφ allowing more robust detection techniques that are not dependent on the detection of the edge of the transition from a "0" to a "1" or from a "1" to a "0". In standard digital encoding techniques the faster the attempt to make the transition, the shaφer the edge, the more likely that the edge will be blurred, missed or improperly identified, and information will be lost. By encoding the information in a continuous manner in the up or down nature of the chiφ it is less likely that the transition from a " 1 " to a "0" or from a "0" to a " 1 " will be missed, since the detector has more chances and time to discover and to identify the distinction. The inventions disclosed in this Specification all take advantage of this fact. A number of alternative methods are available to detect the transmitted waveform.

Preferred & Alternative Embodiments of the Invention

Figure 1 shows a linear frequency up-chiφ 10 and a linear frequency down-chiφ 12. These chiφs are defined by their frequency change ("Δf ') and chiφ period ("t"). Figure 2 shows a linear frequency up-down-chiφ 14 and a linear frequency down-up-chiφ 16.

These chiφs are also defined by their frequency change ("Δf ') and chiφ period ("t").

Figure 3 shows a linear frequency plus-chiφ 18 and a linear frequency minus-up-chiφ 20. These chiφs are likewise defined by their frequency change ("Δf ') and chiφ period ("t").

Figure 4 shows a functional block diagram of the invention 22 disclosed in the Chiφing Digital Wireless System as shown in pending U.S. Patent Application Serial No. 09/212,339. A digital input 24 is fed to a chiφing transmitter system 26 that generates the chiφing radio frequency ("RF") waveform 28.

The transmitted chiφing radio frequency waveform 28 is received by a chiφing receiver system 30 which generates a digital output 32 that recreates the digital input 24.

Figure 5 shows a functional block diagram of a chiφing receiver system 30. The chiφing RF waveform 38 is received by an antenna 34 and RF receiver 36. The received RF input waveform 38 comprises both the RF output waveform 28 as well as RF noise resulting from the wireless transmission. The RF noise is removed from the RF input 38 using a Kalman filter 40 resulting in a filtered RF input waveform 42. The filtered RF input waveform 42 is detected using one or more of the methods disclosed herein. The result is intermediate frequency ("IF") pulses 46 that correlate with input chiφs. The IF pulses 46 are conditioned 48, that is, conformed to square wave, to yield the digital output 32.

Detection Methods

All methods for detecting chiφs assume a base frequency with a chiφ added. The base frequency is fo; the difference between the base frequency and the upper chiφ frequency is Δf. For example, a chiφ could go from 912 MHz to 913 MHz, so the signal could be thought of as a 912 MHz base signal, fo, with a 0-to- 1 MHz, Δf, chiφ added to the base signal. Note that this is, in theory, no different from a chiφ that goes from fo to fo + Δf. Also note that, in this notation, Δf is always positive. The time interval over which the frequency changes from 0 to Δf is the chiφ period t.

Figure 6 shows three (3) linear chiφ (1,0) waveform pairs for digital data transmission: Up-Chiφ ("U") / Down Chiφ ("D") 50,

Up-Down-Chiφ ("UD") / Down-Up-Chiφ ("DU") 52, and

Plus-Chiφ ("P") / Minus-Chiφ ("M") 54.

Figure 1 shows a linear frequency up-chiφ 10 and a linear frequency down-chiφ 12. The up-chiφ ("U") goes from 0 to Δf in time t. The Down-Chiφ ("D") goes from Δf to 0 in a time t. Figure 2 shows a linear frequency up-down-chiφ 14 and a linear frequency down-up-chiφ 16.

The Up-Down-Chiφ ("UD") 14 goes from 0 to Δf in time t/2 and then immediately from Δf to 0 in time t/2 so that the entire Up-Down-Chiφ 14 occurs in a time t. The Down-Up-Chiφ ("DU") 16 goes from Δf to 0 in a time t/2 and then immediately from 0 to Δf in a time t/2 so that the entire Down-Up-Chiφ 16 occurs in time t. Figure 3 shows a linear frequency Plus-Chiφ ("P") 18 and a linear frequency Minus-Chiφ ("M")

20. The Plus-Chiφ 18 can be either an Up-Chiφ or a Down-Chiφ while the Minus-Chirp is its complement, that is, the phase of the Minus-Chiφ lags the phase of the Plus-Chiφ by one hundred eighty degrees (180°). The result of this is that adding a Plus-Chiφ 18 to a Minus-Chiφ 20 gives zero. The two signals are in that sense orthogonal. In this Specification and in the Claims that follow, the Plus-Chiφ ("P") 18 is an Up-Chirp ("U") and the Minus-Chiφ ("M") 20 is the compliment of an Up-Chiφ in all of the figures. All of the methods discussed in this Specification that apply to Plus(Up)Chirp / Minus(-Up)Chiφ pairs also apply exactly to Plus(Down)-Chiφ / Minus(-Down)-Chiφ pairs.

It is assumed that the input 42 to the detector 44 has been properly conditioned, amplified and filtered so that only the base frequency and the chiφ enter the detector and that the waveform 42 amplitude is normalized. It is also assumed that the input signal and the decoding circuit are synchronized, that is, the input chiφ pulse begins as the decoding circuit is ready to begin. In addition, the chiφ period is adjusted so that the Up-Chiφ ("U") starts at zero voltage with a positive slope and ends at zero voltage with a positive slope.

Synchronization of the chiφ waveform can be accomplished in several ways. The first technique is to lock onto the chiφ frequency, given by one over the chiφ rate, using a phase locked loop tuned to that frequency. The strength of this technique is that the chiφ frequency can be made unique and fixed and different from any potential interfering frequency. This is especially powerful where multiple chiφ waveforms are used to encode multiple bits thus allowing slower chiφ rates while maintaining higher data rates. This approach is likely preferred when non-dedicated spectrum is being used. It is also straightforward to implement with analog circuitry. In a situation where dedicated spectrum is used and a continuous chiφ encoding waveform is employed a second simpler technique can be used. In this approach the frequency of the waveform is compared to its average, which is determined by a lag filter with a very long time constant. This produces a logic high when the chiφ frequency is above its average and a logic low when the chiφ frequency is below its average. The switch from logic high to logic low gives the midpoint of the waveform, which can be used for timing in the logic for chiφ decoding. This technique can be extended to non-continuous chiφ waveforms by broadcasting a set of synchronization pulses between information packets. Another technique for synchronization is to convolute the set of basic waveforms with the input signal and shift the timing of the basic waveforms compared to the until the convolutions are maximised and the reception is locked to the input signal and the convolutions can then become the basis for the chiφ decoding. This technique is likely very immune to noise for a discontinuous chiφ encoding waveform and would likely be used in cases where the chiφ rate may correspond to a potentially interfering signal. It is also more complex to implement and may require digital logic implementation. This technique is similar to the correlation techniques used for CDMA.

Normalization of the input waveform can also be accomplished in several ways. In a situation where dedicated spectrum is being used, standard automatic gain control approaches can likely be used. Normalization can be incoφorated into those decoding techniques that detect the chiφ by looking at frequency bins by noting that a large signal in one frequency bin signifies unwanted noise and that signal can be subtracted from the input to renormalize it. The same effect could be accomplished by using a dedicated "set-on" receiver to detect single frequency interference and subtracting that interference from the input signal. The input can then be amplified to the desired level. This technique may be prohibitively expensive.

A phase locked loop tuned to the chiφ frequency will provide amplification of the desired signal and not of the single frequency noise. The signal can then be amplified to the desired level. This technique will then allow both synchronization and normalization of the input to the decoder making it very attractive from a cost stand point. The convolution approach discussed above for synchronization may provide some normalization for pulsed chiφ waveforms as the timing tuning will provide some processing gain. Thus amplification can be done only at the proper times or integration can be done from multiple pulses. Neither of these alter two techniques provides any filtering of white noise, so filtering techniques such as Kalman filtering or correlation filtering will still need to be done if it is desired to pull a signal from white noise. In the following, the types of chiφ signal pairs that the particular method is applicable to is shown in parentheses following the identifying name of the decoding method. For example, the first method is called Frequency to Voltage conversion. It will work with the U/D pair of chiφs 50 and with the UD/DU pair 52, but not with the P/M pair 54. So "U/D" and "UD/DU" are shown in parentheses after the title "Frequency to Voltage". All of the detection methods may be implemented in either digital electronics, analog electronics or a mixture of the two depending on the frequencies being used for fo and Δf .

I. Frequency to Voltage (U/D 50 and UD/DU 52)

The first embodiment of the disclosed invention comprises down converting the incoming signal by subtracting fo from the signal in exactly the same manner that a Frequency Modulation ("FM") demodulator works. This results in a series of U and D 50 or UD and DU 52 pulses containing frequencies between 0 and Δf that are then sent to a frequency-to-voltage ("F/V") converter 56. The TelCom TC 9400 works between 0 and 100 kHz. Similar devices can be built for higher frequencies if not available commercially.

Figure 7 shows the instant embodiment of the disclosed invention 44 for a series of U and D pulses

50. The output waveform 58 of the F/V converter 56 is a linearly rising voltage as a function of time for the U pulse, or a linearly falling voltage as a function of time for the D pulse. These triangular shaped pulses can then be differentiated 60 to give square pulses 46, positive for the U chiφ and negative for the

D chiφ.

Figure 8 shows the instant embodiment of the disclosed invention 44 for a series of UD and DU pulses 52. The output waveform 62 of the F/V converter 56 is a linearly rising then falling voltage as a function of time for the UD pulse, or a linearly falling then rising voltage as a function of time for the DU pulse. These waveforms are then fed into a bistable device 64 that triggers when the voltage passes through a given value. The device is triggered on as the voltage increases and off as the voltage decreases. The circuit is designed to result in a positive square pulse for the UD pulse and a negative square pulse for the DU pulse 66.

II. Compare Patterns of Zero Crossings of Wave Forms

(U/D 50 and UD/DU 52)

A second embodiment of the disclosed invention 44 is to determine the zero crossings of the waveform and to measure and compare the zero crossing intervals to the known patterns for U/D 50 or UD/DU 52 chiφs. The output corresponds to the success of the match. Figure 9 shows a digital method to determine the zero crossings of the U/D 50 and UD DU 52 waveforms, that is, digitize the incoming signal, inteφolate the zero crossings, compare these values to a table defining the known values, and output a positive or negative square pulse as appropriate. The received waveforms are input to an analog-to-digital ("A/D") converter 68. The converted digital signal is stored 70 and then input to a digital signal processor ("DSP") 72. The DSP output is input to a digital-to- analog ("D/A") converter 74 which produces the square pulses 46.

An analog method to determine the zero crossings of the U/D 50 and UD/DU 52 waveforms is to trigger a bistable device every time the voltage crosses zero. This results in a distinct pattern of square pulses for each unique chiφ waveform. Each square wave pulse is then integrated. Because the voltage for all pulses is a constant, the integral for each pulse is proportional to the time length of the individual square pulse. The values are then compared to the distinct patterns of known voltages (time intervals) for each type of chiφ and a positive or negative pulse is output as appropriate.

This is accomplished in practice by having several bistable devices that require the appropriate voltage (time interval) to switch. If all for a given pattern switched at the appropriate time then logic networks generate either a positive or a negative square pulse as appropriate. Figure 10 shows an analog method to determine the zero crossings of the U/D 50 and UD/DU 52 waveforms. The U/D 50 or UD/DU 52 waveform is input to a bistable device 76 that generates a zero crossing pattern 78. The zero crossing pattern is integrated 80 to produce an integrated output 82. The integrated output 82 is fed to two decoding networks, one for decoding a "zero" and one for decoding a "one." Figure 10 shows only one of these networks, the network for decoding a "one." The integrated output 82 is fed to a plurality of bistable devices 76. Each of these bistable devices 76 produces a bistable output 84 referenced against a timing pulse 86. Each bistable output 84 is input to an AND device 88. Succeeding bistable outputs 84 are input to delay elements 90 and then to AND devices 88. The resultant output 92 is a single pulse, here representing a "one."

The incoming signal may or may not have to be down converted depending on available components.

III. Compare Shortest and Longest of Zero Crossing Intervals of Wave Forms

(U/D 50 and UD/DU 52)

The zero crossings of the wave form are determined as described above. A third embodiment of the disclosed invention 44 is to measure the first and last zero crossing intervals for U/D and measure the first and middle crossing intervals for UD/DU. The output corresponds to the success of the match.

A digital method for accomplishing this is to digitize the incoming signal, inteφolate the appropriate zero crossings, and compare the lengths of the appropriate crossing intervals as shown in Figure 1 1. Figure 1 1 is identical to Figure 9 except for the different parameters used in the DSP 94. For U/D 50 if the first is longer, output a positive square pulse and if the last is longer output a negative square pulse. An analog method is to trigger a bistable device every time the voltage crosses zero as shown in

Figure 12. This results in a distinct pattern of square pulses 78 for each unique chiφ waveform. Each square wave pulse is then integrated 80. Because the voltage for all pulses is a constant the integral for each pulse is proportional to the time length of the individual square pulse. The values are then compared to the distinct patterns of known voltages (time intervals) for each type of chiφ and a positive or negative pulse is output 46 as appropriate. This is accomplished in practice by having two (2) bistable devices 76 that require the appropriate voltage (time interval) to switch. If both switch then a positive or negative square pulse is output as appropriate.

The incoming signal may or may not have to be down converted depending on available components. IV. Integrate Waveform

(U/D 50 and P/M 54)

A fourth embodiment of the disclosed invention 44 is to integrate 80 the incoming waveform 50,54 as shown in Figure 13. A U 10 or P 18 waveform will have a positive integral because as the period decreases, each succeeding negative cycle is slightly shorter than the preceding positive cycle. A D 12 or

M 20 waveform will have a negative integral. The resulting integral thus gives the correct square pulse 46 for the incoming signal.

V. Use Only Waveforms for One (Not Zero), Rectify and Integrate

(U IO. UD 14, P 18) The Up-Chiφ 10, Up-Down-Chiφ 14, and Plus-Chiφ 18 (in this case the same as the Up-Chiφ) are used to represent a "one." A "zero" is represented as an absence of signal. A fifth embodiment of the disclosed invention 44 as shown in Figure 14 is to rectify 96 the incoming waveform and integrate 80 it to give a pulse corresponding to a "one" pulse 98.

VI. Subtractive Integration Comparison to Known Wave Form (U/D 50, UD/DU 52, P/M 54)

As shown in Figure 15, a sixth embodiment of the disclosed invention 44 is to split the incoming signal and send it to two circuits: the "one" comparison circuit and the "zero" comparison circuit. In the

"one" comparison circuit, the signal is subtracted 100 from the appropriate known "one" chiφ wave form

102. The voltage difference is negatively rectified 104 and integrated 80. If the input is "one" chiφ, the output is zero; if the input is a "zero" chiφ, the output is a negative pulse 106.

In the "zero" comparison circuit, the signal is subtracted 100 from the appropriate known "zero" chiφ wave form 108. The voltage difference is rectified 96 and integrated 80. If the input is a "zero" chiφ, the output is zero; if the input is a "one" chiφ, the output is a positive pulse 110.

A simple variation shown in Figure 16 is to check to see if the other comparison circuit has a complimentary output pulse by inputting the negative pulse 106 and the positive pulse 1 10 to an NAND gate 1 12. Thus, if the "one" comparison circuit has a small output pulse and the "zero" comparison circuit has a large output pulse, then the incoming pulse is a one. If the "zero" comparison circuit has a small output pulse and the "one" comparison circuit has a large output pulse then the incoming pulse is a zero.

VII. Additive Integration Comparison to Known Wave Form (U/D 50, UD/DU 52, and P/M 54)

As shown in Figure 17, a seventh embodiment of the disclosed invention 44 is to split the incoming signal and send it to two circuits: the "one" comparison circuit and the "zero" comparison circuit. In the "one" comparison circuit, the signal is added 1 14 to the appropriate known "one" chiφ wave form 102. The voltage sum is rectified 96 and integrated 80. If the input is a "one" chiφ, the voltage output is large; if the input is a "zero" chiφ, the voltage is small 116. The signal is then input to a bistable device 76 that is set to trigger at a voltage between the two (2) possible outputs. Thus, only a "one" pulse will trigger an output 110. The bistable device is reset a fixed time after it is triggered. In the "zero" comparison circuit, the signal is added 1 14 to the appropriate known "zero" chiφ wave form 108. The voltage difference is rectified 96 and integrated 80. If the input is a "zero" chiφ, the voltage output is large; if the input is a "one" chiφ, the voltage is small 1 18. The signal is then input to a bistable device 76 that is set to trigger at a voltage between the two (2) possible outputs. Thus, only a "zero" pulse will trigger an output 106. The bistable device is reset a fixed time after it is triggered. A simple variation shown in Figure 18 is to check to see if the other comparison circuit has a complimentary output pulse by inputting the negative pulse 106 and the positive pulse 1 10 to an NAND gate 1 12. Thus, if the "one" comparison circuit has a large output pulse and the "zero" comparison circuit has a small output pulse, then the incoming pulse is a one. If the "zero" comparison circuit has a large output pulse and the "one" comparison circuit has a small output pulse then the incoming pulse is a zero.

VIII. Out of Phase Chiφs

(P/M 54)

Because a "one" is an Up-Chiφ 10 and a "zero" is its complement, the Up-Chiφ 10 shifted by a phase of 180o, then adding 112 the input signal to a P waveform 18, rectifying 96 and integrating 80 will give a large output pulse if the input is a P 18 and a small output if the input is an M 20. This is the eighth embodiment of the disclosed invention 44 and is shown in Figure 19.

IX. Time Phased Reception

(U/D 50, UD/DU 52)

In the ninth embodiment of the disclosed invention 44 shown in Figure 20 the input signal 50,52 is fed through a number of non-overlapping notch filters 120 that cover the chiφ frequency interval. The outputs of the filters are each rectified 96 and integrated 80 and sent into an AND junction 88 gated by a generated 122 signal 102 timed to the sweep of the chiφ 86. The output of the AND gates 84 is fed into an AND gate array so that only if all of the frequency inputs occur in the proper order at the proper interval is the output a positive pulse corresponding to the "one" chiφ 92. An identical circuit but with the gating signal set to a "zero" chiφ sequence decodes the "zero" chirp. The circuit is identical to that shown in Figure 20 but is not shown here.

A particular advantage of this embodiment is its ability to detect the proper waveform when a strong, on-frequency interfering signal is present. Because the voltage is constant across all of the filters, a strong interfering signal will cause the voltage of that filter to be high. The excess voltage may simply be ignored. Or, because the voltage across the filters is a known constant value, the excess voltage may be subtracted from the total voltage. In a commercial embodiment of the invention, these two circuits operate in parallel.

X. Very Short Chiφs (P/M 54) If the chiφ period t is short compared to one over the chiφ width Δf, the signal frequency change,

[1/ Δf] the waveform is very abbreviated 124. In fact it looks like a pulse as is shown in Figure 21. If the input signal is down shifted from the base frequency and a "one" is an Up-Chiφ 10 and a "zero" is the compliment, the resulting waveform is either an up pulse 1 10 or a down pulse 106. No decoding is necessary in this tenth embodiment of the disclosed invention 44.

XI. Multiple Frequency Down Shift

(U/D 50, UD/DU 52)

In the eleventh embodiment of the disclosed invention 44 shown in Figure 22 the input waveform 50,52 is split into N channels each successively down shifted by fo + k(Δf/N) using an oscillator 126 and frequency multiplier 128 and sent through a notch filter 120 with Δf N width, with k running from 1 to N. The output of each channel is rectified 96 and integrated 80. The output of all of the channels is fed into a timed 86 AND gate 88 array so that only if all of the frequency inputs occur in the proper order at the proper interval is the output a positive pulse corresponding to a "one" chiφ 92. An identical circuit, not shown, generates a negative pulse corresponding to a "zero" chiφ. In a commercial embodiment of the invention, these two circuits operate in parallel.

XII. Sloped Filter

(U/D 50, UD/DU 52)

In the twelfth embodiment of the disclosed invention 44 the input signal is input to a filter 130 whose output is linearly proportional to the frequency. The result is a voltage signal whose magnitude is proportional to the input frequency. For the U/D chiφ pair 50 shown in Figure 23, the output after passing through an envelope detector 132 is triangular pulses with positive or negative slopes 58 that are differentiated 60 to give square pulses of appropriate sign 46.

For the UD/DU chiφ pair 52 shown in Figure 24, the output after passing through an envelope detector 132 is a set of positive and negative triangular pulses 62 that are used to trigger a bistable device 76 to produce positive and negative pulses 66. XIII. Delay Element

(U/D 50, UD/DU 52)

In the thirteenth embodiment of the invention 44, the input signal is directed into two paths, one of which is input to a delay element 90 and is delayed by some small time Δt and then multiplied 126 into the original signal. The output of the multiplier is sent through an envelope detector 132. The resulting signal is proportional to the chiφ frequencies times the delay. For the U/D chiφ pair 50 shown in Figure 25, the output is triangular pulses with positive or negative slopes 58 that are differentiated 60 to give square pulses of appropriate sign 46.

For the UD/DU chiφ pair 52 shown in Figure 26, the output after passing through an envelope detector 132 is a set of positive and negative triangular pulses 62 that are used to trigger a bipolar device

64 to produce positive and negative pulses 66.

A preferred embodiment of the disclosed invention 44 utilizes multiple frequency down shift, disclosed here as the eleventh embodiment.

The present invention encompasses methods and apparatus to enable efficient high bandwidth digital wireless communications. It is fundamentally different from existing wireless technologies which rely upon detection of changes of state to extract information from a received signal. The invention encodes information continuously across the chiφ, thereby allowing more robust detection techniques that are not dependent on the detection of the edge of the transition. As a result, the disclosed invention can be used to detect chiφ waveforms that are used to provide a variety of interactive information and data services, including voice, audio, data, image and compressed video to mobile users, and also to fixed users.

The disclosed invention responds to increasing mobility and demands for real-time information.

CONCLUSION

Although the present invention has been described in detail with reference to one or more preferred embodiments, persons possessing ordinary skill in the art to which this invention pertains will appreciate that various modifications and enhancements may be made without departing from the spirit and scope of the Claims that follow. The various alternatives for a digital wireless communications system that have been disclosed above are intended to educate the reader about preferred embodiments of the invention, and are not intended to constrain the limits of the invention or the scope of Claims. The List of Reference Characters which follow is intended to provide the reader with a convenient means of identifying elements of the invention in the Specification and Drawings. This list is not intended to delineate or narrow the scope of the Claims. INDUSTRIAL APPLICABILITY

The Chirp Waveform Decoding System will enable efficient high bandwidth digital wireless communications leading to new markets for interactive wireless communications services, including voice, data, image, compressed video and Internet access.

LIST OF REFERENCE CHARACTERS

10 Linear Frequency Up-Chiφ

12 Linear Frequency Down-Chiφ

14 Linear Frequency Up-Down-Chiφ

16 Linear Frequency Down-Up-Chiφ

18 Linear Frequency Plus-Chiφ

20 Linear Frequency Minus-Chiφ

22 Chirping Digital Wireless System

24 Digital Input

26 Chiφing Transmitter

28 Chiφing Radio Frequency Waveform

30 Chiφing Receiver

32 Digital Output

34 Receive Antenna

36 Radio Frequency Receiver

38 Received Radio Frequency Input Waveform 0 Kalman Filter 2 Filtered Radio Frequency Input Waveform 4 Detector 6 Intermediate Frequency Pulses 8 Pulse Conditioner

50 Up-Chiφ ("U") / Down Chiφ ("D") Waveform

52 Up-Down-Chiφ ("UD") / Down-Up-Chiφ ("DU") Waveform

54 Plus-Chiφ ("P") / Minus-Chiφ ("M") Waveform

56 Frequency-to- Voltage ("F/V") Converter

58 F/V Output Waveform for U/D

60 Differentiator

62 F/V Output Waveform for UD/DU

64 Bipolar Device

66 Bipolar Device Output Waveform for UD/DU

68 Analog-to-Digital ("A/D") Converter Digital Storage Register Digital Signal Processor ("DSP") Digital-to-Analog ("D/A") Converter Bistable Device Waveform Zero Crossing Pattern Integrator Integrated Waveform Integrated Bistable Output Timing Pulse AND Logic Device Delay Element Output Pulse Digital Signal Processor Rectifier Output Pulse Subtracter "One" Chiφ Waveform Negative Rectifier Negative Pulse "Zero" Chiφ Waveform Positive Pulse NAND Logic Device Adder Small Voltage Waveform for "Zero" Chiφ Small Voltage Waveform for "One" Chiφ Notch Filter Chiφ Generator Very Short Chiφ Waveform Oscillator Frequency Multiplier Sloped Filter Waveform Envelope Detector

Claims

1. A method of extracting information from a plurality of transmitted chiφ radio frequency waveforms comprising the steps of: receiving a plurality of chiφ radio frequency waveforms (28); removing noise from said received chiφ radio frequency waveforms; and extracting information from said received chiφ radio frequency waveforms after said noise is removed.

2. A method as recited in claim 1 , further comprising the step of conditioning a plurality of intermediate frequency pulses which result from the removal of said noise to form a square wave digital output that correlates with said transmitted chiφ radio frequency waveforms.

3. A method as recited in claim 1 or 2, in which noise is removed from said chiφ radio frequency waveforms using a Kalman filter (40).

4. A method of extracting information from a plurality of transmitted chiφ radio frequency waveforms comprising the steps of: receiving a plurality of chiφ radio frequency waveforms (28); and extracting information from said received chiφ radio frequency waveforms.

5. A method as recited in any preceding claim wherein, before the information extraction step, the waveform amplitude is normalised.

6. A method as recited in any preceding claim, wherein synchronisation occurs before the information extraction step.

7. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: down converting said chiφ radio frequency waveform by subtracting f₀ from said chiφ radio frequency waveform to produce a series of U and D or UD and DU pulses containing frequencies between 0 and Δf ; sending said series of U and D or UD and DU pulses to a frequency-to-voltage converter (56); and differentiating (60) the resulting triangular shaped pulses to produce square pulses, positive for the U chiφ and negative for the D chiφ.

8. A method as recited in any of claims 1 to 6, in which the step of extracting mformation from said received chiφ radio frequency waveforms includes the following steps: determining (76) the zero crossings of received chiφ radio frequency waveform; and measuring and comparing the zero crossing intervals to the known patterns for U/D (50) or UD/DU (52) chiφs.

9. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: measuring the first and last zero crossing intervals for U/D (50); and measuring the first and middle crossing intervals for UD/DU (52).

10. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: integrating (80) said chiφ radio frequency waveform; and determining the pulse value by evaluating the negative or positive integral that results.

11. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: rectifying (96) said received chiφ radio frequency waveform; and integrating (80) said received chiφ radio frequency waveform to give said received chiφ radio frequency waveform a pulse corresponding to a "one" pulse.

12. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: splitting said received chiφ radio frequency waveform; sending said received chiφ radio frequency waveform to both a "one" comparison circuit (100, 104, 80) and "zero" comparison circuit (100, 96, 80); subtracting (100) said received chiφ radio frequency waveform from the appropriate known "one" chiφ waveform; rectifying (104) and integrating (80) the voltage difference; subtracting (100) said received chirp radio frequency waveform from the appropriate known "zero" chiφ waveform; and rectifying (96) and integrating (80) the voltage difference.

13. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: splitting said received chiφ radio frequency waveforms into a first signal and a second signal; feeding said first and said second signals to a "one" comparison circuit and to a "zero" comparison circuit; adding (114) said first signal to an appropriate known "one" chiφ waveform (102) in said "one" comparison circuit; rectifying (96) the resulting voltage sum from the "one" comparison circuit; integrating (80) the rectified signal from the "one" comparison circuit; feeding the integrated signal from the "one" comparison circuit to a first bistable device (76) that is set to trigger at a voltage between two possible outputs; adding (114) said second signal to an appropriate known "zero" chirp waveform (108) in said

"zero" comparison circuit; rectifying (96) the resulting voltage sum from the "zero" comparison circuit; integrating (96) the rectified signal from the "zero" comparison circuit; and feeding the integrated signal from the "zero" comparison circuit to a second bistable device (76) that is set to trigger at a voltage between two possible outputs.

14. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: adding said received chiφ radio frequency waveforms to a plus chiφ waveform (18); rectifying (96) the sum; and integrating (80) the rectified signal.

15. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: feeding said received chiφ radio frequency waveforms through a non-overlapping notch filter (120) that covers the chiφ frequency interval; rectifying (96) the output of said filter; integrating (80) the rectified signal; conveying the integrated signal into an AND junction (88) which is gated by a generated signal (102) that is timed to the sweep of a chiφ; conveying the output of the AND junction into an AND gate array so that only if all of the frequency inputs occur in the proper order at the proper interval, a pulse corresponding to a "one" chiφ is produced.

16. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: feeding said received chiφ radio frequency waveforms through a non-overlapping notch filter that covers the chiφ frequency interval; rectifying the output of said filter; integrating the rectified signal; conveying the integrated signal into an AND junction which is gated by a generated signal that is timed to the sweep of a chiφ; conveying the output of the AND junction into an AND gate array so that only if all of the frequency inputs occur in the proper order at the proper interval, a pulse corresponding to a "zero" chiφ is produced.

17. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following step: downshifting said received chiφ radio frequency waveforms from the base frequency.

18. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: splitting said received chiφ radio frequency waveforms into N channels; successively down shifting each of said channels by f₀ + k(Δf/N) using an oscillator (126) and a frequency multiplier (128); conveying the resulting signal through a notch filter (120) with Δf/N width, with k running from 1 to N; rectifying (96) and integrating (80) the output of each channel; and feeding the output of all the channels into a timed AND gate array (88) so that only if all of the frequency inputs occur in the proper order at the proper interval is the output a pulse corresponding to a "one" chirp.

19. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms after said noise is removed includes the following steps: splitting said received chiφ radio frequency waveforms into N channels; successively down shifting each of said channels by f₀ + k(Δf/N) using an oscillator and a frequency multiplier; conveying the resulting signal through a notch filter with Δf/N width, with k running from 1 to N; rectifying and integrating the output of each channel; and feeding the output of all the channels into a timed AND gate array so that only if all of the frequency inputs occur in the proper order at the proper interval is the output a pulse corresponding to a "zero" chiφ.

20. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: conveying said received chiφ radio frequency waveforms to a filter (130), the output of which is linearly proportional to the frequency to produce a voltage signal, the magnitude of which is proportional to the input frequency; passing said voltage signal through an envelope detector (132); and differentiating (60) the output of said envelope detector to produce square pulses (46) of appropriate sign.

21. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: conveying said received chiφ radio frequency waveforms to a filter (130), the output of which is linearly proportional to the frequency to produce a voltage signal, the magnitude of which is proportional to the input frequency; passing said voltage signal through an envelope detector (132); and using the output of said envelope detector to trigger a bistable device (76) to produce positive and negative pulses.

22. A method as recited in any of claims 1 to 6, in which the step of extracting information from said received chiφ radio frequency waveforms includes the following steps: splitting said received chiφ radio frequency waveforms into a first signal and a second signal; feeding said first signal to a delay element (90) which introduces a delay Δt; multiplying (126) said delayed first signal by said received chiφ radio frequency waveforms; and feeding the product to an envelope detector (132) to generate a signal that is proportional to the chiφ frequencies times the delay.

23. Apparatus for extracting information from chiφ radio frequency waveforms comprising means (30) for receiving transmitted chiφ radio frequency waveforms (28), and means (44) for extracting information from the received waveforms.

24. Apparatus as recited in claim 23, further comprising means for normalising the received waveforms and/or means for synchronising the received waveforms with the information extraction means (44).

25. Apparatus as recited in claim 23 or 24, wherein the means (44) for extracting information operates according to the method of any of claims 7 to 22.