WO2001001386A9 - Multistandard liquid crystal display with automatic adjustment of timing signals - Google Patents
Multistandard liquid crystal display with automatic adjustment of timing signalsInfo
- Publication number
- WO2001001386A9 WO2001001386A9 PCT/US2000/017494 US0017494W WO0101386A9 WO 2001001386 A9 WO2001001386 A9 WO 2001001386A9 US 0017494 W US0017494 W US 0017494W WO 0101386 A9 WO0101386 A9 WO 0101386A9
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- video
- signal
- video signal
- clock signal
- extracted clock
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
- G09G5/008—Clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/005—Adapting incoming signals to the display format of the display terminal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
- H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
- G09G2340/0485—Centering horizontally or vertically
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
Definitions
- This invention pertains to display devices, more particularly computer display devices including liquid crystal device (LCD) displays.
- LCD liquid crystal device
- CTR cathode ray tubes
- LCD lighter weight liquid crystal device
- CRT displays use a raster based approach where a scan line is moved from left to right across the screen in a plurality of rows from top to bottom of the screen. As the electron beam moves in this raster pattern, its intensity is varied in order to create the screen image by varying the intensity of the light at each portion of the screen.
- each X Y coordinate on the screen corresponds to a unique pixel whose intensity can be altered as desired, in order to produce the desired screen image, pixel by pixel.
- AGC automatic gain control
- the LCD display is a fixed resolution device, and it accepts only fixed horizontal and vertical frequencies, the LCD display cannot adapt to different horizontal and vertical scan frequencies for a variety of industry standard graphic modes. Centering is also a problem because the LCD screen is a fixed resolution display. If the horizontal centering is not done correctly, the data on either the left or the right side of the screen will be missing. If the vertical centering is not done correctly, the data on either the top or bottom of the screen will be missing.
- the input analog data needs to be converted into digital form before driving the LCD display.
- the sampling clock information is not present in the analog monitor interface. The LCD display therefore needs to generate a clock with the correct frequency and phase to sample the analog image data correctly.
- Prior art LCD displays provide manual adjustments for the user, which allows the user to press buttons in order to move the screen image left to right, and top to bottom, thereby allowing the user to manually center the image in the LCD screen.
- Prior art LCD displays perform pixel adjustment by delaying the input data on a clock by clock basis. The user setting can be saved in the EEPROM in the system, but when the display hardware board is changed the setting needs to be readjusted.
- Such prior art LCD displays only support a preset number of display resolutions.
- a novel method and structure is taught for allowing a liquid crystal device (LCD) display to be used in a computer running a variety of programs which may provide screen images of a variety of graphic modes, and which center the screen image in the LCD display without operator intervention or adjustment.
- the video mode of the video signal provided by the video driver is automatically detected without the need for specific instructions from the video driver.
- the active portion of the display signal is determined and appropriate offsets automatically provided in order to send a video signal to the LCD display having the proper horizontal and vertical frequencies, and a screen image which is centered on the LCD display.
- the optimum sampling phase is automatically determined by making a number of measurements at different sampling phases and detecting which sampling phase provides the greatest contrast value, indicating that is the optimum sampling phase to be used.
- Fig. 1 is a timing diagram showing the relationship between horizontal sync signals and RGB data signals
- Fig. 2 is a timing diagram showing the relationship between vertical sync signals :and_horizontal_sync signals;-
- Fig. 3 is a timing diagram depicting the relationship between horizontal sync signals, RGB data signals, and the extracted clock signal in accordance with this invention
- Fig 4. is a block diagram depicting one embodiment of a line locked PLL used in conjunction with the present invention.
- Fig. 5 is a block diagram depicting a computer system of the present invention.
- Fig. 6 is a block diagram depicting one embodiment of a screen control circuity 400 of the present invention.
- Fig. 7 is a timing diagram depicting the position of the active RGB data signal with respect to horizontal sync pulse
- Fig. 8 is a timing diagram depicting the determination of the active RGB data signal with respect to vertical sync signals
- Fig. 9 is a flowchart depicting the operation of one aspect of the present invention.
- Fig. 10 is a flowchart depicting the operation of another aspect of the present invention.
- Fig. 11 is a timing diagram depicting possible sampling points of a video signal
- Fig. 12 is a diagram depicting the relationship between image quality and sampling phase in accordance with one embodiment of the present invention.
- Fig. 13 is a diagram depicting the relationship between image quality and sampling phase in accordance with another embodiment of the present invention.
- Fig. 1 is a timing diagram showing the relationship between horizontal sync pulses and RGB image data.
- Horizontal sync pulses indicate when a new line of the screen image is to start, and RGB data provides intensity information for each pixel within one line of the screen image.
- the horizontal sync appears on a different line as the RGB data. It defines when the CRT electron beam starts the horizontal sweep.
- the number of pixels (x) from the active edge of the horizontal signal to the valid data is fixed for a particular graphics mode, but the value of x is different for different graphics mode.
- Fig. 2 is a timing diagram showing the relationship between horizontal sync pulses and vertical sync pulses.
- Vertical sync pulses define when a new screen image is to begin, and thus, following each vertical sync pulse there follows a plurality of horizontal sync pulses, one for each line in the screen image.
- Associated with each horizontal sync pulse is a corresponding RGB data stream, as discussed above with reference to Fig. 1.
- a first step is to extract a clock from the signals driving the display.
- a fixed clock or a set of fixed clocks useful for a variety of the most popular industry standards, is not used, because the horizontal clock providing the image signal may be off frequency, thus leading to an error in clock frequencies between that generating the image data and that being used to drive the LCD display.
- a line locked phase lock loop PLL is used to extract a clock from the image signal.
- Fig. 3 is a timing diagram-depicting in more detail a horizontal sync signal, RGB data in the form of a plurality of pulses running at a predetermined clock frequency, and the extracted clock pulse derived from the line locked PLL driven by the horizontal sync signal and locked to the frequency of the analog RGB data.
- PLL 404 uses the horizontal sync signal as an input reference and divides the output signal F cl0ck by a certain value determined by the graphics mode. This is how PLL 404 provides F cl0Ck at the RGB data rate.
- Fig. 5 is a block diagram depicting a computer system constructed in accordance with the teachings of this invention.
- computer system 40 includes computer 41 which provides, on its output bus, video signals of any convenient format.
- computer 41 would directly drive a video display.
- computer 41 would be required to output a standard video format for directly driving a LCD display.
- a novel screen control circuitry 400 receives the video signals from computer 41 and in turn provides appropriate signals to control LCD display 42.
- storage device 43 Used in conjunction with screen control circuitry 400 is storage device 43 for storing one or more lines, or frames, of video display data as eight bit R, G, and B bytes per pixel, after manipulation by screen control circuitry 400 and prior to that video data stored in storage in 43 being sent to LCD display 42 under the control of screen control circuitry 400.
- Screen control circuity 400 controls the output of digital RGB data from storage device 43 to LCD display 42, and provides horizontal and vertical sync signals H, ⁇ . and V, ⁇ - to control LDC display 42.
- storage device 43 is contained on the same circuit as screen control circuity 400. In one embodiment, storage device 43 allows for storage of two lines of pixel information, one being written to by screen control circuity 400 while the other, previously stored, is being read out from storage device 43 to provide a line of pixel data to LCD display 42, in a ping pong fashion.
- storage device 43 contains sufficient memory to allow two entire video frames to be stored, again in a ping pong fashion, one frame being written into storage device 43 by screen control circuity 400 while the other, previously stored video frame, is being read out from storage device 43 to provide video information to LCD display 42.
- different vertical frequencies are capable of being achieved between that vertical frequency sent by computer 41 and that vertical frequency required by LCD display 42.
- Fig. 6 is a block diagram depicting one embodiment of a structure suitable for use as screen control circuity 400 of Fig. 5.
- the overhead operations described below with respect to determining the video mode and performing the screen image centering operation is performed upon boot-up and when there is a video mode change, for example, when there is a change in V, ⁇ and/or H, ⁇ .
- Screen control circuity 400 receives horizontal sync signal H, ⁇ on line 401, vertical sync signal V, ⁇ on line 402, and analog image information, in RGB format (typically) on three line bus 403, on which are provided horizontal sync, vertical sync, and analog RBG signals, respectively.
- the horizontal sync signal received on 401 is applied to
- This clock signal will have a frequency:
- Horizontal sync signal H ⁇ received on lead 401 is also applied to horizontal period counter 405.
- Horizontal period counter 405 determines the time period between successive horizontal sync signals, thus determining the horizontal frequency associated with the screen image mode. (Refer to Table 1).
- the vertical sync signal V ⁇ ⁇ received on lead 402 is applied to vertical period counter 406 which determines the period between successive V, ⁇ signals, thus establishing the vertical frequency for the screen image. (Refer to Table 1).
- the node information is derived in steps 91 and 92 as a result of the output signals from horizontal period counter 405 and vertical period counter 406 being applied to incoming display mode detection circuitry for 407 which establishes certain parameters based upon the detected graphics mode.
- incoming display mode detection circuity 407 determines that the graphics mode of the image being sent to the LCD display is SVGA and thus, the display image is 800 x 600 pixels.
- incoming display mode detection circuitry 407 provides as output data horizontal count information, associated with the horizontal frequency for storage into a horizontal count register, and vertical count information, associated with the vertical frequency, for storage in a vertical count register.
- incoming display mode detection circuity 407 is conveniently implemented as a table look up. In alternative embodiments, circuity 407 is implemented in software, or hardware, or a combination of both, as will be readily appreciated by those of ordinary skill in the art in light of the teachings of this invention.
- the analog RGB signals are applied on bus 403 to analog to digital converters
- the digital outputs (eight bits each, in one embodiment) of -these-analog-to-digital converters are-stored in storage unit 43 (Fig. 5) for later application to LCD display 42 (Fig. 5).
- the digital outputs of analog to digital converters 408-R, 408- G, and 408-B are also applied to horizontal and vertical active/inactive detection circuity 409, which determines the position of the active RGB data signal with respect to the horizontal sync signals, as shown in step 93 of Fig. 9.
- the difference between these two horizontal counts is equal to the number of horizontal active data pixels. In the example given above, for SVGA mode, this number should equal 800. If the difference between these two counts does not equal 800, this means that the extracted clock CLK is not accurately matched to the clock used to generate the video signal being received. In this event, line locked PLL 404 is adjusted as necessary so that the difference between the first and the second count is equal to the expected horizontal resolution for the detected graphics mode. The internal counter of the line locked PLL is incremented/decremented to adjust the sample clock frequency in such a way that the count is set to 800, for this example.
- horizontal and vertical active/inactive detection circuity 409 detects the active and inactive vertical positions by counting the number of H, ⁇ pluses from the start of the vertical sync pulse to the beginning of the active data portion of the RGB signal to derive V ⁇ u, and the number of lines (H, ⁇ pulses) to the end of the active portion of the RGB data signal to derive V ⁇ ⁇ , as depicted in Fig. 8. This results in a first count V ⁇ u ,,,, indicating the number of scan lines to the beginning of the active RGB data portion, and a second count V ⁇ ⁇ indicating the number of scan lines to the end of the active portion of the RGB data signal.
- Horizontal and Vertical Active/Inactive Detection Circuity 409 stores the horizontal active position H couatl , horizontal inactive position H count2 , vertical active position V ⁇ ,, and vertical inactive position V ⁇ ⁇ data in registers for the firmware to process.
- the difference between these two vertical counts is equal to the number of vertical active lines. In the example given above, for SVGA mode, this number should equal 600. If the difference between these two counts does not equal 600, the current graphics mode is a standard graphics mode.
- a non-standard mode of operation refers to mode that deviates from the standard mode table, for example that of Table 1.
- the standard 1024x768 60Hz XGA mode has a pixel (horizontal) rate of 65Mhz.
- the frequency may be at, for example, 65.5Mhz. In the 65.5 Mhz example, the number of pixels per active display width will not be equal to 1024 using the standard XGA mode setting.
- the firmware adjusts the period of line locked PLL 404 such that the number of pixels per active display width is equal to 1024. If adjusting line locked PLL 404 within a predefined margin does not yield the correct number of pixels per display width (in this case 1024), the firmware defaults the setting back to the standard XGA setting, otherwise, the new PLL clock period is used.
- horizontal and vertical active/inactive detection circuity 409 is able to, for a plurality of horizontal lines, determine the smallest counter value after the start of the horizontal sync pulse to RGB data in order to determine the start of-the RGB-active data portion-of the signal, and the largest counter value of valid RGB data in order to determine the end of the active data portion of the RGB signal.
- the screen image can be automatically centered. This is accomplished by sending the valid screen image to the display controller, with appropriate leading blank rows per frame and appropriate leading blank pixels per row.
- clock signal CLK can be of the same frequency but out of phase with that clock used by the graphics card. If this out of phase condition exists, the RGB data will not be sampled properly by analog to digital converters 408-R, 408-G, and 408-B, resulting in improper screen imagery.
- line locked PLL 404 is provided with the ability to phase adjust its output clock signal CLK.
- the method used to automatically adjust the phase of line locked PLL clock signal CLK is shown in the flow chart of Fig. 10.
- a first step is to select a line in a display image having the highest changes of intensity, as depicted in step 101 of the flowchart of Fig. 10. This is done in order to avoid using blank lines or solid white lines, for example, during this process, as that-would yield very poor results.
- a comparison between adjacent pixels is made and a sum tabulated. Thus, for each line in a frame, the following value is calculated:
- n number of pixels in a line
- This determination of which line has the highest change in intensity is performed simultaneously on a plurality of, or each line of a frame, or alternatively, is performed sequentially one line per frame until the entire frame (or a desired portion thereof) has had its line intensity variations detected.
- the video driver being run by computer 41 can provide a specific image to the screen for this purpose, although it has been found that this usually not necessary because when a computer boots up, an image is sent to the screen which remains static for a significant period of time to allow this operation to take place.
- the screen image during this time is not seen because LCD display 42 (Fig. 5) is not sent signals from screen control circuity 400 to allow LCD display 42 to become active during this time, although computer 41 is providing video signals to screen control circuity 400. In this embodiment, only after this activity by screen control circuity 400 does screen control circuity 400 provide active video signals to LCD display 42.
- Fig. 11 depicts a greatly enlarged portion of the RGB signal, showing the analog signal corresponding to several sequential pixels. Since this is an analog signal, the point at which the-saraple is taken Js ⁇ of ⁇ mportance. For example, possible sample points Sj and S 2 would yield incorrect data, while sample point S 3 would yield correct data, and thereby provide the greatest screen image contrast.
- a line has been selected having greatest intensity variations, that line is sampled a plurality of times, each with a different phase for sampling the analog RGB data by analog to digital converters 408-R, 408-G, and 408-B.
- the ⁇ lntensity values for the line is stored for each variation in sampling phase, with a resulting curve shown in Fig. 12.
- the greatest ⁇ lntensity value is used to select the best phase for sampling, and it is this phase to which line locked PLL 404 is adjusted in order to provide clock signal CLK to have this best phase for sampling.
- sampling phase detection is performed by comparing the intensity of sampled pixels in different frames.
- storage device 43 in Fig. 5 or internal storage within screen control circuity 400 of Fig. 5 the previous frame pixel intensity is stored and is compared to the current frame pixel intensity. If the sampling phase is correct, the intensity difference ( ⁇ lntensity) is minimal. Similar to the previous phase detection method, once a line has been selected having greatest intensity variations, that line is sampled a plurality of times, each with a different phase for sampling RGB data. For each sampling phase, the sum of the difference of the pixel intensity between frame for the selected lines calculated:
- n number of pixels in a line
- Pi' pixel intensity of previous frame
- Pj pixel intensity of current frame ⁇ lntensity values are stored for each variation in sampling phase, with resulting curve shown in Fig. 13. The smallest ⁇ lntensity value provides the best sampling phase.
- the phase of line locked PLL 404 is changed in increments of 1/10, providing a selection of ten phases for sampling, the best of which is selected, as shown in steps 102, 103, and 104 of Fig. 10.
- ten phases being considered, ten frames are required in order to sequentially make the phase/ ⁇ lntensity measurements, which for a 60 Hz mode requires only l/6th of a second.
- the same image information will be sent to the screen (although the screen is preferably blanked by screen control circuity 400, as previously described) and thus an accurate determination can be made (step 105 of Fig. 10) and the associated phase angle selected for sampling (step 106 of Fig. 10).
- a plurality of phase delay clocks are used for the simultaneous sampling of the analog RGB signal, allowing the best phase for sampling to be determined even more quickly.
- this requires greater hardware and is not generally required.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US34654999A | 1999-06-30 | 1999-06-30 | |
US09/346,549 | 1999-06-30 |
Publications (2)
Publication Number | Publication Date |
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WO2001001386A1 WO2001001386A1 (en) | 2001-01-04 |
WO2001001386A9 true WO2001001386A9 (en) | 2002-07-11 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US2000/017494 WO2001001386A1 (en) | 1999-06-30 | 2000-06-21 | Multistandard liquid crystal display with automatic adjustment of timing signals |
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TW (1) | TW514858B (en) |
WO (1) | WO2001001386A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10339661B4 (en) * | 2003-08-28 | 2006-07-27 | Siemens Ag | Method and arrangement for synchronizing a video input signal with a video output signal |
US7061281B2 (en) | 2004-06-15 | 2006-06-13 | Mediatek Inc. | Methods and devices for obtaining sampling clocks |
US7388618B2 (en) | 2004-07-22 | 2008-06-17 | Microsoft Corporation | Video synchronization by adjusting video parameters |
US7936364B2 (en) * | 2004-08-17 | 2011-05-03 | Intel Corporation | Maintaining balance in a display |
KR20080105608A (en) * | 2007-05-31 | 2008-12-04 | 삼성전자주식회사 | Automatic coarse setting method of a image display apparatus |
JP6034703B2 (en) * | 2013-01-21 | 2016-11-30 | サターン ライセンシング エルエルシーSaturn Licensing LLC | Conversion circuit, image processing apparatus, and conversion method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1257719A (en) * | 1985-02-25 | 1989-07-18 | Stephen Maine | Graphics display system |
JP2702941B2 (en) * | 1987-10-28 | 1998-01-26 | 株式会社日立製作所 | Liquid crystal display |
JPH07219485A (en) * | 1994-02-07 | 1995-08-18 | Toshiba Corp | Liquid crystal display device |
JP3823420B2 (en) * | 1996-02-22 | 2006-09-20 | セイコーエプソン株式会社 | Method and apparatus for adjusting a dot clock signal |
US5917461A (en) * | 1996-04-26 | 1999-06-29 | Matsushita Electric Industrial Co., Ltd. | Video adapter and digital image display apparatus |
JP3220023B2 (en) * | 1996-09-18 | 2001-10-22 | 日本電気株式会社 | Liquid crystal display |
-
2000
- 2000-06-21 WO PCT/US2000/017494 patent/WO2001001386A1/en active Application Filing
- 2000-06-28 TW TW89112765A patent/TW514858B/en not_active IP Right Cessation
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TW514858B (en) | 2002-12-21 |
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