WO2000078106A1

WO2000078106A1 - Printed circuit board with a non-discrete capacitive element and method of manufacture

Info

Publication number: WO2000078106A1
Application number: PCT/US2000/016174
Authority: WO
Inventors: Nicholas Biunno
Original assignee: Hadco Santa Clara, Inc.
Priority date: 1999-06-14
Filing date: 2000-06-13
Publication date: 2000-12-21
Also published as: AU5734200A

Abstract

A printed circuit board including an organic core (34) and a non-discrete capacitive element (5) is described. The non-discrete capacitive element (5) is disposed on the surface of the organic core (34) and includes a conductive element (10) defining an electrical isolation gap (14) and having a first gap side (15) and a second gap side (16), a dielectric layer (26) insulating the first gap side (15) from the second gap side (16), and a conductive layer (30) coating the dielectric layer (26) and in electrical contact with the second gap side (16). A method of forming the above printed circuit board also is described.

Description

PRINTED CIRCUIT BOARD WITH A NON-DISCRETE CAPACITIVE ELEMENT AND METHOD OF MANUFACTURE

Field of the Invention

The invention relates generally to electronic circuits and more specifically to electronic circuits that damp transients.

Background of the Invention

Circuits exhibit multiple resonances due to a variety of reasons, including current spikes resulting from switching activity, the return current of high-speed signals, and signal radiation. These resonances, which often produce transient currents, increase as circuits are subjected to increasing clock speeds and decreasing supply voltages. It has been demonstrated that these resonances can be reduced in ground and power planes of printed circuit boards by resistive termination along the board edge. Placing discrete resistors about the perimeter of a printed circuit board effected this resistive termination. However, the placement of these discrete resistors takes up valuable surface area and creates lead inductance. The present invention avoids these problems.

Summary of the Invention

The present invention provides a novel printed circuit board with a non-discrete capacitive element, and methods of forming such a non-discrete capacitive element on a printed circuit board. The use of non-discrete capacitive elements allows the printed circuit board to be embedded, for example, in a multilayer circuit board, and eliminates lead inductance with respect to these elements. The circuit comprising the non-discrete capacitive element may be, for example, a ground plane, a power distribution plane or a signal trace disposed on a surface of a printed circuit board.

In one aspect, the present invention provides a novel printed circuit board comprising an organic core and a non-discrete capacitive element. The non-discrete capacitive elements includes a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side. It also includes a first dielectric layer coating at least a portion of the first gap side and a first conductive layer coating at least a portion of the first dielectric layer and at least a portion of the second gap side and spanning the electrical isolation gap.

In another aspect, the present invention provides a novel method of forming a printed circuit board comprising an organic core and a non-discrete capacitive element. First, an organic core of a printed circuit board having a conductive element disposed on a surface of the organic core is provided; the conductive element defining an electrical isolation gap and having a first gap side and a second gap side. Next, at least a portion of the first gap side is coated with a first conductive layer. Then, at least a portion of the first conductive layer is coated with a first dielectric layer. Finally, at least a portion of the first dielectric layer and at least a portion of the second gap side is coated with a second conductive layer, such that the second conductive layer spans the electrical isolation gap.

In yet another aspect, the present invention provides a printed circuit board having an organic core and a non-discrete capacitive element. The non-discrete element includes a conductive element disposed on a surface of the organic core; the conductive element defining an electrical isolation gap and having a first gap side and a second gap side. It also includes a first conductive layer coating at least a portion of the first gap side, a first dielectric layer coating at least a portion of the first conductive layer, and a second conductive layer coating at least a portion of the first dielectric layer, at least a portion of the second gap side and spanning the electrical isolation gap, such that first conductive layer is not in contact with the second conductive layer

In yet another aspect, the present invention provides a novel method of forming a circuit including a non-discrete capacitive element. First, an organic core of a printed circuit board having a conductive element disposed on a surface of the organic core is provided; the conductive element defining an electrical isolation gap and having a first gap side and a second gap side. Second, at least a portion of the first gap side is coated with a first conductive layer. Third, at least a portion of the first conductive layer is coated with a first dielectric layer. Finally, at least a portion of the first dielectric layer and at least a portion of the second gap side is coated with a second conductive layer, such that the second conductive layer spans the electrical isolation gap. In still yet another aspect, the present invention provides a novel printed circuit board comprising an organic core and a non-discrete capacitive element. The non-discrete capacitive element includes a conductive element disposed on a surface of the organic core; the conductive element defining an electrical isolation gap and having a first gap side and a second gap side. It also includes a dielectric layer insulating the first gap side from the second gap side and a conductive layer coating at least a portion of the dielectric layer and in electrical contact with the second gap side.

The invention will be understood further upon consideration of the following drawings, description and claims.

Description of the Drawings

The invention is pointed out with particularity in the appended claims. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. Like reference characters in the respective drawn figures indicate corresponding parts. The advantages of the invention described above, as well as further advantages of the invention, may be better understood by reference to the description taken in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic cross-sectional side view of an embodiment of a printed circuit board including an organic core and a non-discrete capacitive element in accordance with the present invention;

Figure 2 is a schematic cross-sectional side view of another embodiment of a printed circuit board including an organic core and a non-discrete capacitive element in accordance with the present invention;

Figure 3 is a schematic top plan view of yet another embodiment of the present invention wherein the conductive element is a signal trace having a non-discrete capacitive element;

Figure 4 is a schematic top plan view of still yet another embodiment the present invention wherein the conductive element is a ground plane or a power plane of a printed circuit board;

Figure 5 is a schematic cross-sectional side view of the embodiment of Figure 4 taken along line A- A'; Figure 6 is a flowchart diagram illustrating an embodiment of a method of forming a printed circuit board including an organic core and a non-discrete capacitive element in accordance with the present invention;

Figure 7 is a schematic cross-sectional side view of yet another embodiment of a printed circuit board including an organic core and a non-discrete capacitive element in accordance with the present invention; Figure 8 is a flowchart diagram illustrating another embodiment of a method of forming a printed circuit board including an organic core and a non-discrete capacitive element in accordance with the present invention; and

Figure 9 is a schematic cross-sectional side view of yet another embodiment of a printed circuit board including an organic core and a non-discrete capacitive element in accordance with the present invention.

Detailed Description of the Invention

In order to more clearly and concisely describe the subject matter of the claims, the following definitions are intended to provide guidance as to the meaning of specific terms used in the following written description, examples and appended claims.

As used herein the term "dielectric" refers to a non-conductor or insulator, as opposed to a "conductor" which conducts, or serves as a channel for, electric current. Conductors have the properties of conductivity, which is a measure of the ability of a given substance to conduct electric current, and resistivity, which is a measure of the opposition to the passage of current. As used herein the term "high dielectric constant" means materials having a dielectric constant of above about 4 at about 20°C and a frequency of about 1 KHz which can be applied and adhered to various surfaces such as, for example, the surface of a printed circuit board layer. From this point forward it can be assumed, unless otherwise noted, that dielectric constants are given for material at about 20° C and a frequency of about 1 KHz. While materials are known which have dielectric constants above about 1 ,000, these materials typically must be reduced to powder form and mixed with a binder because they are brittle and do not exhibit acceptable adhesion properties. Reducing these solid dielectrics to powder and mixing them with a binder dramatically decreases their effective dielectric constant. For example, barium titanate has a dielectric constant of about 2,000 when the material is solid. However, when it is reduced to a powder having an average particle size of about 10 μm or less and mixed with a phenolic resin binder, the dielectric constant drops to about 20 or less. At the present time, materials having high dielectric constants that are suitable for use with the present invention are known to have dielectric constants of up to about 80, however, it is anticipated that this threshold will increase in the near future and that these materials will increase the performance of the non-discrete capacitive elements of the present invention. As used herein the term "non-discrete capacitive element" means a capacitive element formed about an electrical isolation gap in a circuit comprising multiple layers of materials, including at least one dielectric layer and at least one conductive layer. The term "non-discrete" refers to the integral nature of these elements in that they are laid down in multiple layers across an electrical isolation gap and, optionally, upon a surface or surfaces adjacent to the isolation gap, in a circuit and thus becomes an integral part of the circuit as opposed to a discrete element which is mounted upon the surface of a printed circuit board and electrically connected to the circuit with mounting pins, or leads, and solder. These non-discrete elements may be embedded in, for example, a multilayer printed circuit board. This represents an advantage over typical surface-mounted, or discrete, capacitors and/or resistors which cannot be embedded within the layers of a multilayer printed circuit board due to their size and bulk, and thus require valuable printed circuit board surface area.

As used herein the term "electrical isolation gap" refers to a gap in a circuit that does not allow direct transmission of current due to a gap in the conductive material of the circuit. However, the addition of a non-discrete capacitive element will allow transmission of electric current subjected to an alternating voltage potential by the capacitor formed within the non- discrete capacitive element. That is, the capacitor transmits alternating current, but not direct current.

As used herein the term "printed circuit board layer" includes one or more layers (such as signal layer or power/ground layers) included in backplanes, multilayer printed circuit boards, mother boards, daughter boards, rigid-flex printed circuit boards, personal computer memory card interconnect devices, and the like.

Figure 1 is a schematic cross-sectional side view of an embodiment of a printed circuit board having an organic core 34 and a non-discrete capacitive element 5 in accordance with the present invention. The non-discrete capacitive element 5 includes, in overview: a conductive element 10 defining an electrical isolation gap 14 and having a first gap side 15 and a second gap side 16; a first dielectric layer 26 coating at least a portion of the first gap side 15; and a first conductive layer 30 coating at least a portion of the first dielectric layer 26 and at least a portion the second gap side 16 and spanning the electrical isolation gap 14. The conductive element 10, the first dielectric layer 26, and the first conductive layer 30 form a capacitor. If the first conductive layer 30 has sufficient resistance, the non-discrete capacitive element 5 will be the equivalent of a discrete capacitor and a discrete resistor connected in series. In Figure 1, the first gap side 15 of the conductive element 10, includes a first gap wall 18 and a first planar surface 38 adjacent to the first gap wall 18. The second gap side 16 includes a second gap wall 22 and a second planar surface 42 adjacent to the second gap wall 22. The first dielectric coating 26 is shown in Figure 1 to coat both the first gap wall 18 and a portion of the first planar surface 38. Alternatively, the first dielectric coating 26 might only coat the first gap wall 18 and not the first planar surface 38 (not shown). Similarly, the first conductive coating 30 may coat only the second gap wall 22 and not the second planar surface 42 (also not shown).

The dimensions of the first dielectric layer 26 and the first conductive layer 30 needed to achieve a desired capacitance can be approximated using the formula C = εA/t, wherein ε is the dielectric constant of the first dielectric layer 26, A is the surface area of the conductive element 10 and the first conductive layer 30 which overlaps with the first dielectric layer 26, and t is the thickness of the first dielectric layer 26. The capacitance may be adjusted by choosing a dielectric for the first dielectric layer 26 with a higher or lower dielectric constant. For example, for a non-discrete capacitive element with a first dielectric layer 26 having a dielectric constant of 20 and a thickness of 0.0004 inches, and a first conductive layer 30 and a conductive element 10 that overlap the first dielectric layer 26 over an area that is 0.28 inches by 0.26 inches, the approximate capacitance of the non-discrete capacitive element would be 3.65 nanoFarads (nF). Preferably, the capacitance is adjusted to filter the range of frequencies in which the circuit will operate. If the capacitance is too high or too low, it will not effectively filter disturbances in the operating range of the circuit. Filters are typically defined as low-pass, high- pass or band-pass. For low pass filters, the relationship between the frequency, resistance and capacitance is represented by the following formula: V_oul = F,„2π/RC/(l+(27i RC) ) , where V,„ is the voltage amplitude into the filter, V_ow, is the voltage amplitude out of the filter, /is the frequency above which it is desired that noise be filtered, R is the resistance of the element and C is the capacitance of the element. For high pass filters, the relationship is represented by the

") 1 /9 formula: V_ou,= V,„/(l+(2π RC) ) , where/is the frequency below which it is desired to filter noise. Similarly, bandpass filters and resonators also may be formed with non-discrete elements by using relationships known in the art.

The dimensions of the first conductive layer 30 needed to achieve a desired resistance, R, can be approximated from the general formula R = p tl t w, wherein p is the resistivity of the - 1 - first conductive layer 30, t is the thickness of the first conductive layer 30, £ is the length of the first conductive layer 30, and w is the width of the first conductive layer 30. For example, a non- discrete capacitive element having a first conductive layer with a resistivity of 10 ohm-mils, a thickness of 0.8 mils, a length of 16 mils and a width of 260 mils, will have a resistivity of approximately 0.77 ohms. This also is an approximation because, for example, the thickness of the first conductive layer 30 may vary, particularly in the electrical isolation gap 14.

While the first dielectric layer 26 and the first conductive layer 30 may often extend over the first planar surface 38 and/or the second planar surface 42 of the conductive element 10, in order to achieve desired values of capacitance and resistivity, such extension may not be necessary depending on the desired capacitance and resistivity as well as the dielectric constant of the first dielectric layer 26 and the resistivity of the first conductive layer 30. Additionally, further layers may be added to the non-discrete capacitive element in order to increase capacitance and/or resistance without taking up more space on the surface of the conductive element 10. This is shown in Figure 2, which is a schematic cross-sectional side view of another embodiment of a printed circuit board having an organic core and a non-discrete capacitive element in accordance with the present invention. This embodiment is substantially similar to the embodiment shown in Figure 1 but further includes a second dielectric layer 150 and a second conductive layer 154. The second dielectric layer 150 coats the first conductive layer 130 and contacts the first dielectric layer 126. The second conductive layer 154 coats the second dielectric layer 150 and also contacts the conductive element 110 at the contact point 156. The capacitor defined by the non-discrete capacitive element 105 of Figure 2 comprises: the conductive element 110 and the second conductive layer 154 which acts as one capacitor plate; the first conductive layer 130 which acts as the second capacitor plate; and the first dielectric layer 126 and the second dielectric layer 150 which acts as a single dielectric layer insulating the first and the second capacitor plates.

Thus, the embodiment of Figure 2 more than doubles the capacitance achieved by the embodiment shown in Figure 1 , assuming that the same materials and same layer dimensions are used, because the overlap area more than doubles. The first dielectric layer 126 and the second dielectric layer 150 may have the same or different dielectric constants. Similarly, the first conductive layer 130 and the second conductive layer 154 may have the same or different resistivities. Thus, if only the first conductive layer 130 or the second conductive layer 154 are designed to act as a resistor, a series capacitor and resistor is defined by the non-discrete capacitive element 105. If both the first conductive layer 130 and the second conductive layer 154 are designed to resist the flow of current, then a series resistor, capacitor and resistor is defined by the non-discrete capacitive element 105. Preferably, at least one of the conductive layers is sufficiently resistive to operate as a resistor.

Optionally, additional dielectric and conductive layers might be added to the embodiment described in Figure 2 depending on the desired performance of the non-discrete capacitive element and space constraints. For example, if the planar surface area adjacent to the electrical isolation gap were constrained, more layers over smaller surface areas might be used to achieve desired levels of capacitance and resistance. Using the formulae described above, the dimensions of the layers can be approximated for desired values of capacitance and resistance.

It is preferable to use dielectric materials for the dielectric layer or layers having a high dielectric constant in order to maximize capacitance while minimizing the area needed to achieve such capacitance. Some materials having high dielectric constants are known to those in the art. One example of such a material, suitable for use in the present invention is the polymer dielectric paste sold under the trade name CX-11TM by Asahi Chemical Research Laboratory (Tokyo, Japan). Preferably, the dielectric constant is between about 4 and about 2,000, more preferably, the dielectric constant is between about 20 and about 2,000, most preferably, the dielectric constant is between about 80 and 2,000. It should be noted that the above dielectric constants are given assuming a frequency of 1 KHz, and therefore if the frequency used is not lKHz, the dielectric constant may be different. The frequency range is typically from about lKHz to about 10,000 MHz and the dielectric constant for a given material across this or any other range can be measured using a Network Analyzer such as the model HP8757D/E available from Hewlett Packard Corporation (Englewood, CO). Materials having resistive properties suitable for use in the present invention are known.

An example of a such a material suitable for use in accordance with the present invention are the polymer resistive paste solders sold under the trade name MINICO® 1000, available from Acheson Colloids Co. (Port Huron, MI). The MINICO® 1000 series is available with resistivities from 0.1 ohm-mil to 1 Megaohm-mil. These materials are designed to be screen printable. The resistance of the non-discrete capacitive element should be chosen so that it filters the desired frequency range using the relationships discussed above or other resistance and capacitance relationships known in the art. Figure 3 is a schematic top plan view of yet another embodiment of the present invention wherein the non-discrete capacitive element 205 includes, in overview: a conductive element 210 comprising a signal trace defining an electrical isolation gap 214 and having a first gap side 215 and a second gap side 216; a first dielectric layer 226 coating the first gap side 215; and a first conductive layer 230 coating the first dielectric layer 226 and the second gap side 216, and spanning the electrical isolation gap 214. In this embodiment the coatings are present on both the first and second gap walls 218 and 222, and the first and second planar surfaces 238 and 242. However, as discussed in reference to Figure 1 , the coatings might alternatively be confined to the gap walls 218 and 222. The signal trace of Figure 3 may be any signal trace, including a return signal bus line lying on a backplane (not shown). This would be particularly advantageous for use in high speed bus lines which may exhibit unacceptable levels of noise due in part to the switching of the various signals entering and exiting the bus line, cross talk due to the proximity of other bus lines, and signal bounce from unterminated lines. Another advantage to this embodiment is that it provides resistive and capacitive elements on the signal trace even though the trace lies on a printed circuit board layer embedded within a multilayer printed circuit board.

Figure 4 is a schematic top plan view of still yet another embodiment of the present invention wherein the conductive element is a ground plane or a power plane of a printed circuit board. Figure 5 is a schematic cross-sectional side view of the embodiment of Figure 4 taken along line A-A'. In general overview, the capacitive element 305, disposed on organic core 334, includes: a conductive element 310, which may be a power or ground plane, defining an electrical isolation gap 314 having a first gap side 315 and a second gap side 316; a first dielectric layer 326 coating the first gap side 315; and a first conductive layer 330 coating the first dielectric layer 326 and the second gap side 316 and spanning the electrical isolation gap 314.

Additional layers may be added to the capacitive element of Figures 4 and 5, as discussed above with regard to the embodiments of Figures 1 and 2. Similarly, materials and dimensions of material layers may be chosen as discussed with regard to the embodiments of Figures 1 and 2 to achieve a desired level of capacitance and, optionally, resistance. The electrical isolation gap 314 in Figures 4 and 5 is a slot that defines two portions of the conductive layer 310. In this embodiment, the portion of the conductive layer 310 on the second gap side 316 is an edge strip about the perimeter of a power or ground plane. Alternatively, or additionally, the slot may define further portions of the conductive layer 310 (not shown). For example, electrically isolated regions may be defined around plated vias connecting the conductive layer to other conductive layers in order to reduce or eliminate multiple resonances traveling to or from the conductive layers. Also shown in Figures 4 and 5 is a plurality of vias 368 plated with conductive material

376. The vias 368 electrically connect the conductive layer 310 to a second conductive layer 372, disposed on the opposing surface of the organic core 334. Providing a plurality of buried vias is advantageous because inductance is inversely proportional to the number of plated vias. Total inductance, L_T, can be calculated by the formula Lτ=Lγ/n, wherein Ly is the inductance of an individual via, and n is the total number of vias. It can be seen from this formula that as the number of vias, n, approaches infinity, the total inductance approaches zero.

Optionally, the first conductive layer 360, the organic core 334, and the second conductive layer 372 may be a printed circuit board layer that provides shared capacitance within a multilayer circuit board, thus taking advantage of both the distributive and the decoupling advantages of buried capacitance, and rendering the currents less noisy with dissipative edge termination. In preferred embodiment, the organic core 334 has a dielectric constant of about 4.7 and a thickness of from about 1 to about 4 mils, and the first conductive element 310 and the second conductive element 372 are made of copper and have a thickness of about 1.2 mils to about 1.4 mils. Figure 6 is a flowchart diagram illustrating an embodiment of a method of forming a printed circuit board including an organic core and a non-discrete capacitive element in accordance with the present invention. In general overview the method includes the steps of: providing an organic core of a printed circuit board including a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side (step 600); coating at least a portion of the first gap side with a first dielectric layer (610); and coating at least a portion the second gap side and at least a portion of the first dielectric layer with a first conductive layer such that the first conductive layer spans the electrical isolation gap (step 620).

In step 600, the conductive element may be a signal trace including, but not limited to, copper signal traces. The conductive element also may be planar, such as a power plane, a ground plane and/or other conductive plate, such as for example, a conductive plate of a capacitor laminate as described above. The electrical isolation gap may be defined by standard develop-and-etch manufacturing processes for defining inner layer patterns for multilayer printed circuit boards. In a planar conductive element, the electrical isolation gap may be a slot, which defines a first portion of the planar conductive element and a second portion of the planar conductive element. For example, the electrical isolation slot may define an edge strip about the perimeter of the planar conductive element. Optionally, the edge strip may also include one or more plated vias, which may serve to connect to a second planar conductive element, a trace or a discrete element.

In step 610, at least a portion of the first gap side is coated with a first dielectric layer. The portion of the first gap side coated may be limited to the gap wall or extend onto the planar surface adjacent the gap wall. Preferably, the dielectric layer has a high dielectric constant.

The coatings of the present invention may be applied through a mask using standard screen printing techniques known in the art. Additionally or alternatively, the coatings of the present invention may be applied by spray coat and/or sputter coat techniques that are known in the art. This first dielectric layer may be cured at this point, however, preferably, the first dielectric layer is dried by evaporating the volatile solvent from the dielectric material.

In step 620, at least a portion of the second gap side and at least a portion of the first dielectric layer is coated with a first conductive layer such that the first conductive layer spans the electrical isolation gap. Similar to step 610 above, the portion of the second gap side coated may be limited to the gap wall or extend onto the adjacent planar surface. This coating also may be applied as described above. This layer is preferably dried if further layers are to be added to the non-discrete capacitive element. Generally, it is preferable to cure after all of the layers have been applied in order to maximize the adhesion between the layers.

This method may optionally include a further step (not shown) of coating at least a portion of the first conductive layer and a portion of the first dielectric layer with a second dielectric layer. Further, this method also may include the step of coating at least a portion of the second dielectric layer and a portion of the conductive element with a second conductive layer. Further layers may be similarly added in further steps. The materials used for each layer and the layer dimensions may be chosen according to the desired capacitance and resistance as discussed above. Further, the material selected for these layers may have similar polymer bases, for example, the layers may all be ether epoxy-based or phenolic based. Alternatively, the layers may have different polymer bases. Figure 7 is a schematic cross-sectional side view of yet another embodiment of a printed circuit board in accordance with the present invention. The capacitive element 405 disposed on the organic core 434 includes, in overview: a conductive element 410 defining an electrical isolation gap 414 and having a first gap side 415 and a second gap side 416; a first conductive layer 400 coating at least a portion of the first gap side 415; and a first dielectric layer 404 coating at least a portion of the first conductive layer 400; and a second conductive layer 408 coating at least a portion the first dielectric layer 404 and at least a portion of the second gap side 416 and spanning the electrical isolation gap 414. The first conductive layer 400, the first dielectric layer 404 and the second conductive layer 408 form a capacitor. If the first conductive layer 400 and the second conductive layer 408 have sufficient resistance, the capacitive element 405 will be equivalent to a discrete resistor, a discrete capacitor and a discrete resistor connected in series.

In Figure 7, the first gap side 415 of the conductive element 410, includes a first gap wall 418 and a first planar surface 438 adjacent to the first gap wall 418. The second gap side 416, includes a second gap wall 422 and a second planar surface 442 adjacent to the second gap wall 422. The first conductive coating 300 is shown in Figure 7 to coat both the first gap wall 418 and a portion of the first planar surface 438. Alternatively, the first conductive coating 400 might only coat a portion of the first planar surface 438 and not the first gap wall 418 (not shown). Another alternative is to coat at least a portion of the first gap wall 418 and not the first planar surface 438 with the first conductive coating 400 (also not shown). Similarly, the second conductive coating 408 may coat either or both the second gap wall 422 and the second planar surface 442. However, the second conductive layer 408 should not contact either the first conductive layer 400 or the conductive element 410 on the first gap side 415 in order for there to be a capacitor element formed about the first dielectric layer 404. The dimensions of the first conductive layer 400, the first dielectric layer 404 and the second conductive layer 408 needed to achieve a desired capacitance can be approximated using the formulae discussed above with regard to Figure 1. Additionally, further layers may be added to the capacitive element 405 in order to increase capacitance and/or resistance is as desired. For example, a second dielectric layer coating at least a portion of the second conductive layer and a portion of the first dielectric layer could be added along with a third conductive layer coating at least a portion of the second dielectric layer and contacting the first conductive layer (not shown). It is contemplated that the first dielectric layer 404 and any additional dielectric layers may have the same or different dielectric constants. Preferably, as discussed above, materials having high dielectric constants are used. This is because higher dielectric constants allow for a smaller plate area for the same capacitance, thus minimizing the surface area of the conductive element necessary for the non-discrete capacitive element 405.

It also is contemplated that the first conductive layer 400, the second conductive layer 408 and any additional conductive layers may have the same or different resistivities. Thus, if only the first conductive layer 400 or second conductive layer 408 are designed to act as a resistor, a series capacitor and resistor is defined by the capacitive element 405. If both the first conductive layer 400 and the second conductive layer 408 are designed to resist the flow of current, then a series resistor, capacitor and resistor is defined by the capacitive element 405.

The conductive element 410 of Figure 7 may be a copper signal trace, much like that described in reference to Figure 3, with the exception of the order and placement of the layers. The conductive element 410 also may be planar, such as a power plane, a ground plane and/or other conductive plate, such as a conductive plate of a capacitor laminate as described above. As described above in Figures 4 and 5, in a planar conductive element the electrical isolation gap may be a slot defining a first portion of the planar conductive element and a second portion of the planar conductive element. For example, the electrical isolation slot may define an edge strip about the perimeter of the planar conductive element. Optionally, the edge strip may also include one or more plated vias, which may serve to electrically connect the conductive element to a second planar conductive element, a trace or a discrete element. In the case of a capacitor laminate, the organic core 434 preferably has a dielectric constant of about 4.7 and a thickness of from about 1 to about 4 mils, and the first conductive element 410 and a second conductive element (not shown) are preferably made of copper and have a thickness of about 1.2 mils to about 1.4 mils.

Figure 8 is a flowchart diagram illustrating another embodiment of a method of forming a printed circuit board in accordance with the present invention. In general overview the method includes the steps of: providing an organic core of a printed circuit board having a conductive element disposed on the surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side (step 700); coating at least a portion of the first gap side with a first conductive layer (step 710); coating at least a portion of the first conductive layer with a first dielectric layer (step 720); and coating at least a portion of the first dielectric layer and at least a portion of the second gap side with a second conductive layer, such that the second conductive layer spans the electrical isolation gap and is not in contact with the first conductive layer (step 730).

In step 700, the conductive element may be a signal trace including, but not limited to, copper signal traces. The conductive element also may be planar, such as a power plane, a ground plane and/or other conductive plate, such as for example, a conductive plate of a capacitor laminate as described above.

The electrical isolation gap may be defined by standard develop-and-etch manufacturing processes for defining inner layer patterns for multilayer printed circuit boards. In a planar conductive element, the electrical isolation gap may be a slot, which defines a first portion of the planar conductive element and a second portion of the planar conductive element. For example, the electrical isolation slot may define an edge strip about the perimeter of the planar conductive element. Optionally, the edge strip may also include one or more plated vias, which may serve to connect to a second planar conductive element, a trace or a discrete element. In step 710 (Figure 8) at least a portion of the first gap side is coated with a first conductive layer. The portion of the first gap side coated may be limited to the gap wall or the adjacent planar surface. Alternatively, both the gap wall and the planar surface may be coated. The coatings of the present invention may be applied as described for Figure 6. This first conductive layer may be cured at this point. Preferably, however, it is dried by evaporating the volatile solvent from the conductive material and cured after all the layers have been applied.

In step 720 at least a portion of the first conductive layer is coated with a first dielectric layer. Similar to the first conductive layer, this layer preferably is dried by evaporating the solvent. In step 730, at least a portion of the second gap side and at least a portion of the first dielectric layer is coated with a second conductive layer such that the second conductive layer spans the electrical isolation gap and is not in contact with the first conductive layer. The portion of the second gap side coated may be limited to the gap wall or the adjacent planar surface. Alternatively, both the second gap wall and the second planar surface may be coated. This coating also may be applied as described above. This layer is preferably dried if further layers are to be added to the non-discrete capacitive element. Otherwise, the layers may be cured at this point.

Additionally, further layers may be similarly added in further steps. For example, a second dielectric layer might be added that coats at least a portion of the second conductive layer and contacts the first dielectric layer. Further, a third conductive layer might be added that coats at least a portion of the dielectric layer and contacts the first conductive layer. The materials used for each layer and the layer dimensions may be chosen according to the desired capacitance and resistance as discussed above. The materials selected for the above layers may have similar polymer bases, for example, the layers may all be ether epoxy-based or phenolic based. Alternatively, the layers may have different polymer bases.

Figure 9 is a schematic cross-sectional side view of yet another embodiment of a printed circuit board having an organic core 534 and a non-discrete capacitive element 505 in accordance with the present invention. The non-discrete capacitive element 505 comprises, in overview: a conductive element 510 defining an electrical isolation gap 514 and having a first gap side 515 and a second gap side 516; a discontinuous dielectric layer 500 coating at least a portion of the first gap side 515 and at least a portion of the second gap side 516; and a conductive layer 504 coating at least a portion of the discontinuous dielectric layer 500 and spanning the electrical isolation gap 514. The first gap side 515 includes a first gap wall 518 and a first planar surface 538, and the second gap side 516 includes a second gap wall 522 and a second planar surface 542. The discontinuous dielectric coating 500 is shown in Figure 9 to coat the first gap wall 518, a portion of the first planar surface 538, the second gap wall 522 and a portion of the second planar surface 542. Alternatively, the discontinuous dielectric layer 500 may only coat the first gap wall 518 and the second gap wall 522. However, the discontinuous dielectric layer in this embodiment should coat at least a portion of the gap wall such that the overlying conductive layer 504 does not contact the conductive element 510, either on the first gap side 515 or the second gap side 516. The conductive layer 504 coats the discontinuous dielectric layer 500 and the organic core 534 in the isolation gap 514. Thus two capacitors are defined about the two parts of the discontinuous dielectric layer 500 shown in Figure 9. If the conductive layer 504 is sufficiently resistive, the non-discrete capacitive element 505 will be the equivalent of a discrete capacitor, resistor, and capacitor connected in series.

The dimensions of the discontinuous dielectric layer 500 and the conductive layer 504 needed to achieve a desired capacitance can be approximated using the formulae discussed above with regard to Figure 1. Preferably the discontinuous dielectric layer 500 has a high dielectric constant. This is because higher dielectric constants allow for a smaller plate area for the same capacitance, thus minimizing the surface area of the conductive element 510 necessary for the capacitive element 505. The conductive element 510 of Figure 9 may be a copper signal trace, much like that described in reference to Figure 3, with the exception of the order and placement of the layers. The conductive element 510 also may be planar, such as a power plane, a ground plane and/or other conductive plate, such as for example, a conductive plate of a capacitor laminate as described above. As described above in Figures 4 and 5, in a planar conductive element, the electrical isolation gap may be a slot, which defines a first portion of the planar conductive element and a second portion of the planar conductive element. For example, the electrical isolation slot may define an edge strip about the perimeter of the planar conductive element. Optionally, the edge strip may also include one or more plated vias, which may serve to electrically connect the conductive element to a second planar conductive element, a trace or a discrete element. In the case of a capacitor laminate, the organic core 534 preferably has a dielectric constant of about 4.7 and a thickness of from about 1 to about 4 mils, and the first conductive element 510 and a second conductive element (not shown) are preferably made of copper having a thickness of about 1.2 mils to about 1.4 mils. It can be appreciated that many variations of the above embodiments might be made, which also are within the scope of the present invention. For example a resistor, capacitor, resistor, capacitor, and resistor in series may be formed by effecting the following coatings: a first conductive layer which coats at least a portion of the first gap side; a first dielectric layer which coats at least a portion of the first conductive layer; a second conductive layer which coats at least a portion of the first dielectric layer but is not in electrical contact with either gap side or the first conductive layer; a second dielectric layer coating the second conductive layer; and a third conductive layer coating at least a portion of the second dielectric layer, which is not in electrical contact with the second conductive layer, and which is in electrical contact with the second gap side. In yet another embodiment, the present invention provides a novel printed circuit board comprising an organic core and a non-discrete capacitive element. The non-discrete capacitive element includes: a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side; a dielectric layer insulating the first gap side from the second gap side; and a conductive layer coating at least a portion of the dielectric layer and in electrical contact with the second gap side. The dielectric layer may coat the conductive element directly as shown in Figures 1 and 2, or it may coat a conductive layer as shown in Figure 7. Optionally, it may coat a plurality of conductive layers. The conductive layer coating the dielectric layer of the above embodiment may similarly be coated with additional layers. This embodiment may be further limited in regards to materials choice, layer dimensions, etc., as described in the above embodiments and may be made by similar methods. Furthermore, the present invention is applicable to both digital and analog applications. Practice of the invention will be still more fully understood from the following theoretical examples, which are presented herein for illustration only and should not be construed as limiting the invention in any way.

Example 1 : Formation of a Two-Layer Non-Discrete Capacitive Element about the Edge of a Conductive Sheet in a Capacitor Laminate Layer A capacitor laminate having an organic core with a dielectric constant of about 4.7 and a thickness of about 1.5 mils, and copper conductive sheets having a thickness of about 1.2 mils to about 1.4 mils was provided. These capacitor laminates are available from Polyclad Laminates, Inc. (Franklin, New Hampshire) under the trade name FR4. A plurality of 13.5 mil vias were drilled in the laminate in 50 mil intervals with their centerpoints 28 mils from the edge of the laminate using a 13.5 mil drill bit. The vias were then plated with copper at a thickness of about 1 mil to form a buried vias core. An electrical isolation gap about 0.016 inches wide was etched about the perimeter of the laminate defining a 56 mil edge strip about the laminate. A polymer dielectric paste strip about 0.25 inches wide was coated along the interior edge of the electrical isolation gap such that the capacitive layer extended into the electrical isolation gap side by about 0.008 inches. This polymer dielectric paste contained barium titanate powder in a phenolic resin binder and is sold under the trade name CX-11 by Asahi Chemical Research Laboratory (Tokyo, Japan). The paste was thinned with butyl carbitol to adjust the viscosity and printed using a 200 mesh screen using standard printing techniques. This layer was allowed to dry at 140°C for about 30 minutes. A conductive layer about 0.28 inches wide was then applied such that the interior edge of the conductive layer was 0.01 inches from the interior edge of the dielectric layer and its exterior edge overlapped the exterior edge of the electrical isolation gap by 0.01 inches. The conductive layer was an emulsion of silver, diethylene glycol butyl ether, resins, butyl cellulosive acetate, graphite and carbon black sold by Emerson & Cuming Specialty Polymers (Canton, Massachusetts) under the trade name MINICO^® M-1010-RS. The conductive layer was printed using a 200 mesh screen using standard printing techniques. The layers were then cured for 30 minutes at 150°C. The cured dielectric paste has a 0.4 mil thickness. The capacitance is estimated to be approximately 152 nF, and the resistance approximately 0.1 to 0.2 ohms. Example 2: Formation of a Two-Layer Non-Discrete Capacitive Element in a Signal Trace Disposed on a Circuit Board Layer

An organic core was provided having a copper signal trace disposed thereon. The copper signal trace was about 0.0013 inches thick and 0.004 inches wide. The signal trace was widened to about 0.3 inches wide where the non-discrete capacitive element was to be formed. A electrical isolation gap about 0.02 inches wide was etched in the copper signal trace defining a first gap side 0.3 inches wide by 0.3 inches long, and a second gap side 0.3 inches wide by 0.04 inches long. A polymer dielectric paste about 0.28 inches wide by 0.3 inches long was coated along the first gap side of the electrical isolation gap in the trace such that the dielectric layer extended about halfway into the electrical isolation gap. The polymer dielectric paste contained barium titanate powder in a phenolic resin binder and is sold by Asahi Chemical Research Laboratory (Tokyo, Japan) under the trade name CX-11. The paste was thinned with butyl carbitol and printed using a 200 mesh screen using standard printing techniques. This layer was allowed to dry at 70°C for 10 minutes. A conductive layer was then applied over the dielectric layer and second gap side such that it spanned the electrical isolation gap. The conductive layer was about 0.26 inches wide and about 0.32 inches long, extending 0.02 inches onto the surface of the trace adjacent to the second gap wall on the second gap side, and extending across the dielectric layer to about 0.01 inches from the edge of the dielectric layer on the first gap side. The conductive layer was an emulsion of silver, diethylene glycol butyl ether, resins, butyl cellulosive acetate, graphite and carbon black sold by Emerson & Cuming Specialty Polymers (Canton, Massachusetts) under the trade name MINICO^® M-1010-RS. The conductive layer was printed using a 200 mesh screen using standard printing techniques. The layers were then cured for 30 minutes at 150°C. The cured dielectric paste had a 0.4 mil thickness. The capacitance was estimated to be approximately 3.65 nF. The capacitance and the resistance were measured by a Model 3330 Kiethley LCZ Meter. The capacitance was measured to be 3 nF and the resistance 5.5 ohms averaged over 20 readings.

Although generally the preferred embodiments of the invention have been shown and described, numerous variations and alternative embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims as the invention may be embodied in other specific forms.

Claims

CLAIMS What is claimed is:

1. A printed circuit board comprising: an organic core; and a non-discrete capacitive element comprising: a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side; a first dielectric layer coating at least a portion of the first gap side; and a first conductive layer coating at least a portion of the first dielectric layer and at least a portion of the second gap side and spanning the electrical isolation gap.

2. The printed circuit board of claim 1, further comprising: a second dielectric layer coating at least a portion of the first conductive layer and contacting the first dielectric layer; and a second conductive layer coating at least a portion of the second dielectric layer and a portion of the second gap side.

3. The printed circuit board of claim 1 , wherein the first dielectric layer coats at least a portion of the second gap side and is discontinuous about the electrical isolation gap.

4. The printed circuit board of claim 1 , where the conductive element is a copper signal trace.

5. The printed circuit board of claim 1 , wherein the conductive element is a ground plane of a multilayer printed circuit board and the electrical isolation gap is a slot which defines a first portion of the ground plane and a second portion of the ground plane.

6. The printed circuit board of claim 5, wherein the ground plane defines a perimeter and the second portion of the ground plane is an edge strip about the perimeter of the ground plane.

7. The printed circuit board of claim 6, further comprising a buried via connecting the ground plane to a power distribution plane located in the edge strip.

8. A method of forming a printed circuit board comprising an organic core and a non- discrete capacitive element comprising the steps: (a) providing an organic core of a printed circuit board having a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side; (b) coating at least a portion of the first gap side with a first dielectric layer; and (c) coating at least a portion of the second gap side and at least a portion the first dielectric layer with a first conductive layer such that the first conductive layer spans the electrical isolation gap.

9. The method of claim 8, further comprising the steps: (d) coating at least a portion of the first conductive layer and a portion of the first dielectric layer, with a second dielectric layer; and (e) coating at least a portion of the second dielectric layer and a portion of the first gap side with a second conductive layer.

10. The method of claim 8, wherein step (b) comprises coating at least a portion of the first gap side and a portion of the second gap side with a first dielectric layer such that the first dielectric layer is discontinuous about the electrical isolation gap.

11. The method of claim 8, where the conductive element is a copper signal trace.

12. The method of claim 8, wherein the conductive element is a ground plane of a multilayer printed circuit board and the electrical isolation gap is a slot which defines a first portion of the ground plane and a second portion of the ground plane.

13. The method of claim 12, wherein the ground plane defines a perimeter and the second portion of the ground plane is an edge strip about the perimeter of the ground plane.

14. The method of claim 13, further comprising a buried via connecting the ground plane to a power distribution plane located in the edge strip.

15. A printed circuit board comprising: an organic core; and a non-discrete capacitive element comprising: a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side; a first conductive layer coating at least a portion of the first gap side; a first dielectric layer coating at least a portion of the first conductive layer; and a second conductive layer coating at least a portion of the first dielectric layer, at least a portion of the second gap side and spanning the electrical isolation gap, such that first conductive layer is not in contact with the second conductive layer.

16. The printed circuit board of claim 15, further comprising: a second dielectric layer coating at least a portion of the second conductive layer and contacting the first dielectric layer; and a third conductive layer coating at least a portion of the second dielectric layer and contacting the first conductive layer.

17. The circuit of claim 16, where the conductive element is a copper signal trace.

18. The circuit of claim 16, wherein the conductive element is a ground plane of a multilayer printed circuit board and the electrical isolation gap is a slot which defines a first portion of the ground plane and a second portion of the ground plane.

19. The circuit of claim 18, wherein the ground plane defines a perimeter and the second portion of the ground plane is an edge strip about the perimeter of the ground plane.

20. The circuit of claim 19, further comprising a buried via connecting the ground plane to a power distribution plane located in the edge strip.

21. A method of forming a printed circuit board comprising an organic core and a non- discrete capacitive element comprising the steps: (a) providing an organic core of a printed circuit board having a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side; (b) coating at least a portion of the first gap side with a first conductive layer; (c) coating at least a portion of the first conductive layer with a first dielectric layer; and (d) coating at least a portion of the first dielectric layer and at least a portion of the second gap side with a second conductive layer, such that the second conductive layer spans the electrical isolation gap.

22. The method of claim 21 , where the conductive element is a copper signal trace.

23. The method of claim 21 , wherein the conductive element is a ground plane of a multilayer printed circuit board and the electrical isolation gap is a slot which defines a first portion of the ground plane and a second portion of the ground plane

24. The method of claim 23, wherein the ground plane defines a perimeter and the second portion of the ground plane is an edge strip about the perimeter of the ground plane.

25. The method of claim 24, further comprising a buried via connecting the ground plane to a power distribution plane located in the edge strip.

26. A printed circuit board comprising: an organic core; and a non-discrete capacitive element comprising: a conductive element disposed on a surface of the organic core, the conductive element defining an electrical isolation gap and having a first gap side and a second gap side; a dielectric layer insulating the first gap side from the second gap side; and a conductive layer coating at least a portion of the dielectric layer and in electrical contact with the second gap side.