WO2000075751A2

WO2000075751A2 - Processing a digital media data stream

Info

Publication number: WO2000075751A2
Application number: PCT/US2000/040169
Authority: WO
Inventors: Daniel J. Holmes
Original assignee: Media 100 Inc.
Priority date: 1999-06-09
Filing date: 2000-06-08
Publication date: 2000-12-14
Also published as: AU6120800A; WO2000075751A3

Abstract

A digital media data stream including image data (32) and ancillary data (36) is received at a digital media input circuit. The ancillary data includes ancillary data words and an index characterizing the ancillary data words and/or image data. A control signal is generated at an interpreter (29) based upon the value of the index. The ancillary data words and/or image data in are processed based upon the control signal, words with different indexes being processed differently. A memory (60) storing control data values can be used in the interpreter, the index being used to address the memory.

Description

PROCESSING A DIGITAL MEDIA DATA STREAM Background of the Invention The invention relates to a method and apparatus for processing and generating a digital media data stream.

Digital data can be used to record, create, and modify "media" including various types of image and audio data. ITU-R BT-656 is a standard that has been developed for the format and transmission of digital media data.

Video data are a particular type of image data in the form of a stream of digital data used to create sequential images that appear to be moving in real time to the observer. Analog video from a source such as a camera or video cassette recorder can be more easily edited after conversion to digital form.

A television image is generated by a raster pattern in which horizontal lines of the image are sequentially generated on the screen, such that an entire new screen is generated every l/30th of a second. When the analog television signals are digitized, there is a horizontal blanking interval at the end of each horizontal line of image data and two vertical blanking intervals during each frame (corresponding to a screen)- equal to the time for a number of horizontal lines.

Standards for the format and transmission of digitized television signals have been developed by the Society of Motion Picture and Television Engineers (SMPTE) . The standards includes standards for serial data interfaces operating at 270 MHz, 360 MHz, 540 MHz and 1.485 GHz and standards for parallel (10 -bit wide component video signal) digital interfaces operating at l/10^ch that of the serial interfaces: 27 MHz, 36 MHz, 54 MHz and 148.5 MHz (referenced here as ΞDI/10 Clock) . SMPTE 291M specifies the format for "ancillary data packets" that are embedded in the horizontal and vertical blanking periods of frames of digitized, serial video data. Referring to Fig. 7, ancillary data packet 153 is shown within horizontal blanking period 152 between two lines of pixel data 150. Ancillary data packet 153 includes a three-word (10-bits per word) ancillary data flag (ADF) 156, followed by a data identification word (DID) 158, a data block number word (DBN) 160 (for type 1) or secondary data ID word (for type 2), a data count word (DC) 162, user data words 164 (up to a maximum of 255 words) , and a checksum word 166. The ancillary data flag 156 marks the beginning of the ancillary packet 153; the data identification word 158 defines the user data format and may consist of one or more consecutive 10 bit values; the data block number 160 distinguishes successive ancillary packets with a common data DID, and the data count 162 defines the quantity of user words. Television equipment can access a DID to see if any ancillary data present are to be used by the particular piece of equipment. The user words can include audio data and other data. SMPTE standard 125M defines a 10-bit parallel digital video for a component video signal in the 4:2:2 format, and SMPTE 259M defines serial data. SMPTE 125M and 259M are subsets of ITU-R BT- 656, which supports both parallel and serial data.

As used herein, "ancillary data" can include any data that are not image related.

Summary of the Invention In one general aspect this invention concerns processing a digital media data stream including image data and ancillary data. The ancillary data include ancillary data words and an index characterizing the ancillary data words and/or the image data. The digital media data stream is received at a media input circuit, and the index is accessed and used to generate a control signal based upon the value of the index at an interpreter. The ancillary data words and/or the image data are then processed based upon the control signal . Ancillary data words or image data having one index are processed differently than some other ancillary data words or image data having a different index. In another general aspect, the invention concerns processing a digital video data stream including frames of video image data and blanking periods in which one or more blocks of ancillary data words and associated indices are embedded. The video data stream is received at a digital video input circuit, and the index is accessed and used to generate a control signal based upon the value of the index at an interpreter. The ancillary data words are then processed based upon the particular control signals that were generated. In another general aspect;, the invention concerns processing a digital data scream containing blocks of various types of data and indices^" associated with respective blocks of data. The digital data stream is received at an input circuit, and each index is used to address a memory storing control data values in an interpreter. The blocks of data are then processed based upon respective control data values that were read out of the memory with respective indexes .

Preferred embodiments may include one or more of the following features. The ancillary data words can include audio data words, time code, teletext or close captioning, secondary data, and compressed data. The handling of the data in the data stream can be easily changed by storing new control data values in the memory. The data stream can be a serial data stream or a parallel data stream; if serial, it can be converted to a parallel data stream. The index can be identified by recognizing an ancillary data flag in the data stream and using data in a known position following the ancillary data flag as the index. The control data value can include a value indicating that the index continues in a subsequent word, and the subsequent word can be used to address the memory a further time to read out a further control data value. The processing of data in the stream can include generating an enable signal to enable transmission of the data words to one of a plurality of processing pipelines. The pipelines can include an audio pipeline, a video pipeline and a further pipeline for data other than audio or image. The processed words can be stored at a cache memory for access by a host computer. In another general aspect, the invention concerns generating a digital video data stream including image data and ancillary data. A block of ancillary data for embedding in a frame including video image data and blanking periods are created at an append engine. The block of ancillary data includes ancillary data words and an index characterizing the ancillary data words. A digital video data stream including the frame is generated at the append engine, including embedding one or more blocks of ancillary data in the frame . The invention also features apparatus for processing and generating digital data streams.

Embodiments of the invention may include one or more of the following advantages. The use of a memory to store control values permits use of a large variety of different data types and processing options, and identifies proper processing quickly, e.g., m a clock cycle. Use of a programmable memory permits the control data values to be easily changed. Other advantages and features of the invention will

De apparent from tne following description of a preferred embodiment thereof and from the claims.

Brief Description of the Drawings Fig. 1 is a block diagram of circuitry for processing and generating a digital video data stream. Fig. 2 is a block diagram of an input path of a digital video input/output (I/O) circuit of the Fig. 1 system.

Fig. 3 is a block diagram of video, audio and ancillary processing circuits of the Fig. 2 input path.

Fig. 4 is a block diagram^" of a data interpreter of a digital video I/O circuit of the Fig. 1 system.

Fig. 5 is a diagram of a cache memory controller and host interface circuit of the Fig. 1 system. Fig. 6 is a diagram of an output data path of the

Fig. 1 system.

Fig. 7 is a diagram of an ancillary data packet.

Description of the Preferred Embodiment While the processing of a particular type of digital media stream s shown in the figures and described, any variety of digital data streams can be processed and generated. Referring to Fig. 1, system 10 for processing and generating digital video data streams includes digital video I/O circuit 12, video editing circuit 14 (e.g., available from Media 100 Inc. under the Media 100 (Macintosh) and Finish (NT) trade designations, and personal computer 16, which has an associated mass storage 18 and user input devices 20, monitor 22, and application software 24. Digital video I/O circuit 12 includes input path 26 and output path 28. Computer 16, e.g., can be programmed to carry out editing and compiling of a video program. U.S. Patent No. 5,471,577, DISPLAYING A SUBSAMPLED VIDEO IMAGE ON A COMPUTER DISPLAY, which is hereby incorporated by reference, describes such a video editing system.

Serial digital data according to ITU-R BT-656 (e.g., SMPTE 259M) are received at input port 30 and supplied to input path 26 for processing. Input path 26 converts the serial data into 10 -bit parallel data according to ITU-R BT- 656 (e.g., SMPTE 125M) and decodes the data into 16-bit or 20-bit video data that are output over lines 32 to video editing circuit 14, which includes processing pipelines 39, cache memory and controller 58, 60 and host bus master 41.

Input path 26 also extracts embedded audio data and provides it over path 34 to video editing circuit 14 and extracts ancillary data and provides it over path 36 to video editing circuit 14. Output path 28 similarly receives digital 16- bit or 20-bit video data over lines 38, audio data over lines 40, and ancillary data over lines 42 for combining and embedding into the ITU-R BT-656 serial data outputted at output port 44.

Referring to Fig. 2, it is seen that input path 26 includes serial data interface (SDI) receive circuit 46 and extraction circuit 50 (shown m detail in Fig. 4 and discussed below) . SDI receive circuit 46 includes serial digital receiver, decoder and error detection chips (e.g., as available from Gennum Corp.) , and provides a 10-bit ITU-R BT-656 output 160 to video, audio and ancillary detection and extraction 50 ana processing pipelines 39. While the audio is shown to nave a separate designation and processing pipeline in Fig. 2, audio data are still considered "ancillary data" herein) . Still referring to Fig. 2, video, audio and ancillary detection and extraction circuit 50 receives the 10-bit ITU-R BT-656 data scream 160, interprets the data and generates a steering signal which enables 10 -bit ITU-R BT- 656 data types of interest to be input into the video processing pipeline 52, the audio processing pipeline 54 or the ancillary processing pipeline 56. All processing pipelines are output, via the cacne memory controller 58, to the cache memory 60. Cache memory 60 is addressed into the address space of PCI bus 62 of video editing circuit 14. Referring to Fig. 3, the 10-bit ITU-R BT-656 data is input, when enabled by extraction circuit 50 (Figs. 2, 4), into the video processing pipeline 52. The data can be compressed at video compression circuit 66, decoded the digital video processor 48, or both. Digital video processor 48 converts the 10-bit input into an output data stream including 8-bιts or 10-bιts of Y and 8-bιts or 10- bits of CBCR. The outputs of processor 48 and compression circuit 66 are connected to multiplexer 68. The output of multiplexer 68 is connected to FIFO circuit 70 for temporary storage before the data are read by the cache controller circuit 58, into the cache memory 60.

Still referring to Fig. 3, the 10-bit ITU-R BT-656 data are input, when enabled by extraction circuit 50 (Figs. 2, 4), into audio-processing pipeline 54. Audio format circuit 74 consists of programmable logic that reformats the extracted audio data into a format that is compatible with the audio receiver/processor 76. The reformatted audio data is connected to the audio receiver/processors 76 and the audio input multiplexer 78. The audio receiver/processors 76 are American Engineering Society/European Broadcast Union (AES/EBU) decoders that decode two channels according to American National Standards Institute (ANSI) standard S4.40. Receiver/processor 76 is also connected to multiplexer 78. The output of the multiplexer 78 is connected to FIFO circuit 80 for temporary storage before the data are read, by the cache controller circuit 58, into the cache memory 60.

Still referring to Fig. 3, the 10-bit ITU-R BT-656 data are input, when enabled by the extraction circuit 50, into the ancillary data processing pipeline 56. The ancillary data undergo reformatting and packing at logic 84 for more efficient transfer to cache memory 60. The ancillary format and packing logic 84 is connected to FIFO circuit 86 for temporary storage before the data are read, by the cache controller circuit 58, into the cache memory 60.

Referring to Fig. 4, video, audio, ancillary detector and extraction circuit 50 includes control logic 88 and static random access memory (SRAM) decode memory 90. Control logic 88 includes SRAM control logic 89 and data steering logic 100 and can be implemented, e.g., as a field programmable gate array (FPGA) or a complex programmed logic device (CPLD) . SRAM control logic 89 receives the 10-bit ITU-R BT-656 data and also has a CPU interface 108 for software configuration of SRAM decode memory 90, and an "SDI/10" clock 92. (A clock that is at 1/lOth the rate of the serial data coming in, to handle 10-bit parallel words.) SRAM control logic 89 has a 16 -bit output 94 to input the 10-bit DID, sequence flags, and processor interface address to the address pins of SRAM decode memory 90, write enable control 96 to control SRAM decode memory 90, and 8-bit data input/output bus 98 to write and read data to and from SRAM decode memory 90. SRAM decode memory 90 stores 8-bit words used as control signals by control logic 89 and data steering logic 100. (Alternatively, memory 90 could store words with a different number of bits.) Data steering logic 100 has video extraction enable lines 102 to the video processing pipeline 52, audio extraction enable lines 104 to the audio processing pipeline 54, and ancillary extraction enable lines 106 to ancillary processing pipeline 56. Logic 100 also has other lines (not shown) to pipelines 52, 54, 56 to control operations in them (e.g., whether to compress at video compressor 66, whether to process at audio receiver 76, and how to process at logic 84) . Referring to Fig. 5, the cache controller and host interface 58 receives video FIFO status 108, audio FIFO status 110 and ancillary FIFO status 112 from the respective pipeline FIFOs (Fig. 3) . Cache controller 58 is configured, by software running on the host computer 16, to allocate sections of cache memory 60 for storage of extracted and processed video data, audio data, and many types of ancillary data. As data are available, cache controller 58 asserts a video read enable 114, audio read enable 116 or ancillary read enable 118 to pipeline FIFO's 70, 80, 86, respectively, and routes the received data to the appropriate location in the cache memory 60. The host 16 will read cache memory 60, via the cache controller 58, to retrieve and further process the extracted data. Referring to Fig. 6, output path 28 includes output audio FIFO 126, AES/ABU encode circuits 128 (available, e.g., from Crystal Semiconductor), output audio cue FIFO 130, output ancillary cue FIFO 132, append engine 134, error detection and handling circuit (EDH) 136 and SDI transmitter 138 (e.g., circuits 136 and 138 are both available from Gennum) . Append engine 134 is implemented as FPGA. The output processing and append pipeline generates a steady SDI/10 clock stream of 10-bit values needed to generate the serial ITU-R BT-656 output. EDH 136 generates CRC codes used in the standard to help identify and track errors. The operation of system 10 will now be described. Referring to Figs. 1-7, incoming digital video (e.g., according to ITU-R BT-656) is received at serial digital video receiver 46 at 270 MHz, where it is subjected to error detection. Serial digital video receiver 46 outputs 10-bit parallel digital video data to video processing pipeline 52 and video, audio and ancillary detection and extraction circuit 50 on a 27 MHz clock. The lines of pixel data 150 (Fig. 7) are decoded at digital video processor 48 in video processing pipeline 52.

When SRAM control logic 89 (Fig. 4) detects the three-word pattern of ADF 156 (Fig. 7) indicating the start of an ancillary data packet 153, SRAM control logic 89 then passes the next 10-bit parallel word (which is DID 158) over lines 94 to the lower 10 address bits of SRAM decode memory 90, which, following a short period (less than a 27 MHz clock period) needed for the SRAM data output to settle, outputs the 8 -bit data that had been addressed over lines 98. If the DID is a sequence of values, the SRAM sequence flags, which are the upper bits of the 8 -bit data 98, will be read by SRAM control logic 89 to indicate that the upper bits of the SRAM address 98 are to be manipulated along with the next DID in the sequence to point to a new interpreter location. Upon waiting the short interval (less than a clock period) needed for the SRAM output to settle, SRAM control logic accesses the 8 -bit data value that had been addressed by the DID 158 and uses the 3-bit data value to determine how the ancillary data packet should be processed. The DID value, or values, are thus efficiently interpreted in less than a single clock cycle, per DID word, by SRAM decode memory 90. If DID 158 indicates that the data are for the video channel, the appropriate video enable signal switches state on the appropriate line 102 (Fig. 4) to enable the appropriate pipeline. If DID 158 indicates that the data is for the audio channel, the appropriate audio enable signal switches state on the appropriate line 104 (Fig. 4) to enable the appropriate pipeline. If DID 158 indicates that the data are ancillary data, then the ANC enable over line 106 (Fig. 4) switches state to enable the ancillary pipeline; in addition, the particular type of ancillary data indicated by DID 158 can have an associated 8 -bit word that causes communication from SRAM control logic 88 to the host CPU over lines 108 to alert video editing circuit 14 as to the type of ancillary data being received. The processing of the 8-bit data value addressed by each DID 158 value and the change of state of enable lines 102, 104, 106 takes one SDI (27 MHz) clock period. On the next SDI clock, DID 158 is clocked out and into the enabled pipeline 52, 54, 56 (Fig. 2) . DBN 160 is used by SRAM control logic 88 to keep track of when the entire packet 153 has been received and read into the appropriate pipeline 52, 54, 56.

There can be two or more ancillary data packets 153 in each horizontal blanking period 152 (Fig. 7) . E.g., there can be one packet 153 for each of two pairs of audio channels (in fact there could be up to eight pairs of audio channels) and one or more ancillary packets 153 for different types of ancillary data. E.g., ancillary data can include time code, secondary audio, teletext, close captioning, and secondary data. Secondary data could be decoded to provide instructions for display on a monitor such as "go to commercial." The ancillary data space can also be used for compressed data. The serial digital video interface may consist of only ancillary data. So long as the user does not use DID values that are defined or are reserved (as indicated in Table A.l of SMPTE 291M) the user can assign DID values to define the ancillary data as desired. In addition, the user can change the data values that are stored in SRAM decode memory 90 and are addressed by the DID values in order to change the processing of data types or to accommodate new data types.

The audio data associated with a horizontal line 150 of pixel data will typically come in 27 MHz bursts that are stored in respective FIFO 74 (Fig. 3) . The audio data are read out of FIFO 74 in pairs of 32-bit words (one for each channel in the pair) in bit-serial fashion at some multiple of the audio rate. The 32 -bit words are then processed at AES/EBU receivers 76 (Fig. 3) and output to FIFO circuits 80 where the data can be read, by the cache controller/host interface 58 into video editing circuit 14. The ancillary data are reformatted and packed by logic block 84 (Fig. 3) and buffered into ANC FIFO 86 with the DID, DBN, and DC values for use in processing at video card 14. The ancillary data and associated values are periodically read into the cache memory 58 at a high rate. FIFO 86 is used to avoid repeated accesses of cache memory 50 with relatively small amounts of data. Cache memory 60 is accessed by host 16 or video editing circuit 14 over PCI bus 62 via the cache controller/host interface circuit 58 (Fig. 2) . The use of system 10 to generate a 291M serial digital video data stream is essentially the reverse of the operation just described for processing a serial digital video data stream. Referring to Fig. 6, audio is sent in bursts via the cache controller 58 to output audio pipeline FIFO 126. The audio data are read out continuously into the AES/EBU encode circuit 128, the encoded audio data is temporarily stored in audio output cue FIFO 130 and read in 27 MHz bursts when it s to be appended by append logic 134 onto the output data stream. Ancillary data are sent, via the cache controller 58, nto output ancillary FIFO 132, where data then are temporarily stored until needed m the construction of an ancillary data packet. The 10-bit ITU-R BT-656 output video write enable 146 drives the append engine 138 and indicates to the append engine 138 the current position m the video frame and in this way the append engine 138 can track where ana wnen video, audio and ancillary data are to ce inserted. Append engine 138 also generates the ancillary data packets 153 (Fig. ^~> ) and inserts them at the end of each appropriate horizontal line 150 (Fig. 7) of pixel data by first generating ADF 156, DID 158, DBN 160, DC 162 and then sending read enables to the appropriate FIFO pipe 130 or 132 to access 10-bit words at 27 MHz at the appropriate time. EDH 136 adds checksum 166 and the digital data according to ITU-R BT-656 are output by SDI transmitter 138 at 270 MHz.

Other embodiments of the invention are within the scope of the appended claims. E.g., the interface could be used to transmit other data instead of digital television αata. The invention is also applicable to other serial digital transport interfaces such as SMPTE 305M.

What is claimed is:

Claims

1. A method of processing a digital media data stream including image data and ancillary data comprising receiving said digital media data stream at a media input circuit, said ancillary data including ancillary data words and an index characterizing said ancillary data words and/or said image data, accessing said index and generating a control signal based upon the value of said index at an interpreter, and processing said ancillary data words and/or said image data based upon said control signal, ancillary data words or image data having one index being processed differently than some other ancillary data words or image data with a different index.

2. The method of 1 wherein said accessing and generating includes using said index to address a memory, and reading a control data value stored at said address, said data stored at said address being said control signal.

3. A method of processing a digital video data stream comprising receiving a digital video data stream including frames including video image data and blanking periods m which one or more blocks of ancillary data are embedded at a digital video input circuit , a said block cf ancillary data including ancillary data words and an index characterizing said ancillary data words, accessing said index and generating a control signal based upon the value of said index at an interpreter, and processing said ancillary data words in a frame based upon said control signal at an ancillary data processor, words with different indexes being processed differently.

4. The method of 3 wherein said accessing and generating includes using said index to address a memory, and reading a control data value stored at said address, said data stored at said aαdress being the control signal.

5. The method of claim 1 or 3 wherein said ancillary data words include audio data words.

6. The method of claim 1 or 3 wherein said ancillary data words include time code.

7. The method of claim 1 or 3 wherein said ancillary data words include teletext or close captionmg.

8. The method of claim 1^" or 3 wherein said ancillary data words include compressed data.

9. A method of processing a digital data stream containing various types of data comprising receiving said digital data stream at an input circuit, said stream including blocks of data and indices associated with respective blocks of data, accessing each said index to address a memory storing control data values and reading out a respective control data value stored at the associated address, and processing said respective block of data for each said index used to address said memory based upon said control data value, blocks with one index being processed differently than some other blocks with a different index.

10. The method of claim 2 , 4 or 9 further comprising storing said control data values in said memory.

11. The metnod of claim 1, 3 or 9 wherein said data stream is a serial data stream, and further comprising, after said receiving and before said accessing, converting said serial digital data stream into a parallel data stream.

12. The method of claim 1, 3 or 9 wherein said accessing includes recognizing an ancillary data flag m said data stream and using the data m a known position following said ancillary data flag as said index.

13. The method of claim 2, 4 or 9 wherein said control data value can include a value indicating that the index continues in a subsequent word, and using said subsequent word to address said memory to read out a further control data value .

14. The method of claim 1 wherein said processing includes generating an enable signal to enable transmission of said ancillary data worαs to one of a plurality of processing pipelines.

15. The method of claim 3 wherein said processing includes generating an enable signal to enable transmission of said ancillary data words to one of a plurality of processing pipelines.

16. The method of claim 9 wherein said processing includes generating an enaple signal to enable transmission of said blocks of data to one of a plurality of processing pipelines.

17. The method of claim 14, 15, or 16 wherein said pipelines include an audio pipeline and a further pipeline.

18. The method of claim 14, 15, or 16 wherein said pipelines include an audio pipeline, a video pipeline and a further pipeline, and wherein image data are processed at said video pipeline, and audio data are processed at said audio pipeline and data other than audio or image are processed at one or more further ^"pipelines .

19. The method of claim 14, 15 or 16, further comprising storing processed words at a cache memory for access by a host computer.

20. A method of generating a digital media data stream including image data and ancillary data comprising receiving said image data at an append circuit, receiving said ancillary data at said append circuit, generating one or more blocks of said ancillary data at said append circuit, each said bloc of ancillary data including ancillary data words and an index characterizing said ancillary data words and/or said image data, generating said digital media data stream, said data stream including sequences of said image data and a block of ancillary data between two said sequences of image data, and outputtmg said digital media data stream.

21. A method of generating a digital video data stream including image data and ancillary data comprising receiving frames of video image data at an append circuit, receiving ancillary data to be embedded in said frames at said append circuit, generating one or more blocks of said ancillary data at said append circuit for embedding in a said frame, each said blocK of ancillary data including ancillary data words and an index characterizing said ancillary data words, generating a frame of said digital video data stream, said frame including lines of said image data and blanking periods between said lines, each said block of ancillary data being included in a said blanking period, and outputting said digital video data stream.

22. The method of claim 20 or 21 wherein said ancillary data words include audio data words.

23. The method of claim 20 or 21 wherein said ancillary data words include time code.

24. The method of claim 20 or 21 wherein said ancillary data words include teletext or close captionmg.

25. The method of claim 20 or 21 wherein said ancillary data words mciuαe compressed data.

26. An apparatus for processing a digital media data stream comprising a digital video input circuit for receiving a digital media data stream including image data and ancillary data, said ancillary data including ancillary data words and an index characterizing said ancillary data words and/or said image data, an interpreter for accessing said index and generating a control signal based upon the value of said index, and a data processing circuitry for processing said ancillary data words and/or said image data based upon said control signal, words and/or image data with different indexes being processed differently.

27. An apparatus for processing a digital video data stream comprising a digital video input circuit for receiving a digital video data stream including frames including video image data and blanking periods m which one or more blocks of ancillary data are embedded, a said block of ancillary data including ancillary data words and an index characterizing said ancillary data words, an interpreter for accessing said index and generating a control sιgna_ cased upon the value of said index, and an ancillary αata processing circuitry for processing said ancillary data words in a frame based upon said control signal, words with different indexes being processed differently.

28. The apparatus of claim 26 or 27 wherein said interpreter includes control logic and a memory, said control logic being connected to use a said index to address said memory, said memory storing control data values, said control data stored at an address of said memory being said control signal.

29. An apparatus for processing a digital data stream containing various types of data comprising a digital input circuit for receiving said digital data stream, said stream including blocks of data and indices associated with respective blocks of data, an interpreter including a memory storing control data values, said interpreter accessing each said index to address said memory and read out a respective control data value stored at the associated address, and. a data processing circuitry for processing said blocks of data based upon said control data value, blocks with one index being processed differently than some other blocks with a different index.

30. The apparatus of claim 26 or 27 wherein said data processing circuitry includes a plurality of processing pipelines that are selectively enabled by said interpreter based upon said control signal.

31. The apparatus of claim 29 wherein said data processing circuitry includes a plurality of processing pipelines that are selectively enabled by said interpreter based upon said control data value.

32. The apparatus of claim 26, 27 or 29 wherein said data processing circuitry includes an audio pipeline and a further pipeline that are selectively enabled by said interpreter.

33. The apparatus of claim 26, 27 or 29 wherein said apparatus includes an audio pipeline, a video pipeline and a further pipeline, and wherein image data are processed at said video pipeline, audio data are processed at said audio pipeline, and data other than audio or image are processed at one or more further pipelines.

34. The apparatus of claim 26, 27 or 29 wherein said apparatus includes an audio pipeline, a video pipeline and a further pipeline, and wherein image data are processed at said video pipeline, audio data are processed at said audio pipeline, and data other than audio or image are processed at one or more further pipelines, and further comprising storing processed words at a cache memory for access by a host computer.

35. An apparatus fcr generating a digital media data stream including image data and ancillary data comprising a source of image data, a source of ancillary data, and an append circuit connected to said sources to receive said image data and ancillary data, said append circuit generating one or more blocks of ancillary data, each said block of ancillary data including ancillary data words and an index characterizing said ancillary data words, said append circuit generating said digital media data stream, said data stream including sequences of said image data and blanking periods between said lines and a block of ancillary data between two said sequences of image data, said append circuit having an output for outputting said digital media data stream.

36. An apparatus for generating a digital video data stream including image data and ancillary data comprising a source of frames of video image data, a source of ancillary data to be embedded in said frames, and an append circuit connected to said sources to receive said frames of video image data and ancillary data, said append circuit generating one or more blocks of ancillary data for embedding m a said frame, each said block of ancillary data including ancillary data words and an index characterizing said ancillary data words, said append circuit generating a frame of said digital video data stream, said frame including lines of said image data and blanking periods between said lines, each said block of ancillary data being included m a said blanking period, said append circuit having an output for outputting said digital video data stream.