WO2000064068A1 - Jitter measurement system and method - Google Patents
Jitter measurement system and method Download PDFInfo
- Publication number
- WO2000064068A1 WO2000064068A1 PCT/US2000/009107 US0009107W WO0064068A1 WO 2000064068 A1 WO2000064068 A1 WO 2000064068A1 US 0009107 W US0009107 W US 0009107W WO 0064068 A1 WO0064068 A1 WO 0064068A1
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- WIPO (PCT)
- Prior art keywords
- waveform
- signal waveform
- measurement
- oscillators
- oscillation signals
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
- H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
Definitions
- the present invention relates to a system and method for measuring time jitter in periodic signals and, in particular, to such a system and method that are suited to built-in self test applications for phase-locked loops.
- Phase-locked loops are used in a wide variety of applications including frequency synthesis, timing recovery, clock distribution, and phase demodulation. These applications are sometimes employed, for example, in optical fiber links, wireless telephones, and computers. In many of these applications, timing variations or jitter characteristics of a PLL can significantly affect the performance of the PLL and the application in which the PLL is used.
- a PLL may be used to recover a clock signal from a serial data stream.
- the recovered clock signal can have timing variations or "jitter.”
- a jittery clock signal can introduce errors in the reading of the serial data stream, thereby increasing the bit error rate for the data stream.
- measuring the performance of a PLL in terms of its jitter can be important to providing accurate clock recovery and lower bit error rates.
- some large integrated circuits include PLLs for clock generation.
- the PLL may provide a clock signal that is phase-shifted relative to a supply clock signal.
- Accurate operation of such an integrated circuit can require that the PLL provide the phase-shifted clock signal without jitter.
- Accurate measurement of jitter characteristics, including jitter characteristics of PLLs is needed for a wide variety of applications.
- PLLs increasingly being incorporated into larger-scale integrated circuits jitter measurement components suitable for built-in self test applications are also desirable.
- the present invention provides, therefore, a jitter measurement system for measuring timing variations or "jitter" in a periodic signal waveform as provided, for example, by a PLL.
- a PLL receives a periodic input signal waveform F REF and generates a periodic output signal waveform F vco with a frequency and phase that correspond to the input signal F REF .
- the jitter measurement system measures jitter in the output signal waveform F vco .
- the oscillator output signals function together as a vernier scale that provides high resolution period measurements.
- the extent to which the frequencies of the oscillator output signals are matched determines the resolution with which the jitter measurement system can measure the period of the output signal waveform F vco and hence its jitter.
- the frequencies are substantially matched in that they differ by less than 1 percent and, in some implementations, by 1/10 percent or less.
- oscillator output signals having frequencies that are about 100 MHz to within 1/10 percent are capable of period measurements to a resolution of about 10 picoseconds.
- Such a resolution is an order of magnitude better than that of available jitter measurement systems that are suitable for built-in self test (BIST) and automatic test equipment (ATE) applications.
- Fig. 1 is a block diagram of a jitter measurement system 10 for measuring timing variations or "jitter" in a periodic signal waveform.
- Jitter measurement system 10 is described herein with reference to measuring jitter in a signal waveform provided by a phase-locked loop (PLL) 12.
- PLL phase-locked loop
- phase-locked loops are used in a wide variety of applications such as frequency synthesis, timing recovery, clock distribution, and phase demodulation. These applications are sometimes employed, for example, in optical fiber links, wireless telephones, and computers. It will be appreciated, however, that jitter measurement system 10 may similarly measure jitter in periodic signal waveforms provided by other sources.
- jitter measurement system 10 includes a period gate generator 13 that generates a gate signal 14 that is labeled as and has the instantaneous period of the output signal waveform F vco .
- Gate signal 14 includes a leading edge 16 and a trailing edge 18 and is delivered to a pair of triggered oscillators 20 and 22 that provide respective oscillator output signals 24 and 26 with substantially matched frequencies. Oscillators 20 and 22 are triggered at, respectively, leading edge 16 and trailing edge 18 of gate signal 14.
- coincidence detector 34 may include a shift register that receives one of oscillator output signals 24 and 26 as a clock signal input (e.g., oscillator output signal 26) and receives the other of oscillator output signals 24 and 26 as a data input signal (e.g., oscillator output signal 24).
- the shift register would initially obtain the low (or zero) value of oscillator output signal 24 that is present as of the triggered leading edge of oscillator output signal 24. This low (or zero) value may be considered a coincidence data value and is indicated in Fig. 2 beneath oscillator output signal 24.
- Coincidence detector 34 delivers count termination signals to control inputs 36 and 38 of respective counters 30 and 32 when coincidence between output signals 24 and 26 is detected.
- oscillation counters 30 and 32 count the numbers of cycles of oscillator output signals 24 and 26 from when they are triggered from gate signal 14 until receiving the count termination signals.
- Histogram analysis component 40 may be implemented with a programmed processor or with a dedicated circuit as described, for example, in U.S. Patent No. 4,774,681. It is a relatively straightforward matter to process the resulting histogram to extract the peak to peak and rms values of the time jitter associated with Tvco.
- the counts provided by counters 30 and 32 may be used by a programmed or fixed circuit processor 42 to determine the period T vco of the gate signal 14 by the following equation:
- Tvco nT ⁇ ⁇ T 2 in which n and m are the numbers of oscillations, cycles, or periods determined by counters 30 and 32 and T and T 2 are the periods of oscillator output signals 24 and 26, respectively.
- the period of oscillator output signal 24 is greater than the period of gate signal 14 (and hence underlying output signal waveform F vco )
- the counts n and m will be equal, which simplifies the measurement determination to:
- Tvco nfT, - T 2 ).
- Fig. 4 is a flow diagram of a jitter measurement process 50 for measuring timing variations or "jitter" in a periodic signal waveform provided, for example, by a PLL.
- Process block 52 indicates that a first oscillation signal is triggered with reference to a leading edge of a selected period of the periodic signal waveform.
- the first oscillation signal may be triggered directly or indirectly from the selected period. Indirect triggering could employ a gate signal with an instantaneous period matching the selected period, as described above with reference to jitter measurement system 10.
- Process block 54 indicates that a second oscillation signal is triggered with reference to a trailing edge of the selected period. The second oscillation signal may be triggered directly or indirectly from the selected period.
- Process block 58 indicates that a period measurement is determined for the selected period from the numbers of periods of the first and second oscillation signals that are counted until the two signals coincide with each other.
- Process block 60 indicates that the period measurement for the selected period is incorporated into a jitter measurement analysis.
- the jitter measurement analysis includes multiple period measurements of the periodic signal waveform.
- Query block 62 represents an inquiry as to whether another period measurement is to be taken. Query block 60 returns to process block 52 whenever another period measurement is to be taken and otherwise proceeds to termination block 64.
- all components other than data processor 42 are incorporated into an integrated circuit in as a BIST system.
- incorporating jitter measurement system 10 or process 50 as a BIST component in an integrated circuit can provide enhanced accuracy in the measurement of jitter.
- the resolution and accuracy of jitter measurement system 10 improves with the degree to which the frequencies of oscillators 20 and 22 are matched. As described above, calculations of period measurements are based in part upon the difference in the periods of the oscillation signals provided by oscillators 20 and 22. Smaller differences in these frequencies provide greater resolution in the measurement.
- the frequencies are substantially matched if they differ by less than 1 percent and, in some implementations, by no more than 1/10 percent. Such close matching of the frequencies is better achieved when oscillators 20 and 22 are located together on a common circuit substrate, as would be the case in a BIST implementation.
- oscillators 20 and 22 are operated continuously. Whenever a jitter measurement is to be performed, oscillators are temporarily turned off until they are re-started in response to their selected trigger events (e.g., leading or trailing edges of gate signal 14). The oscillators are turned off for 5 to 7 cycles (of the periodic signal being measured) prior to activating the clock gate. In this implementation, the temporary times that oscillators are turned off are insufficient for the underlying regions of the circuit substrate to cool enough to create thermal differences that cause appreciable frequency differences.
- a common circuit substrate for oscillators 20 and 22 provides a thermal environment that allows them to be implemented as relatively simple, independent, free-running oscillators.
- the match between the frequencies of oscillators 20 and 22 may be calibrated prior to a measurement.
- the frequency match can be adjusted to be within the required tolerance, e.g. 0.1 percent, during a frequency calibration operation conducted immediately before the measurement.
- U.S. Patent No. 4,164,648 describes a time interval measurement system that uses triggered phase-locked oscillators.
- phase-locked oscillators terminates time measurement counts based upon coincidence between the phase-locked oscillators and a separate time base signal.
- the relative complexity of such a system makes it comparatively expensive to implement and ill-suited to use in BIST applications.
- schemes for measuring jitter rely on using time or frequency standards having better short term stability than that of the signal to be measured. The subject scheme does not. Instead its resolution is based upon the requirement that the relative difference between the two matched ring oscillator frequencies be smaller than the relative difference in period (i.e., jitter) to be measured.
- matched variations in the frequencies of the oscillators do not degrade the measurement resolution, even if the variations (e.g., jitter) in the oscillator signals are greater than the relative difference in period to be measured.
- variations in the power supply voltage can cause variations in the periods of the two oscillator signals (i.e., jitter). This jitter would be common to the two oscillators, and would not adversely affect the measurement accuracy.
- jitter caused by temperature variations affecting the common substrate on which the oscillators are located would be common to the two oscillators and would not adversely affect the measurement accuracy.
- the jitter of the oscillators may be greater than the jitter to be measured.
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- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00923137A EP1171961A4 (en) | 1999-04-20 | 2000-04-06 | Jitter measurement system and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/295,142 US6295315B1 (en) | 1999-04-20 | 1999-04-20 | Jitter measurement system and method |
US09/295,142 | 1999-04-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000064068A1 true WO2000064068A1 (en) | 2000-10-26 |
WO2000064068B1 WO2000064068B1 (en) | 2000-12-14 |
Family
ID=23136407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/009107 WO2000064068A1 (en) | 1999-04-20 | 2000-04-06 | Jitter measurement system and method |
Country Status (3)
Country | Link |
---|---|
US (2) | US6295315B1 (en) |
EP (1) | EP1171961A4 (en) |
WO (1) | WO2000064068A1 (en) |
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US20010049757A1 (en) * | 2000-03-01 | 2001-12-06 | Ming-Kang Liu | Programmable task scheduler for use with multiport xDSL processing system |
US20030076181A1 (en) * | 2000-03-17 | 2003-04-24 | Sassan Tabatabaei | Tunable oscillators and signal generation methods |
US6754613B2 (en) * | 2000-03-17 | 2004-06-22 | Vector 12 Corporation | High resolution time-to-digital converter |
US6735538B1 (en) * | 2000-03-29 | 2004-05-11 | Advantest Corporation | Apparatus and method for measuring quality measure of phase noise waveform |
US6661266B1 (en) * | 2000-11-08 | 2003-12-09 | Texas Instruments Incorporated | All digital built-in self-test circuit for phase-locked loops |
GB2368651B (en) * | 2000-10-31 | 2006-05-31 | Consultronics Europ Ltd | Method and apparatus for measurement of jitter |
US6525523B1 (en) * | 2000-11-24 | 2003-02-25 | Advantest Corporation | Jitter measurement apparatus and its method |
US6922439B2 (en) * | 2001-03-16 | 2005-07-26 | Advantest Corporation | Apparatus for and method of measuring jitter |
US6850051B2 (en) * | 2001-03-26 | 2005-02-01 | Mcgill University | Timing measurement device using a component-invariant vernier delay line |
US6874107B2 (en) * | 2001-07-24 | 2005-03-29 | Xilinx, Inc. | Integrated testing of serializer/deserializer in FPGA |
US7212022B2 (en) * | 2002-04-16 | 2007-05-01 | Transmeta Corporation | System and method for measuring time dependent dielectric breakdown with a ring oscillator |
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US6703884B2 (en) | 2002-05-30 | 2004-03-09 | Texas Instruments Incorporated | System and method for distributing a reference clock in an integrated circuit using filtered power supply line |
US7110446B1 (en) * | 2002-07-26 | 2006-09-19 | Xilinx, Inc. | Method and apparatus for reducing effect of jitter |
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US7340381B2 (en) * | 2002-10-04 | 2008-03-04 | University Of Washington | Characterization of radio frequency (RF) signals using wavelet-based parameter extraction |
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US20050229053A1 (en) * | 2003-07-25 | 2005-10-13 | Logicvision, Inc., 101 Metro Drive, 3Rd Floor, San Jose, Ca, 95110 | Circuit and method for low frequency testing of high frequency signal waveforms |
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US7627790B2 (en) * | 2003-08-21 | 2009-12-01 | Credence Systems Corporation | Apparatus for jitter testing an IC |
US7409617B2 (en) * | 2004-09-30 | 2008-08-05 | Credence Systems Corporation | System for measuring characteristics of a digital signal |
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US7286947B1 (en) * | 2006-04-13 | 2007-10-23 | International Business Machines Corporation | Method and apparatus for determining jitter and pulse width from clock signal comparisons |
CN100501423C (en) * | 2006-04-18 | 2009-06-17 | 北京大学深圳研究生院 | High-frequency clock jitter measuring circuit and calibration method thereof |
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US7684478B2 (en) * | 2006-06-30 | 2010-03-23 | International Business Machines Corporation | Generating an eye diagram of integrated circuit transmitted signals |
US7383160B1 (en) * | 2006-06-30 | 2008-06-03 | International Business Machines Corporation | Method and apparatus for constructing a synchronous signal diagram from asynchronously sampled data |
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TWI342403B (en) * | 2007-09-29 | 2011-05-21 | Ind Tech Res Inst | Jitter measuring system and method |
GB0807625D0 (en) * | 2008-04-25 | 2008-06-04 | Glonav Ltd | Method and system for detecting timing characteristics in a communications system |
US8793536B2 (en) | 2012-08-22 | 2014-07-29 | Tektronix, Inc. | Test and measurement instrument with auto-sync for bit-error detection |
US8917109B2 (en) | 2013-04-03 | 2014-12-23 | United Microelectronics Corporation | Method and device for pulse width estimation |
US9568548B1 (en) | 2015-10-14 | 2017-02-14 | International Business Machines Corporation | Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping |
US10520901B2 (en) * | 2018-02-23 | 2019-12-31 | Qualcomm Incorporated | Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation |
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- 1999-04-20 US US09/295,142 patent/US6295315B1/en not_active Expired - Fee Related
-
2000
- 2000-04-06 WO PCT/US2000/009107 patent/WO2000064068A1/en not_active Application Discontinuation
- 2000-04-06 EP EP00923137A patent/EP1171961A4/en not_active Withdrawn
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2001
- 2001-09-24 US US09/962,006 patent/US20020106014A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
EP1171961A4 (en) | 2005-09-07 |
WO2000064068B1 (en) | 2000-12-14 |
EP1171961A1 (en) | 2002-01-16 |
US20020106014A1 (en) | 2002-08-08 |
US6295315B1 (en) | 2001-09-25 |
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