WO2000062470A1 - Systeme de reseau synchrone universel pour processeur internet et environnement de fonctionnement internet - Google Patents

Systeme de reseau synchrone universel pour processeur internet et environnement de fonctionnement internet Download PDF

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Publication number
WO2000062470A1
WO2000062470A1 PCT/US2000/010101 US0010101W WO0062470A1 WO 2000062470 A1 WO2000062470 A1 WO 2000062470A1 US 0010101 W US0010101 W US 0010101W WO 0062470 A1 WO0062470 A1 WO 0062470A1
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WIPO (PCT)
Prior art keywords
phase
channel
signal
com2000
frequency
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PCT/US2000/010101
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English (en)
Inventor
Francois Trans
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Saphire Communications, Inc.
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Publication date
Priority claimed from US09/417,528 external-priority patent/US6553085B1/en
Priority claimed from PCT/US2000/006842 external-priority patent/WO2000062415A1/fr
Application filed by Saphire Communications, Inc. filed Critical Saphire Communications, Inc.
Priority to CA002370634A priority Critical patent/CA2370634A1/fr
Priority to AU47990/00A priority patent/AU4799000A/en
Priority to EP00930112A priority patent/EP1173949A1/fr
Publication of WO2000062470A1 publication Critical patent/WO2000062470A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03356—Baseband transmission
    • H04L2025/03363—Multilevel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H04L2025/03484—Tapped delay lines time-recursive
    • H04L2025/0349—Tapped delay lines time-recursive as a feedback filter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H04L2025/03509—Tapped delay lines fractionally spaced
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03592—Adaptation methods
    • H04L2025/03598—Algorithms
    • H04L2025/03611—Iterative algorithms
    • H04L2025/03617—Time recursive algorithms

Definitions

  • Video, Voice, Data delivery systems are the current mechanism of extending the human perceptions or Tele-senses .
  • Each of the communication means have made many independently advances in the past decade. Still, the voids are still there and hence there is a need to invent new technology for striving and enabling the human Tele-senses in a global scale.
  • New application types drive new demands on the communication infrastructure as to integrate all of the existing technologies to a seamless manner for delivering the human Tele- senses.
  • the capacity of the backbone and edge network links has been the main bottleneck in a data and telecommunication system.
  • the evolution of high speed data transfer at the telecommunication edge changes this situation; with the large amount of data capacity offered by ATM/SONET backbone networks, the bottleneck is moving towards the processing and buffering in switch-points and end-points.
  • the same also applies to the wireless as well as for data communication with 10/100/1000 Mb/s Ethernet edge communication devices.
  • Each of these communication methods have their own unique services, protocols and centralized processing architecture.
  • circuit-switched networks for existing wireline Telecommunication backbone and edge have many attractive properties in terms of providing real-time services from end- equipment to end-equipment.
  • circuit-switched networks which are only available for the telecommunication infrastructure, have been too inflexible to provide a data service that is suitable for a wireline data communication and wireless data communication integrated services network.
  • the Com2000 Technologies described below supports a new data communication architecture.
  • the new architecture is the Unified Communication System - Fast Circuit Switch (packet/circuit) communication processors which enables a new Internet Exchange Networking Processor Architecture .
  • the Com2000 Technologies set out to increase speeds over any communication channels, synchronizing, enabling, improving, controlling and securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data com backbone, is illustrated in Figure 02. III. Summary of the Invention
  • the Com2000TM Technologies increase speeds over any communication channel, synchronizing, enabling, improving, controlling and securing all of the data transmission of Web OS enabled applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data com backbone.
  • the Com2000 t Technology addresses all of the challenges for the new unified architecture of packet/circuit processors of internet networking processor, which includes the increased speed and delivery of a highly integrated services and solutions of the convergence nature of Security and Intelligence limitations over existing wireline and wireless data communication and telecommunication infrastructures.
  • the breakthrough Com2000 tm Speed, Security and Intelligent solutions enabling increase speed and robust transport schemes, over existing copper wire line and wireless infrastructures, illustrated in Figure 03.
  • Com2000TM technologies represents a collection of state-of-the-art schemes in multi-channel signal modulation coding, advance adaptive equalization, precision synchronization, reconfigurable DSP structures to increase speed and to deliver real-time, robust and deterministic multiple-access, and intelligence transport protocols which can be used for mapping of legacy protocols. It reflects the concept of reconfigurable and remote computing internet networking processor applied to future communications so-called software radio/wireless/wireline or web transceiver/internet processor.
  • Com2000 tm Speed technology addresses the current wireless and wireline capacity limitation and challenges with a highly integrated solution that will enhance any data and telecommunications where noise is a problem.
  • This technology can be applied and deployed in numerous major market segments such as Standard Compliance High Speed Networking lOOOBaseT Copper Gigabit (802.3ab) Single & Quad, or Broadband Access (HDSL2 focus) and other high-speed wireless and wireline networking.
  • This technology can be applied and deployed in numerous new major market segments such as Next Generation High Speed Networking 2000BaseT (2G/s) Copper Gigabit (802.3ab+) Single & Quad, 10 Gigabit Networking over Copper, Next Generation Fiber Channel SAN over copper, Next Generation Broadband Access (HDSL3 w/ 3Mb/s), Next Generation lOOMb/s Home Networking over POTs and other next generation high-speed wireless and wireline networking applications.
  • 2G/s Copper Gigabit (802.3ab+) Single & Quad
  • 10 Gigabit Networking over Copper Next Generation Fiber Channel SAN over copper
  • Next Generation Broadband Access HDSL3 w/ 3Mb/s
  • Next Generation lOOMb/s Home Networking over POTs
  • other next generation high-speed wireless and wireline networking applications such as Next Generation High Speed Networking 2000BaseT (2G/s) Copper Gigabit (802.3ab+) Single & Quad, 10 Gigabit Networking over Copper, Next Generation Fiber Channel
  • the CO ⁇ LZOOO 1 " 1 Speed technology represents the collection of state-of-the-art FIR filtering schemes in multi-channel signal coding (advance adaptive equalization) that enhance the channel Inter-symbol Interference (ISI) and Cross Talk noise suppression for wireline and Multipath Noise and Fading Suppression for wireless applications, as illustrated in Figure 04.
  • the initial wireline applications for the technology are Copper Gigabit Ethernet and HDSL2.
  • SNR signal to noise ratio
  • Analysis shows an improvement of the SNR by 8dB over Copper Gigabit with respect to the 802.3ab IEEE Standard suggested 10 dB receiver designs. It further shows a >5 dB SNR improvement over the current HDSL2 suggested front-end designs of Tl/El on the downstream and >3 dB upstream for crosstalk models represent the 1% worst-case coupling scenario for all the packings of N disturbers into a 50-pair binder group.
  • the present invention can be used to increase the higher performance and data rate capacity of the channel or to reduce the cost of the channel. For example, increasing the SNR results in simpler Forward Error Correction (FEC) and filtering schemes that reduce the design complexity which leads to power savings and die size reduction. This can be used in higher performance applications such as higher speeds or longer distance.
  • FEC Forward Error Correction
  • the enhanced SNR coupled with the multichannel signal coding can be used to deliver the increased bandwidth.
  • the new transceiver can deliver lOOOMb/s over 200 meters vs. 100 meter 802.3ab standard for longer distance applications or 2000Mb/s vs.
  • the new transceiver can deliver 1.5Mb/s over 18Kft vs. 12Kft HDSL2 Tl/El standard for longer distance applications or 3Mb/s vs. 1.5Mb/s standard for higher speed applications.
  • Com2000 tm Intelligence - Modem technology in general, utilizes a combination of the frequency division, phase division and time division duplex techniques in signal coding and latency controls to provide new and integrated solutions for next generation universal synchronous networking communications. It supports legacy modulations and also as an integrated platform for 2-dimensional CDMA (Phase), TDMA (Time) and FDM (Frequency) multi-access schemes. Each of these legacy schemes in each of the transmitting domain will be further exploited for higher data rate transfers with the help of 3-dimensional multi-access scheme and controls.
  • a new Com2000 tm data delivery architecture for wireline and wireless is the shared or non- shared medium access with multi-channel networks with the support of synchronous and controlled environment.
  • the Com2000 tm Intelligent (Modem)- Precision Clock Transfer technology is used to enable the synchronous data communication networks.
  • the precision clock transfer and control technology relates to stringent applications such as ITU global and local synchronization level service of SONET and telecom synchronization, as illustrated in Figure 02.
  • Com2000 tm Intelligence (Modem) - Channel Measurement and Calibration Control Technology measures and calibrates the communication channel to determine the highest possible data capacity for a particular medium, as illustrated in Figure 05.
  • Advanced Channel Measurement & Control techniques also enable any topology media channel calibration for optimal signal controls and intelligence flow.
  • Today's cable and wireless communication infrastructures are less than ideal.
  • the communications channel must be first characterized so that errors and imperfections, such as frequency, phase, time and other distortions, can be identified.
  • Com2000 tm s calibration system then uses these measurements to improve communication channel resolution by controlling the errors and imperfections of the channel.
  • the Residual measurements of the Com2000 t Intelligence (Modem) - Channel Measurement and Calibration Control (343) system are very powerful tools for troubleshooting and calibrating communications across any wireline and wireless channels. Once the reference signal has been subtracted, it is easier to see small errors that may have been swamped or obscured by the signal distortion and modulation itself.
  • non-uniform noise distribution or discrete signal peaks indicate the presence of externally coupled interference.
  • a goal of the Com2000TM Measurement and Calibration system is to ensure that the sending and receiving of selected parameters are measured and calibrated. Seven parameters measured by the Com2000TM Measurement system include power, frequency, phase, timing and other code modulation accuracy related parameters.
  • the frequency and phase counter capabilities provide another method of measurement for the Com2000TM Measurement (343) system for determining the channel transmission medium frequency and phase distortions.
  • Com2000TM Measurement Technology is used to measure many parameters that contribute to the propagation delays of communication channel infrastructure.
  • the Com2000TM Measurement circuitry is also used to measure phase interval, frequency, period, pulse width, phase, rise and fall time and also does event counting
  • the Com2000 Technologies set out to adapt over any communication channels and topologies.
  • the Com2000 tm Intelligent (Modem) - Advanced Medium Adaptation & Equalization Technology seamlessly filter adaptation techniques over any channel's topologies in any wireless & wireline infrastructure such as bus, point-to-point, point-to-multipoint, mesh, etc., so that higher speed and more reliable data transmission may be achieved, as illustrated in Figure 05.
  • the Com2000 tm Intelligent (Modem) - Multi-Channel Signal Coding technology allow to deliver higher data rates in a unique way from a single continuous or burst streams carrier frequency.
  • the technology delivers multi-channel (phase division) network architecture that uses parallel bitstream in a novel way. It uses the non-complex or complex base band symmetry signal with phase division multiplex coding scheme or PDM to deliver the multi-channel requirements which also meets the selected media FCC constraints, as illustrated in Figure 05.
  • the phase domain's multi-channel wireline and wireless network utilize the optimal phase division multiplexing (PDM) for multi-channel wireline and wireless network.
  • PDM phase division multiplexing
  • the Com2000 tm Intelligent (Modem) - Precision Sampling technology enables to the precision sample the signal's parameters any or combination of the Time (Multi-Time Slot sampling), Phase (Multi-Channel Phase sampling) and Frequency (Multi-Carrier sampling) signal spaces, as illustrated in Figure 05.
  • the signal coding and decoding is orchestrated in a "Relative" Phase Synchronization manner.
  • the receivers recover the clock and phase from the received signal and use it for the sample timing to recover the data.
  • Our enhanced technique is not only to deliver the "Relative” Synchronization scheme, but it also delivers the "Absolute” Synchronization technique to enable multitude of novel ways to increase bandwidth and intelligence controls.
  • the ordinary and single carrier frequency channel can be interpreted in a vector of channels, which can be characterized through precision phase channel measurement and calibration. Every other channel in a multi-channel media will be a non-interference channel with respect to the other channel and the selected M-PAM or M- QAM signal coding can be used to transmit over channels as in the current scheme.
  • INTELLIGENCE Today a network carrier can be analogized with an airline business. You buy jumbo jets and attempt to ensure that all the seats in that jet are full. The goal is to make sure the network is full all the time. All traffic today is delivered via cargo class, but emerging needs such as voice and video traffic will require higher priority and must be upgraded to first class. With this capability, the present invention also allows to monitor which traffic moves in which class, and charge higher rates for better service. The carriers want to find ways to extract more revenue, and we are going to provide that capability of offering different tiers of network service. The carrier would also be able to have more intelligence about what their customers are doing with the network, so they could have separate billing for voice traffic or for Internet traffic, as illustrated in Figure 01.
  • Com2000 tm Intelligence (Transport) - QoS Transfers technology utilizes a synchronous and controlled environment via a precision clock transfer and controls resident at the edge and the core of the network, to deliver universal and next generation synchronous, isochronous and asynchronous integrated data services or a novel Synchronous and Distributed Switching and Routing method.
  • This precision controlled synchronous clock transfer technology not only enables the physical layer to communicate in increased speeds with a high capacity multi-channel and shared medium access, but also provides a basis for true quality of service, or Hard QoS. This can fundamentally be interpreted as a universal transport mechanism for integrated services that seamlessly map into and out of any new or current and legacy data com and telecom protocols.
  • This universal transport mapping or Fast Protocol Synchronous Circuit Switching which is anything over anything transport mechanism such as IP over ATM, IP over SONET, ATM over IP, ATM over SONET, PPP over SONET, ..etc. is applicable to all protocols from a very stringent synchronous services such as SONET, loosely isochronous services such as ATM and Frame Relay, etc, to a very loosely and best effort asynchronous data services such as Internet IP protocols.
  • the data processing intelligence distributed QoS/switching/routing
  • networking system intelligence Advanced Bandwidth Improvement via TCP/UDP/IP Latency Suppression, Timed Policy Based System Management, Web Remote Computing, and many other applications
  • the ultra high speed bandwidth and network element and data processing intelligence enable a new architecture such as the Fast Data Synchronous Circuit Switching architecture which the fabric intelligence performs most of its tasks at the edge such as: fragmentation/defragmentation of the received packet based into Cell based for QoS controls and other network element intelligence such as the Switching/Router Functional intelligence in a distributed intelligence manner.
  • networking intelligence tasks such as addressing, switching or forwarding, routing, policing and shaping, sequencing and flow controls for each switching node, for example, can be migrated to the edge node systems or Com2000TM UniNet PHY in this case.
  • the high speed network connection between the end node(s) and the core node(s) is (are) just the extension of the "QoS" switching fabric, as illustrated in Figure 06.
  • the ultra optimized method of time division multiplexing (TDM) data of the UniNet PHY the network system intelligence are enabled with a new architecture Fast Transport Synchronous Circuit Switching architecture which the network intelligence performs most of its tasks at the edge such as: (a) Multiprocessor TDM Networking Operating System & Scheduling which can be used in different remote OS applications such as fragmentation/ defragmentation of the received TCP/IP packet based into TDM cell TCP/IP based for further bandwidth improvements; (b) Time Policy based Management; (c) Follow the SUN Management (Universal UTC-Time based Management) ; (d) Web Remote Computing; and many more other applications.
  • TDM time division multiplexing
  • Advanced TCP/UDP/IP Latency Reduction and TDM Scheduling Software Techniques which are derived from Fast Transport Synchronous Circuit Switching, to further improve the bandwidth or capacity at the upper layer, e.g., when the layers deal with the information that are transferring over the data line for a convergence data/video/voice related applications and host.
  • Each application such as in Video (Video Conference - TCP/IP) or Data (Email - UDP/IP ) or Voice (Tele- Conference TCP/IP) has the dedicated network connection such as IP addresses for different host nodes or/and at different TCP ports addresses for the same host node that is hosting all of the related applications.
  • DOCCIS 1.1 for cable modem of most home with digital cable MSC internet access will be installed with this single IP address scenario.
  • Telephone carrier xDSL for Telephone Digital Services allow more than one IP address for each of the access node, as illustrated in Figure 01. SECURITY
  • Com2000 tm Security - E-DNA Technology of packet/circuit processors for internet networking processor technology set out securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data-corn backbone.
  • SSI Com2000 tm Security is to deliver, in a novel way, the lowest encryption and decryption layer possible without significantly impacting the speed by generating unique electronic signal signatures that proliferate through the entire data communication network, as illustrated in Figure 02.
  • the Com2000 tm Technology addresses Speed, Security and Intelligence limitations of the new information communication challenges, not only at the physical level for universal shared and non-shared medium interface, such as POTs, CAT5, wireless etc.; but also at the universal transport layer with stringent telecom delays & jitter requirements for Circuit Switching time sensitive related applications at media access layer or above.
  • Com2000 t Technology addresses and meets all of the above challenges for the new unified architecture of packet/circuit processors for internet networking processor requirement and solutions, as illustrated in Figure 02.
  • This new unified network can be used, in ISO application layer, directly for application-to- application communication or may be used in physical, data and transport layers as a carrier network for other protocols, such as ATM, ISDN or IP.
  • the universal law of the unified network apply and traverse across the ISO layers for which it supports the legacy and new protocols for each of the ISO layer with the most optimal delivery mechanism.
  • Com2000 tm Technology for next generation universal synchronous networking communications will not only coexist with all legacy communication system but also as a new information communication platform that can be used to enable new technology advancement for future data communication challenges.
  • the freeway traffic and its associated traffic congestion also increases. Due to increasing demand for commuting car, trucks, semi (data type loads) in the metropolitan (Internet) area, the freeway (Internet data freeway) needs to be widened so that new lanes can be built and traffic regulations are needed in place for accommodating new traffic type and demands.
  • the freeway overpasses are added and needed to be re-architectured for easy access, freeway changeover, freeway entry, exits and timely regulated freeway admission during the particular time of the day.
  • the commute lanes are also created during certain time of the day for removing traffic congestion. Notice that we can see all of our traffic demands and loads are correlated to our working hours.
  • the demands are different and different time zone for example of pacific and eastern time zone or world standard time (UTC) as far as the global scale traffic demand is concerned.
  • the Com2000 tm Speed Technology addresses the capacity (widen the road) of the network over the existing infrastructure copper links which has been the main bottleneck in a broadband access and high speed networking data communication system at the edge and the core of the network.
  • the demands for high-capacity communications keep increasing at an exponential rate in recent years and have opened doors for opportunities to offer broadband communications solutions for multimedia services.
  • the revolutionary Com2000 tm Speed Technology of the wireline copper changes this situation; with the large amount of data capacity offered by copper at the edge networks.
  • the bottleneck is still moving towards the processing and buffering in central switch-points of the enterprise and telecom networks.
  • the Com2000 tm Speed and Intelligence transceiver technology can deliver up to 2.4Gb/s over existing 4 pairs CAT5 infrastructure for enterprise high speed networking backbone with the intelligence of distributed switch-points processing.
  • SSI's Con ⁇ OOO 1 TM Speed technology offers a unique approach for suppressing ISI and cross talk noise to previously unprecedented low levels, to guarantee and even increase the bandwidth (Signal to Noise Ratio) available over the existing copper cable infrastructure.
  • An aspect of Com2000 tm Speed technology is a collection of state of the art filtering schemes which filter noise intelligently in both the pre-ISI and post-ISI processing, interference and signal distortion and hence substantially boosting the signal-to- noise ratio.
  • SSI Com2000 tm Speed or Noise Suppression via Advanced Equalization Techniques are invented to increase capacity of any channel such as to deliver a ⁇ 3x Signal to Noise Ratio Increase over existing copper infrastructure so that higher speed and more reliable data transmission can be achieved.
  • Com2000 tm Intelligent Technology addresses and resolves the bottleneck problems at the edge and core of the network (overpasses and traffic regulations).
  • the new generation fast circuit- switched network architecture is addressed to enhance the current legacy circuit-switched techniques to a high capacity multimedia network with an integrated services environment.
  • This new architecture is interoperable with a robust protocol suite in which is only available at the telecommunication fiber backbone such as SONET, and WDM transports.
  • the legacy and current Circuit-switched for the existing telecommunication architecture and packet-switched networks of data communications have very different characteristics. They can both support an integrated service environment, but have different merits in terms of providing various service aspects.
  • a new fast or next generation integrated network architecture that is an effort to enhance existing circuit-switched techniques of telecommunication and with seamless integration to existing packet switching system of the wireless and wireline data communication domain are required for the next generation data transfer and delivery infrastructure.
  • This new Intelligent architecture should seamlessly extend a high capacity to the edge of the network with an integrated service environment and seamlessly integrate with the existing wireline and wireless backbone networking without having to resolve the heavy bottleneck processing and buffering in switching points and end- points.
  • the Com2000TM Intelligent technologies for modem offer automatic selection of operating spectrum and bandwidth for a given medium transmission rate and modulation adaptively to given environment to select the optimum capacity versatility and universal in topology: bus (mesh), star (point-to-multi-point), linear (point-to-point), robustness and deterministic in transmission, worldwide or global synchronization and capacity allocation to support Synchronous data delivery such as SONET (SDH), Isochronous data delivery such as realtime data delivery, Asynchronous data delivery such as IP and other different QoS requirements for multimedia services. This is done based on the unified multi-access controllers of the frequency/phase/time multiple access schemes with fixed bursting switching frame size. Time, Phase and Frequency Division multi-access scheme for reconfigurable system are supported with flexible frame structure and slot definition and global signal synchronization for supporting current and future wireless and wireline information communication.
  • Synchronous data delivery such as SONET (SDH)
  • Isochronous data delivery such as realtime data delivery
  • Asynchronous data delivery such as IP and other different QoS
  • Com2000 tm Intelligent Technology delivers a revolutionary way of delivering a combination of multiple distinct Burst data Switching channels via the Time Division Multiplexing scheme and multi-data stream via the multi-channel Phase Controlled Signal Coding scheme simultaneously over the copper media. This is possible via the Com2000 t Intelligent Signal Coding and Precision Sampling Technology. We believe that the parallel channel and parallel data stream structure in such networks are a more flexible solution in terms of bandwidth on demand services, than increasing the bitrate of a single bitstream. This revolutionary Com2000 tm Intelligent Technology proposes and evaluates a network architecture that uses parallel channels and bit streams in a flexible way, and uses distributed switching to avoid the potential bottleneck of centralized switches.
  • TDM Time, Phase division multiplexing
  • FDM multi-data stream
  • Com2000 tm Intelligence delivers the capability of creating and removing new and dedicated data signal lanes in which can simultaneously transmit from any node to any node in point-to-point, point-to-multipoint, multidrop bus topologies. With this capability over existing copper infrastructure, higher speed lanes (commuted lanes) can be intelligently created and managed during the traffic jam time period of the day. This will also allow the Unified Packet/Circuit Switch data type and transmission for convergence of data communication and telecommunication can be seamlessly integrated.
  • Com2000 tm Intelligence delivers the capability of differentiating services between different traffic class or type (such as car/truck/semi) for each of the new data lane traffic.
  • SSI Com2000 tm Intelligence delivers the capability of differentiating between one's network receiving and sending nodes with respect to the other's receiving and sending nodes on shared switched medium data lane traffic (Overpasses with Distributed Switching Nodes).
  • the technology delivers a capability of simultaneously transmitting and receiving on the shared medium of any circuit node to any circuit node, in point-to-point, point-to-multipoint, multidrop bus topologies of local and other networking switching node of existing copper infrastructure.
  • the Com2000 tm Intelligence delivers an intelligent routing and switching, selection of the data freeway overpasses, exiting and admitting back into the freeway for real time delivery of the assembled and reassembled data for all of the data types, channels, circuits.
  • the overpass is also intelligently created and managed during the traffic jam time period of the day between local region and world wide Internet Freeway UTC traffics.
  • SSI Com2000 t Intelligence delivers Synchronous, Isochronous and Asynchronous data messages and services. It is used to seamlessly integrate to the existing SONET telecommunication systems, enhance the capacity of the channels, and synchronize all of the data types channels and circuits.
  • Com2000 tm Security set out securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data-corn backbone.
  • Com2000 tm Security is a collection of the state of the art algorithms that applies across the ISO layers for delivery of the encryption and decryption data message over a defined channel.
  • TCP/UDP/IP data messages the data is encrypted and transported with a higher level E-DNA (Electronic - Deterrence Network Address Access) protocols.
  • E-DNA Electronic - Deterrence Network Address Access
  • the average absolute and relative predictable time and the measured time for a message to travel over a predefined and calibrated channel is generally known to within a precise time window.
  • UTC absolute and relative Time Division Password Algorithm, Connection Awareness Algorithms of the present invention deliver the encryption and decryption to a standard delivery channel with an unsecured key source of the channel communications without the possibility of impacting the speed at the application level and at the highest data security level.
  • the message is encrypted and decrypted with a scrambled & unscrambled key of certain symbol at certain time.
  • the secured transport protocols and connection will be monitored and queried at certain period of time for Deterring Network Address (IP or TCP port ) Access (DNA).
  • the Electronic elements of the Com2000 tm Security (E-DNA) system are designed from the start to enable data and network security at the physical signal layer.
  • the technique greatly reduces the overhead associated with today's encryption and decryption schemes and is implemented to generate unique electronic signal signatures that proliferate through the entire data communication network.
  • the absolute and precision control of a universal time event via the Com2000 tm Clock Transfer technology is marching along between the communicating nodes. This precision and bias forward in time marking is used as the basis for a security seed. This seed will be used to generate a true and unbreakable random number generator during one's lifetime. There will be three markings for the 3 dimensional cubical seeds such as Time, Phase and Frequency matrix cell. This is the Carrier Signal Offset Algorithm.
  • the signal's signature is composed of both the waveform signal itself and the content of the waveforms.
  • the security system transmits the signature of the waveform by pre-positioning the signal at a specific frequency and phase matrix cell.
  • the signal signature of the waveform's content is provided via the pseudo-random noise (PN) signature for each node of the network.
  • PN pseudo-random noise
  • the PN auto correlation will be exercised for multi user ID access.
  • This PN signature provides network security by prohibiting any unauthorized intrusion by validating the signature, or E-DNA, of the sending node.
  • the Com2000 tm Security (E-DNA) technology at the physical layer such as the Carrier Signal Offset Algorithm for the signaling security systems, and in conjunction with standard MAC layer encryption and decryption algorithms, such as the UTC absolute and relative Time Division Password Algorithm, Connection Awareness Algorithm,
  • the Com2000 tm Security technology make transmissions over the Com2000TM system virtually impregnable from unwanted snooping and unauthorized access.
  • Com2000 tm Technology aims to develop the next generation Fast (Data & Transport) Circuit Switch for Information Communication System or Internet Networking Processor. It resides either at the edge and/or the core of the unified convergence network with a focus of integrated services such as multi-media data transmission over existing wireline and wireless infrastructure. This new architecture will seamlessly integrate to the legacy telecom & datacom backbone. This is done via an innovative and breakthrough software and hardware solutions and intellectual property based on SSI's Com2000 tm technology, as disclosed herein. The technology addresses the universal nature of Speed, Security and Intelligence limitations over existing data communication and telecommunication infrastructures. As described above, Com2000 tm Technology is applied on higher level of application layers which reside in the Web OS host.
  • the CyberIT Web host interface has been designed to provide a virtual Web IT Management and Controls of applications with the flexibility and intelligence of buffer management using conditional interrupts, allowing cacheable shared memories and support of fast connection establishment.
  • Figure 01 is an illustration of the Universal Intelligence Network "UniNet”.
  • Figure 02 is an illustration of the deployment example of the Private UniNet Network.
  • Figure 03 is an illustration of the interconnect of the Private UniNet Network.
  • Figure 04 is an illustration of a NEXT & FEXT Noise example of the UniNet Network.
  • Figure 05 is an illustration of the node access in Time Domain of UniNet Share Medium
  • Figure 06 is an illustration of a QoS example of the UniNet Network.
  • Figure 07 is an illustration of a Network Layers example of the UniNet Network.
  • Figure 08 is an illustration of a Parallel Cross Talks Noise example of the UniNet.
  • Figure 09 is an illustration of a UniNet Hierarchical Structure.
  • Figure 10 is an illustration of the Copper Gigabit Ethernet over 4 Pairs of UTP Cables.
  • Figure 1 la is an illustration of the Copper Gigabit 802.3ab Suggested design Overall margins.
  • Figure 1 lb is an illustration of the Copper Gigabit 802.3ab Suggested design FEXT noise margins.
  • Figure 12a is an illustration of the Copper Gigabit 802.3ab Insertion Loss of 100m CAT5
  • Figure 12b is an illustration of the Copper Gigabit 802.3ab Impulse Response of 100m CAT5.
  • Figure 13a is an illustration of the Copper Gigabit 802.3ab Return Loss ECHO of 100m CAT5.
  • Figure 13b is an illustration of the Copper Gigabit 802.3ab Worst Case ECHO Loss wrt
  • Figure 14 is an illustration of the Copper Gigabit 802.3ab Worst Case NEXT Loss wrt Signal.
  • Figure 15 is an illustration of the Copper Gigabit 802.3ab Worst Case FEXT Loss wrt Signal.
  • Figure 16 is an illustration of the Copper Gigabit 802.3ab System Modeling for Analysis.
  • FIG 17 is an illustration of the Copper Gigabit 802.3ab Received Desired Impulse
  • Figure 18 is an illustration of the Copper Gigabit 802.3ab Received ECHO Impulse Response.
  • Figure 19a is an illustration of the Copper Gigabit 802.3ab Received NEXT Impulse Response.
  • Figure 19b is an illustration of the Copper Gigabit 802.3ab Received FEXT Impulse Response.
  • Figure 20a is an illustration of the Copper Gigabit 802.3ab Receiver Cancellers prior to FFE.
  • Figure 20b is an illustration of the Copper Gigabit 802.3ab Receiver Cancellers after to FFE.
  • Figure 20c is an illustration of the new Gigabit 802.3ab cascaded FSLE/DFE receiver
  • Figure 21 is an illustration of the different Gigabit 802.3ab cascaded FFE/DFE SNR comparisons.
  • Figure 22 is an illustration of different Gigabit 802.3ab cascaded FSFE/DFE SNR comparisons.
  • Figure 23 is an illustration of the new cascaded FSFE/DFE and old FFE/DFE SNR comparisons.
  • Figure 24 is an illustration of the Current proposed Gigabit 802.3ab SNR receiver architecture.
  • Figure 25 is an illustration of the Margin offered by DPIC architecture scheme relative
  • Figure 26 is an illustration of the Improved performance DPIC architecture scheme relative
  • Figure 27 is an illustration of the Improved Performance DPIC architecture without NEXT.
  • Figure 28 is an illustration of the Margin offered by various architecture schemes relative
  • Figure 29 is an illustration of the current HDSL2 architecture schemes.
  • Figure 30 is an illustration of the Improved Performance DPIC architecture scheme relative HDSL2.
  • Figure 31 is an illustration of the Improved Performance DPIC architecture scheme
  • Figure 32 is an illustration of the Improved Performance DPIC architecture scheme relative
  • FIG. 33a is an illustration of the Society of Automobile Engineering Delong Network architecture.
  • Figure 33b is an illustration of the SAE Delong Network's Impulse Response.
  • Figure 34 is an illustration of the Delong Network for NG 1553 System Modeling for
  • Figure 35 is an illustration of the Current 1553 Transceiver Architecture & Data Coding
  • Figure 36 is an illustration of the DPIC-FSFE application on 1553 ISI cable for Precursor.
  • Figure 37 is an illustration of the DPIC-FSFE application on 1553 ISI cable for Pre &
  • Figure 38 is an illustration of the DPIC-FSFE application on 1553 ISI cable for Postcursor.
  • Figure 39a is an illustration of the Newly Proposed High Level Next Generation 1553
  • Figure 39b is an illustration of the Newly Proposed Med Level Next Generation 1553 Structure.
  • Figure 39c is an illustration of the Newly Proposed Detail Level Next Generation 1553
  • Figure 40 is an illustration of the Newly Designed UniNet Time, Frequency Multiplexing
  • Figure 41 is an illustration of the Newly Developed Synchronous PAM Signal Coding
  • Figure 42 is an illustration of the Newly UniNet Internet Communication Processor.
  • Figure 43 is an illustration of the Newly Clock Transfer and Measurement Scheme.
  • Figure 43a is an illustration of the Clock Transfer Subsection - Discipline Signal Generator.
  • Figure 43b is an illustration of the Clock Transfer Subsection - Osc Reference Clock
  • Figure 43c is an illustration of the Clock Transfer Subsection - Precision Ref Clock Generator.
  • Figure 43d is an illustration of the Clock Transfer Subsection - Measurement Source Selector.
  • Figure 43e is an illustration of the Clock Transfer Subsection - Correct Output Generator.
  • Figure 43f is an illustration of the Clock Transfer Subsection - Communication Ref Clock
  • Figure 44 is an illustration of the Newly UniNet Internet Clock Transfer Control Logics.
  • Figure 45 is an illustration of the Typical Least Mean Square Adaptive Equalizer Control
  • Figure 46 is an illustration of the Newly UniNet Internet Clock Transfer Transition Diagram.
  • Figure 47a is an illustration of the High Level UniNet Internet System Block Diagram.
  • Figure 47b is an illustration of the High Level UniNet Internet System Architecture Diagram.
  • Figure 48 is an illustration of the High Level UniNet Internet Clock Tuning Logics.
  • Figure 49 is an illustration of the High Level Intersymbol Interference Definitions.
  • Figure 50 is an illustration of the Conventional FFE and DFE Equalizer.
  • Figure 51a is an illustration of a phase dependent coverage of a FFE/DFE filter.
  • Figure 51b is an illustration of the Subsymbol Sampling Phase and SNR Correlation.
  • Figure 52a is an illustration of the Eye Opening Diagram of Biphase Manchester, MLT3,
  • Figure 52b is an illustration of the Signal Spectrum and Eye Opening Diagram of SPAM-5.
  • Figure 53 is an illustration of the A/D Samples and Canceller Taps Errors for ECHO & NEXT.
  • Figure 54 is an illustration of the Precision Angle Phase Control for Precision Signal Coding.
  • Figure 55 is an illustration of the Time, Frequency and Phase Multiple Access Coding Scheme.
  • Figure 56 is an illustration of the 2000 Mb/s Com2000 Gigabit System Block Diagram.
  • Figure 57 is an illustration of the Coherent Carrier Recovery PLL for Com2000 Receiver.
  • Figure 58 is an illustration of the General UniNet Frame Structure.
  • Figure 59 is an illustration of the UniNet Downstream and Upstream Frame Structure.
  • Figure 60 is an illustration of the UniNet Simplified Burst and Cell Structure.
  • Figure 61 is an illustration of the UniNet Time Relationship between various Frame Markers.
  • Figure 62 is an illustration of the UniNet Transmit Frame Gating Signal.
  • Figure 63 is an illustration of the UniNet Receive Frame Formatter.
  • Figure 64 is an illustration of the IP Packet Network Processing Functions.
  • Figure 65 is an illustration of the Distributed Packet Switching Architecture.
  • Figure 66 is an illustration of the UniNet Application over existing Ethernet IP Networks.
  • Figure 67a/b is an illustration of the UniNet Variable TCP Window and Size Controls.
  • Figure 67c is an illustration of the UniNet Variable IP Address Multiplexing and Controls.
  • Figure 67d is an illustration of the UniNet Variable TCP & IP Window Controls.
  • Figure 67e is an illustration of the UniNet Variable TCP & IP Access Window Controls.
  • Figure 67f is an illustration of the UniNet Variable Password Access Window Controls.
  • Figure 67g is an illustration of the UniNet CSOA Control algorithms.
  • Figure 67h/i is an illustration of the UniNet E-DNA DES Algorithms.
  • Figure 67j/k is an illustration of the UniNet E-DNA Key Encryption Control algorithms.
  • Figure 67L is an illustration of the RIPEMD-160 Hash Control algorithms.
  • Figure 68 is an illustration of the UniNet Communication Processor System Block Diagram.
  • Figure 69a is an illustration of the UniNet Baseband Converter and Sampler Block Diagram.
  • Figure 69b is an illustration of the UniNet Proposed Baseband Processor Block Diagram.
  • Figure 70 is an illustration of the Prototype System for Applications using POTS as the Communications Media.
  • Figure 71 is an illustration of the Block Diagram of the Prototype.
  • Figure 72 is an illustration of the Ethernet Interface and Buffer Management Function.
  • Figure 73 is an illustration of the DCA Block & Interface Diagram.
  • Figure 74 is an illustration of the DCA Assignment Process.
  • Figure 75 is an illustration of the Packetizer Block Diagram.
  • Figure 76 is an illustration of the Multi-Frame Format of the Communication Protocol.
  • Figure 77 is an illustration of the Standard Frame Format of the Communication Protocol.
  • Figure 78 is an illustration of the Burst Format of the Communication Protocol.
  • Figure 79 is an illustration of the TDMA Controller Interface Block Diagram.
  • Figure 80 is an illustration of the TDMA Rx Framer Block Diagram.
  • Figure 81 is an illustration of the Receive Framer Block Diagram.
  • Figure 82 is an illustration of the Receive Frame Synchronizer Flow Chart.
  • Figure 83 is an illustration of the Transmit Framer Block Diagram.
  • Figure 84 is an illustration of the Tx Framer Control Flow Chart.
  • Figure 85 is an illustration of the Burst-Mode Modem Block Diagram.
  • Figure 86 is an illustration of the Block Diagram of Burst-Mode Modulator.
  • Figure 87 is an illustration of the Block Diagram of the Equalizer.
  • Figure 88 is an illustration of the Block Diagram of Burst-Mode Demodulator.
  • Figure 89 is an illustration of the Synchronizer Block & Interface Diagram.
  • Figure 90 is an illustration of the Analog Front End Block Diagram of the System.
  • One aspect of the present invention is taking advantage of non-optimal way of current data communication, telecommunication, application communication and processing.
  • the Com2000 tm Internet Communication Processor can be thought as a most ideal platform for application processing, data communication & telecom communication and processing (Information Communication System or InfoCom).
  • the improvement can start at the media or channel(s) and then moving into higher level such as of ISO data communication and processing layers (Physical, Data, Network, Transport, Session, Presentation , Application ).
  • ISO data communication and processing layers Physical, Data, Network, Transport, Session, Presentation , Application .
  • the Com2000 Technologies set out to increase speeds over any communication channel, synchronizing, enabling, improving, controlling and securing all of the data transmission with Web OS related application's processing over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data com backbone, as illustrated in Figure 07.
  • Com2000TM At the Physical Layer (Channel & Equalization), Com2000TM technologies, represents the collection of state-of-the-art characterization and optimization schemes which is not only improving the current data communication over any channel, but also enables a new information communication architecture which enable multitudes of new technologies.
  • ISO layers At the Physical Layer (Channel & Equalization), Com2000TM technologies, represents the collection of state-of-the-art characterization and optimization schemes which is not only improving the current data communication over any channel, but also enables a new information communication architecture which enable multitudes of new technologies.
  • the non-characterized signal parameters of a relatively slow in time invariant Gaussian communication channel (from one node to another communication node) of any wireline communication allows a new optimum way of recovering the signal parameters as to consider the combination of the trellis encoder (FEC -Forward Error Correction) and the channel as on large finite-state machine.
  • the combination of advance and adaptive precoder equalization, Trellis Coding Modulation and Channel Shaping schemes allows us to take advantage of non- characterized channel samples during Symbol Detection, Error Correction and filtering processing of the front-end receiver.
  • This new scheme results in increased Signal to Noise Ratio or SNR and is called "DCA" or Decision Channel Adaptation (Channel Adaptive Equalization). This is described below.
  • a difference between a wireline channel and a wireless channel "DCA" is that in the wireless channel, the channel is estimated for every sending frame or burst while the channel impulse response measurement for wireline channel is refreshed periodically.
  • the non-synchronized and un-optimized signal processing of a receiving distorted signal and noise also allows the present invention to take advantage of non-optimized noisy A/D samples and Symbol samples detection, filtering processing of the front-end receiver.
  • This scheme results in further increased Signal to Noise Ratio or SNR and is called "DPIC" or Decision Precursor Intersymbol Interference Canceller, as illustrated in Figure 08.
  • the synchronized transmitted signals over multiple media or communication channels exhibits a cyclostationary noise and cross-talk characterization that allows new advance and adaptive equalization scheme to further enhanced the SNR.
  • This new advance and adaptive equalization which take advantage of pseudo-synchronized receiving signals (vector) over multiple media or channels simultaneously, is called " FS-DPIC" or Fractional Space Linear Equalization with DPIC. It is described in section 1.0. The section also described the vector equalization processing for removing multi-path of the wireless channel.
  • the non-synchronized phase plane controls the baseband signal processing of a receiving distorted signal and noise also allows new advance multi-channel signal coding scheme to take advantage of non-optimized and non-synchronized phase offset controls Symbol samples detection processing of the front-end receiver. This scheme results in further increased data bits per hertz or Bps/Hz.
  • This new advance signal coding scheme which takes advantage of synchronized controls of Phase Signal Space of receiving signals (vector) over multiple media or channels simultaneously and is called "MSC" or Multi-Channel Signal Coding and is described below.
  • Com2000 tm Intelligent (Modem) - Multi-Channel Signal Coding technology allows higher data rates to be delivered in a unique way from a single continuous or burst streams carrier frequency.
  • the technology delivers multi-channel (phase division) network architecture that uses parallel bitstream in a novel way. It uses the non-complex or complex base band symmetry signal with phase division multiplex coding scheme or PDM to deliver the multi-channel requirements, as illustrated in Figure 03.
  • the phase domain's multi -channel wireline and wireless network utilize the optimal phase division multiplexing (PDM) for multi-channel wireline and wireless network.
  • PDM phase division multiplexing
  • the Com2000 tm Intelligent (Modem) - Precision Sampling technology enables to the precision sampling of the signal's parameters or combination of the Time (Multi-Time Slot sampling), Phase (Multi-Channel Phase sampling) and Frequency (Multi-Carrier sampling) signal spaces.
  • the non-synchronized in time, frequency and phase signal plane controls of the baseband signal processing for the receiving distorted signal and noise also allows new advance multi-channel signal sampling scheme which takes advantage of non-optimized and non-synchronized time, frequency, phase offset controls Symbol samples detection and vector processing over multiple media or channels and is called "PSAM" or Precision Sampling, which is described below , as illustrated in Figure 03.
  • the Com2000 Multi-Channel DPIC capitalize on the synchronous nature of the vector wireless or wireline receiver.
  • each stream of data for each channel in turn is considered to be the desired signal, and the remainder are considered as interferers.
  • the Com2000 Multi-Channel DPIC take advantage of the non-linear alternative approach which is to exploit the signal parameters synchronization inherent in the new synchronous transmit and receiver Com2000 systems.
  • the synchronous signal parameters are carrier, carrier phase, symbol timing, sampling phase synchronous vectors, as illustrated in Figure 03 and Figure 08.
  • the symbol cancellation as well as linear nulling to perform the detection.
  • interference from already-detected components of the symbol vector is subtracted out from the received signal vector, resulting in a modified received vector in which, effectively, fewer interferers are present.
  • This technique can be applied any other or to all of the synchronization signal parameters such as Carrier Synchronization, Carrier Phase Synchronization, Sampling Phase Synchronization and others for the simultaneous transmitting signal space in Frequency (FDM,CDMA)), Phase(CDMA), Time(TDMA) and receiving vector signal processing.
  • Com2000TM technologies At the Data Layer (Framer & Media Access), Com2000TM technologies, as illustrated in Figure 07, represents a collection of state-of-the-art characterization and optimization schemes which not only improves the current data communication over any protocols, but also to enables a new information communication structure that enables a multitude of new QoS and controls technologies.
  • the reconfigurable DSP structures of the design to increase speeds and to deliver real-time, robust and deterministic multiple-access, and intelligence transport protocols, which can be used of mapping of legacy protocols. It reflects the concept of reconfigurable and remote-computing internet networking processor applied to future communications so-called software radio/wireless/wireline or web transceiver/internet processor.
  • the non-synchronized application & data distribution and processing of the current packet and circuit switching data processing also allows new advance multi-channel and multi-purpose QoS or Quality Service distribution scheme which take advantage of non-optimized and non- synchronized quality service controls, detection and processing over multiple media or channels and is called "QoS-XFER" or QoS Transfers, as illustrated in the figure 09.
  • Circuit-switched for existing telecommunication architecture and packet-switched networks for data communications have very different characteristics. They can both support an integrated service environment, but have different merits in terms of providing various service aspects.
  • Co ⁇ OOO* 1 Speed, Security and Intelligence Technology
  • This new "Columbus” architecture stems from Com2000 tm technology, is a highly integrated networks, which are set out to address and resolve the following networking issues: • 1.
  • Com2000 tm Intelligence technology addresses and resolves the real-time guarantees issues, e.g., bounded end-to-end delay and bounded delay variations (jitter);
  • Com2000 tm Intelligence technology addresses and resolves the Multicast issues, i.e., sending data from one sender to many receivers; • 3. Com2000 t Speed technology addresses and resolves the High capacity over any media and any topology;
  • Com2000 t Speed & Intelligence technology addresses and resolves the Bandwidth on demand service, i.e., providing a multi-rate service
  • Com2000 tm Intelligence technology addresses and resolves the Transaction support, for example support for bursts of messages with short access delay;
  • Com2000 t Intelligence technology addresses and resolves the capability of a network interface which should depend on the level of service assigned to a service access point, not the capacity of the total network;.
  • Com2000 tm Intelligence technology addresses and resolves the Distributed Intelligence and data switching/routing processing that seamless integrated into the Fiber Optic Backbone; • 9. Com2000 tm Security technology addresses and resolves the Privacy & Security issues of data communication;
  • the subsection 1 describes the Universal Speed Technology for the Higher Speed in wireline and wireless.
  • the subsection 2 describes the Universal Wireline Intelligence Technology for any type of services, any type of media and any channel topology adaptations.
  • the subsection 3 describes the Universal Security Technology for any data type of services, any type of media and any channel topology adaptations.
  • the subsection 4 describes the Universal Wireless Intelligence
  • the subsection 5 describes the Universal Network Processor and Communication System from the System Architecture point of view.
  • the subsection 6 describes the Universal Operating System or Environment for Network Processor and Communication System's application from the System Architecture point of view.
  • the last subsection 7 describes the summary of the current and next generation Com2000 tm technology.
  • Com2000TM Noise Suppression Technology is applicable to all wireline such as xDSL, Copper Gigabit and Cable Modem Standards, as illustrated in figure 01.
  • any type of wireline communication channel there is distortion that can cause errors in data signaling thereby reducing effective throughput.
  • the signal's characteristics often changes as the signal propagates along the channel.
  • the imperfections in the communication channel tend to reduce the resolution of the data bandwidth of the signal being transmitted across the channel.
  • the data may not be interpreted correctly at the receiving end of the channel if the transmitted signal's characteristics are outside of a defined signal's parameter range.
  • Section II we describe the channel characteristics and modeling.
  • Section III we present the different receiver structures suitable to the transmission of Gigabit Ethernet over 4 cat-5 UTP cables.
  • Section IV we present the analytical model for the cascaded FSLE/DFE receiver structure using interference suppression approach and its performance analysis.
  • each UTP support a 250Mb/s full-duplex channel using a 5-level 125Mbaud transmission scheme.
  • the transmission on pair#l With respect to the Receiver #1L on the left, its wanted signal is sent by the Transmitter #1R on the right.
  • the transmitter #1L on the left sends a signal to the Receiver #1R on the right, but also generates spurious signal (called echo) to its own Receiver#lL on the left.
  • the interference signals generated by Transmitters 2L-4L on the left appear at the input of the Receiver #1L are called near-end crosstalk (NEXT) interferers, NEXT_21 to NEXT_41.
  • the interference signals generated by Transmitters 2R-4R on the right appear at the input of the Receiver #1L are called far-end crosstalk (FEXT) interferers, FEXT_21 to FEXT_41.
  • NEXT near-end crosstalk
  • FEXT far-end crosstalk
  • the transfer function H(d, f) of a perfectly terminated loop with length d can be written as follows
  • ⁇ (f) is the propagation constant
  • a (f) is the attenuation constant
  • ⁇ (f) is the phase constant.
  • the propagation loss (or insertion loss) limit Lp (f) for category 5 (cat-5) 100m cable is a positive quantity expressed in dB
  • the Echo loss is indicated by the return loss.
  • Figure 13 shows the plot of the measured return loss and the return loss limit which is 15dB for frequency from 1 to 20MHz and 15- 101og(f720) for frequency from 20 to 100MHz.
  • the wavy curves in Fig. 4 give the measured pair-to-pair NEXT loss characteristics for three different combinations of twisted pairs in 100m cat-5 cables.
  • the existence of the minima (small loss) and maxima (large loss) in these curves is due to the fact that the frequencies considered here correspond to wavelengths that are in the same length range as the distance between points of unbalance in the NEXT coupling path. Notice that the minima and maxima usually occur at different frequencies for the three pair combinations.
  • the worst-case TIA EIA-568-A NEXT loss model shown in Figure 14 is 27.1-16.81og(f7100) in dB.
  • Figure 16 shows the channel model including the effects of partial response, DAC and hybrid filtering in the transmitter, the main and coupling channel characteristics, and the filtering in the receiver front-end.
  • the DAC and hybrid filtering is represented by the cascade of two identical first-order Butterworth sections with a comer frequency of 180MHz. This introduces a 4ns rise/fall time.
  • the receiver front-end is modelled as a fifth-order Butterworth filter with a corner frequency of 80MHz.
  • the main channel, echo coupling and NEXT coupling channels are represented by C( ⁇ ), E( ⁇ ), N 2 ( ⁇ ), N 3 ( ⁇ ), and N 4 ( ⁇ ), respectively.
  • the models for the FEXT's are similar to those of the NEXT's except the coupling channels will be F 2 ( ⁇ ), F 3 ( ⁇ ), and F 4 ( ⁇ ), instead of N 2 ( ⁇ ), N 3 ( ⁇ ), and N 4 ( ⁇ ).
  • the pulse responses of the main, echo, NEXT's and FEXT's at the input of the RECEIVER shown in Figure 16 are shown in Figures 17, 18, and 19, respectively.
  • the non-synchronized and un-optimized signal processing of a received distorted signal and noise also allows a new advance and adaptive equalization scheme to take advantage of non- optimized noisy A D samples and Symbol samples detection, filtering processing of the front- end receiver.
  • This scheme results in further increased Signal to Noise Ratio or SNR and is called "DPIC” or Decision Precursor Intersymbol Interference Canceller.
  • SNR Signal to Noise Ratio
  • DPIC Decision Precursor Intersymbol Interference Canceller.
  • the frequency synchronized transmitted signals over multiple media or communication channels exhibits a cyclostationary noise and cross-talk characterization which allows new advance and adaptive equalization scheme to further enhance the SNR.
  • This new advance and adaptive equalization which takes advantage of frequency, phase pseudo-synchronized receiving signals (vector) over multiple media or channels simultaneously, is called " FS-DPIC" or Fractional Space
  • Linear Equalization with DPIC The section also describes the vector equalization processing for removing multi-path of the wireless channel. Achieving the increased throughput requires the line signal channel to be as noise free as possible. This is accomplished through two methods:
  • FS-DPIC Symbol or Channel Vector DPIC Processing
  • FSFFE fractionally spaced feed forward equalizer
  • DFE decision feedback equalizer
  • DPIC decision precursor ISI canceller
  • the method delivers the optimally suppression the residual of cyclostationary interference and ISI errors between the multi-channel A D Samples and multi-channel Symbol Recovery Samples.
  • the method which utilizes the receiving channel's carrier phase and delay synchronization feature to control the correlation of the crosstalks and noise in a multi-channel or vector environment.
  • the correlated cross talks and noises between multi-channel behaved as in a cyclic pattern or in a cyclo-stationary fashion. This pattern is further utilized to in minimize the Vector Precursor ISI errors in a close loop fashion. It is done so that the error between the multi-channel residuals of pre ISI correlation noise, which are induced by the
  • Feed Forward filter's coefficient taps from its digital sampling A/D clocking and the multi-channel post ISI correlation noise induced by the Decision Feed Back filter's coefficient taps from its digital sampling A/D clocking are suppressed .
  • the multi-channel precision synchronization is done from utilizing the channel's characterization and error calibration of channels.
  • the method such as the Phase Residual Detector Error Vector Measurement or EVM, are used to determine the external ISI coupling and non-linearity of the signal zero-crossings for each of the channel. This is done so that the multi-channel DPIC can be optimized of the ECHO/NEXT/FFE/DFE filters quantization jitter or noise for each perspective channel.
  • Com2000TM Single or Multiple Channel DPIC Equalization Technology is comprised of a set of multiple conventional FFE/DFE filters and delays with a unique combination of multi-stage filtering and Sheer. Every component of the DPIC filter is the conventional. However, the combination of filter taps and delays for each of the multi-stage FFE/DFE, sheer, along with the A/D Samples input and logic paths are defined the algorithm for DPIC .
  • the Com2000TM Single or Multiple Channel DPIC Equalization Technology provides a revolutionary approach involving adaptive filters and algorithms that model the estimated signal and channel responses to optimize signal recovery for improving the signal to noise ratio (SNR) of the Com2000TM system.
  • SNR signal to noise ratio
  • This increased SNR margins allow many applications such as cost reduction of the current standard design or delivery a ultra high-speed data modulation methods that increase the channel capacity and data for every Hz bandwidth of signal frequency.
  • FIG. 20a and b Structures shown in Figures 20a and b are based on interference cancellation.
  • a NEXT canceller synthesizes, in an adaptive fashion, a replica of the NEXT interferer. The interferer is then cancelled out by subtracting the output of the canceller from the signal appearing at the receiver.
  • a NEXT canceller has the same principle of operation as an echo canceller, and all the familiar structures used for echo cancellers can also be used for NEXT cancellers.
  • the cancellers needs to have access to the local transmitters from which they get their input signals. Typically, this input signal is the stream of symbols generated by the transmitter's encoder. In Fig. 10a the output signal of the canceller is subtracted from the received signal immediately after the A D.
  • the canceller has to generate outputs at the same rate as the sampling rate of the A/D.
  • An alternative is to make the subtraction at the input of the slicer as shown in Fig. b. In this case, the outputs of the canceller need only be generated at the symbol rate.
  • the FFE (feed-forward equalizer) in Figures 20a and b can be a symbol-spaced (SS) or fractionally spaced (FS) FFE or an analog equalizer. It is used to equalize the precursor ISI.
  • the DFE is used to remove the post cursor ISI. Note that the performance of the DFE is also dependent on the reliability of the symbols detected by the slicer and influenced by the error propagation. For this, one may replace the simple slicer by a sequence detector (such as Viterbi decoder) for a better performance. In that case, the long processing delay of the decoder can be an issue.
  • Interference equalization is only feasible if the transceiver uses a large excess bandwidth. Specifically, it can be shown that, with one cyclostationary interferer, these conditions can only be satisfied if the transmitter uses an excess bandwidth of at least 100%. Heuristically, the need for such a large excess bandwidth can be explained as follows. With 0% excess bandwidth, an adaptive equalizer has just enough degrees of freedom to perfectly equalize one signal, but cannot do anything else. In order to equalize two signals, the number of degrees of freedom available to the equalizer has to be doubled with respect to what is required for one signal. This is achieved by doubling the bandwidth of the transmitted signal, which results in an excess bandwidth of 100%.
  • Figure 16 shows the overall system that is used to study the performance of the receiver structure using a FSLE cascaded with a DFE (shown in Figure 20c) in the presence of interference (echo and NEXT's), ISI, and additive white noise (AWN).
  • the AWN has power spectral density of N o /2.
  • the waveform received by the receiver is:
  • ⁇ the first term of r(t) is the desired signal (i.e., sequence to be detected), while the second term represent N interferers, and n(t) is the AWN at the input of the FFE.
  • ⁇ O ⁇ i ⁇ T is the 1th interferer's delay.
  • ⁇ 0 (t) is the overall end-to-end pulse response (e.g., Figure 17)
  • ⁇ (t) is the pair-to-pair pulse response of the 1th interferer (e.g., Figures U 19).
  • ⁇ a is the transmitted symbol
  • ⁇ is the sampling phase representing time shift in a symbol period
  • w m ' s and f m 's are the tap settings of the FFE and DFE, respectively
  • p is the delay in the receiver's decision relative to the receiver's input.
  • the FFE and DFE coefficients are optimized to minimize the mean squared error (MSE), where the error is:
  • interference and includes interference, ISI, and AWN.
  • R n T [r(nT- ⁇ )r(nT-D- ⁇ )---r(nT-N w D- ⁇ )]
  • A E [X n X n T ]
  • V E[X n a n - p ].
  • V 1 - V T U 0 pt (7)
  • V and A are obtained by taking expectations, using (4):
  • a ⁇ E(R n R n T )
  • A2 E(R n a T n .,_ p )
  • I is the identity matrix
  • R(t) is the autocorrelation function of the power spectral density of AWN at the output of the receiver filter. Note that for stationary interference with power spectrum equal to that of the cyclostationary interference, the results are the same except the q(i, j) term becomes:
  • SNR 10 * log ⁇ o (1 /MSE) where the mean squared error (MSE) expression is shown by Equation (7) above.
  • MSE mean squared error
  • ⁇ NT is the span of the FFE in terms of the number of symbol intervals, and D is the delay element used in the FFE.
  • the number of taps of the FFE is given by the product of (NT)(T/D);
  • ⁇ NF is the number of DFE taps. 0
  • D symbol-spaced FFE
  • the proposed structure of the receiver prior to the 4D-TCM Viterbi decoder consists of 4 paths and each path includes:
  • SCHEME PL ONE 50-TAP ECHO CANCELLER, THREE 12-TAP NEXT CANCELLERS, SYMBOL - SPACED 12-TAP FFE, AND 10 -TAP DFE ( and ADC with effective 48 levels).
  • SCHEME PH ONE 121- TAP ECHO CANCELLER, THREE 72 -TAP NEXT CANCELLERS, SYMBOL- SPACED 6-TAP FFE, AND 12 -TAP DFE ( and ADC with effective 96 levels). Note that study was done with the assumption that the FEXT's are neglected. The margin was expected to be adequate for FEXT's.
  • Scheme PL has a much lower complexity than Scheme PH (a total saving of 71 echo canceller taps, 180 NEXT taps, 4 FFE taps and 2 DFE taps per path).
  • Figure 25 shows the plots of the margin including 6dB coding gain when FEXT's are present. It indicates that Scheme PL is not acceptable due to the insufficient margin (i.e., shown as negative margin) while the margin of Scheme PH varies between 1.5dB to 4.5dB dependent on the sampling phase. This can be marginal in practice.
  • FIG 26 shows the position of the newly introduced Decision Precursor ISI Canceller (DPIC).
  • the DPIC makes use of the D detected symbols from the output of the SUcer to estimate the precursor ISI which still exists at the input sample of the Sheer.
  • the estimation of the residual ISI value is done by a D-tap Finite Impulse Filter (FIR).
  • FIR Finite Impulse Filter
  • This D-tap FIR has the same structure as the DFE or the Echo or NEXT canceller except the values of the coefficients. Since it calculates, A D-symbol delay element is used to keep the DT-delayed sample, from which the corresponding residual precursor ISI computed by the D-tap FIR is removed.
  • the DPIC has a simple structure with D-symbol delay (or a memory of D locations) and a D-tap FIR. The value of D is small.
  • D D-symbol delay (or a memory of D locations)
  • D-tap FIR D-tap FIR
  • SCHEME IL ONE 50 -TAP ECHO CANCELLER, THREE 12-TAP NEXT CANCELLERS, SYMBOL- SPACED 12-TAP FFE, 10- TAP DFE( and ADC with effective 48 levels) and ONE 10 - TAP DECISION PRECURSOR ISI CANCELLER, (i.e., SCHEME PL with DPIC)
  • SCHEME IH ONE 121- TAP ECHO CANCELLER, THREE 72 -TAP NEXT CANCELLERS, SYMBOL- SPACED 16-TAP FFE, 12-TAP DFE ( and ADC with effective 96 levels), and ONE 12- TAP DECISION PRECURSOR ISI CANCELLER, (i.e., SCHEME PH with DPIC)
  • Schemes IL and IH are actually the improved versions of Schemes PL one 10-tap DPIC and PH with one 12-tap DPIC, respectively.
  • Figure 25 shows the performance of Schemes IL and IH as compared to Schemes PL and PH. We observe from Figure 25 the following:
  • the new Scheme IL provides a margin of 4dB while the currently proposed Scheme PH has a worse performance than new Scheme IL except for the timing phases of 10T/16 to 15T/16 where Scheme PH is better by at most 0.5dB. Note that the complexity of currently proposed Scheme PH is much higher than that new Scheme IL as shown in Table 1 (3 times).
  • the new Scheme IH provides a large margin of 8dB (including 6dB from the 4D- TCM Viterbi Decoder) or a performance improvement of 4dB over the currently proposed design. This implies that without 4D-TCM and complex Viterbi Decoder, the new Scheme IH still provide 2dB margin.
  • the 4D-TCM and complex Viterbi Decoder can be dropped for cost and simplicity, or • the new DPIC technique can be used in conjunction with 4D-TCM and complex Viterbi Decoder for high performance and longer distance, or higher capacity.
  • DPIC can be used with FFE (Fractionally Spaced or Symbol Spaced) plus DFE plus Echo Canceller to obtain an excellent performance without NEXT Cancellers as 10 shown in Figure 27 below.
  • FFE Fractionally Spaced or Symbol Spaced
  • ILE(T), IHE(T) and IHE(T/2) using the structure shown in Figure 27.
  • ILE(T) and IHE(T) use a Symbol-Spaced FFE while IHE(T/2) use a Fractionally Spaced T/2-FFE.
  • the numbers of taps and complexity of these schemes for the Gigabit receiver are summarized in Table 2 below
  • Figure 28 indicates the best performance with a margin (including Viterbi decoder) of 8dB offered by our introduced schemes IH and IHE(T/2). From Table 2, Scheme IHE(T/2) only needs 145 "symbol” taps and 32 "sample” taps. The number of
  • Scheme IHE(T/2) needs a 32-tap T/2- spaced FFE operating at twice the symbol rate. Compared to IHE(T/2), the performance of IHE(T) is about ldB worse. However, Scheme IHE(T) uses a 16-tap Symbol-Spaced FFE operating at the symbol rate as the currently proposed PH.
  • This application disclosed some of the potential applications of the DPIC to xDSL (Digital Subscribed Loop) to enhance the transmission performance without affecting the proposed coding standards.
  • the HDSL and SHDSL (or HDSL2) are used in the following discussions.
  • HDSL is an extension of DSL based on the same 2B1Q baseband line coding to provide 2-pair repeaterless Tl El symmetric service.
  • the transmission throughput improvement of HDSL over DSL is due to shorter CSA (Carrier Serving Area) operation range instead of that defined by all non-loaded loops.
  • CSA Carrier Serving Area
  • the critical issues were that the required performance would include a BER of 1E-7 and that the margin used in theoretical and simulation studies would be 12dB, while the margin on a measured piece of equipment need only be 6dB.
  • the crosstalk model has a NEXT loss of about 57dB at 80kHz and decreases at about 15dB per decade for frequencies above about 20kHz.
  • Figure 29 shows the currently proposed transceiver structure for SHDSL.
  • the symbol timing recovery is not shown in this figure.
  • the receiver includes a 20-tap fractionally spaced (T/2) equalizer, an 128-tap DFE and an 165-tap symbol-spaced echo canceller.
  • FIG. 30 shows the proposed transceiver structure using DPIC.
  • Schemes IHE(T) or IHE(T/2) are applicable to xDSL to improve the performance of the current xDSL.
  • the Scheme IHE(T/2) use a Fractionally Spaced FFE to suppress the NEXT's and FEXT's as NEXT and FEXT cancellation is not possible in the environment of xDSL.
  • FSFFE fractionally spaced feed forward equalizer
  • DFE decision feedback equalizer
  • DPIC decision precursor ISI canceller
  • Enhanced-performance Rx made of a conventional Rx described above plus an enhanced- performance equalizer.
  • the SNR is calculated at the input of the slicer (decision device). We considered three following environmental situations (disturbers):
  • DSL 24 ADSL+24 HDSL
  • Enhanced-performance Rx made of a conventional Rx described above plus an enhanced-performance equalizer.
  • the SNR is calculated at the input of the slicer (decision device). We considered three following environmental situations (disturbers): o Self: 24 Self o TI : 24 Self+24 Tl o DSL: 24 ADSL+24 HDSL Results: We obtained the following analytical results for the SNR (dB):
  • CENTER TAP defined as the tap with the largest coefficient
  • the AS 1553 standard formerly and commonly referred to as MIL-STD-1553, was introduced in the early 1970's to define a digital communications bus for the interconnection of different subsystems that were required to share or exchange information in a multi-drop configuration. Since its introduction, the AS 1553 standard has been evolving to incorporate functional and user community enhancements. However, the basic communications and architectural characteristics of the bus have not varied from its original release. Message-based communications over the multi-drop bus make use of the Manchester II bi-phase coding for IMb/s transmission in a half-duplex mode over Twisted-Shielded Pair (TSP) with 90% shield coverage. The largest message is 32 word long where a word has 20 bits.
  • TTP Twisted-Shielded Pair
  • Transmission performance is specified for a word error rate (WER) of 10 "7 or better for an equivalent worst- case Additive White Noise (AWG) of 140mVrms in a bandwidth from 1kHz to 4MHz, and a signal level of 2. lVpp.
  • WER word error rate
  • ASG Additive White Noise
  • AS-1A Subcommittee
  • DoD United States Department of Defense
  • the DoD request was driven by present and projected future needs for retrofitting existing weapon system platforms with subsystems that would demand more data transfer bandwidth.
  • the main research objective is to find a solution to support robust, deterministic, and reliable transmission at higher data transfer rates over the existing physical cable plants.
  • the primary goal of the transfer rate is 100 Mb/s.
  • the desirable aim is the interoperability with existing AS 1553 terminals and transformer assemblies.
  • High speed data transmission of digital data over C-17 cables requires adaptive equalization to equalize channel distortion and adaptive interference cancellation to remove both echo and crosstalk interference (NEXT's and FEXT's).
  • Channel distortion includes mainly amplitude distortion and delay dispersion. It causes the smearing and elongation of the duration of each symbol.
  • ISI inter-symbol interference
  • Equalization system in concert with a synchronous communication environment alleviates the relative phase dispersion of the interfered and interfering signals that greatly reduces ISI. This is a critical factor affecting the C-17 or Mil-Std 1553 receiver performance.
  • Interference echo and crosstalks
  • the sources of interference and noise for a system need to be analyzed in order to provide methods of removing interference and increasing the Signal to Noise Ratio (SNR).
  • SNR Signal to Noise Ratio
  • the problem is that there may be insufficient margin in SNR for the receiver to operate reliably (at the required threshold BER) on an existing C-17 or Mil-Std 1553 cable plant.
  • the current 1553 Receiver Design and analysis found that there is only a small SNR margin ( OdB) at IMb/s for C-17 or Mil-Std 1553 Cable Specifications.
  • One aspect of the present invention is the means and method of High Speed Data Transmission over existing Mil-STD-1553 wireline communications, called Next Generation 1553 utilizing the Advance Com2000TM Signal Equalization of Decision Precursor ISI Canceller (DPIC), and Advance Com2000TM Signal Coding Quadrature Amplitude Modulation (QAM- 16) with the emphasis of backward compatible with existing Mil-STD- 1553 standard (As illustrated in figure 39a,39b,39c).
  • DPIC Advance Com2000TM Signal Equalization of Decision Precursor ISI Canceller
  • QAM- 16 Advance Com2000TM Signal Coding Quadrature Amplitude Modulation
  • the above discussions indicate that it is desired to find advanced signaling techniques for high-speed data transmissions over the multi-drop bus using the existing MIL-C-17 Cable.
  • the Next Generation 1553 coding scheme for the enhanced 1553 Standard to support new terminals with data rate up to lOOMb/s using enhanced coupler.
  • the Next Generation 1553 also provides the interoperability with existing low-speed AS 1553 terminals at rate IMb/s using the existing AS 1553 transformer assemblies.
  • the cable channel has a severe frequency-selective attenuation at frequencies beyond 1MHz, which limits the transmission at higher rate.
  • the transmission using Manchester coding is limited by the bandwidth of 1MHz in which the attenuation is relatively flat.
  • the present inventions' equalization techniques and advanced combined coding and modulation schemes transmission at lOOMb/s or above is possible.
  • the baseband bandwidth up to 30MHz.
  • the insertion loss variation is about 2dB, i.e., the frequency- selective attenuation has a depth of 2dB.
  • Our DPIC equalization technique will be used to remove the inter-symbol interference and crosstalk due to such frequency-selective attenuation.
  • adaptive equalization will be applied to adapt to a particular bus in use.
  • Multi-level modulation such as Quadrature Amplitude Modulation (QAM- 16) will increase the bandwidth efficiency required to support transmission of 1 OOMb/s over a bandlimited channel of up to 30MHz. However, it will require higher signal level to maintain the WER of 10 "7 for the specified noise floor.
  • QAM- 16 Quadrature Amplitude Modulation
  • a specified noise floor of 140mVrms in a frequency range from 1kHz to 4MHz is equivalent to 383mVrms in a frequency range from 1kHz to 30MHz.
  • the use of multi-level modulation scheme for high bandwidth efficiency alone will require a much larger signal level to maintain the same WER of 10 "7 , especially when the bandwidth is also increased.
  • Next Generation 1553 signaling scheme for 1 OOMb/s speed does not require new coupler.
  • Next Generation 1553 signaling scheme for 300+Mb/s requires a new coupler for higher data throughput, additional stub wiring would also need to be added to power the couplers.
  • the current legacy passive coupler supports the new transceiver chip operations.
  • an active coupler which is provided power by the new Next Generation 1553 node via a new stub wire, are required.
  • ⁇ (f) is the propagation constant
  • (f) is the attenuation constant
  • ⁇ (f) is the phase constant.
  • the propagation loss (or insertion loss) limit Lp (f) for C-17 100m cable is a positive quantity expressed in dB
  • Figure 34 shows the channel model including the effects of partial response, DAC and hybrid filtering in the transmitter, the main and coupling channel characteristics, and the filtering in the receiver front-end.
  • the DAC and hybrid filtering is represented by the cascade of two identical first-order Butterworth sections with a comer frequency of 180M ⁇ z. This introduces a 4ns rise/fall time.
  • the receiver front-end is modeled as a fifth-order Butterworth filter with a comer frequency of 80MHz.
  • the main channel, echo coupling and NEXT coupling channels are represented by C( ⁇ ), E( ⁇ ), N 2 ( ⁇ ) respectively.
  • the models for the FEXT's are similar to those of the NEXT's except the coupling channels will be F 2 ( ⁇ ) instead ofN 2 ( ⁇ ).
  • Figure 35 shows the currently proposed transceiver structure for 1553 .
  • the symbol timing recovery is shown in this figure.
  • the current 1553 receiver is a standard Bi-Phase Manchester Signaling Receiver.
  • the new proposed 1553+ transceiver as illustrated in figure 39a, 39b, 39c with the simulation results as illustrated in figure 36,37,38, includes a 20-tap fractionally spaced (T/2) equalizer, an 128-tap DFE and an 165-tap symbol-spaced echo canceller.
  • T/2 20-tap fractionally spaced
  • the performance margin is very tight and a rate 3 A 512-state Trellis Code is used in order to provide 6dB of coding gain required for a proper operation. It is therefore desired to enhance the transceiver performance so that a larger margin can be provided. Additional margin can be used to increase the range (distance) or Tx rate.
  • Figure 39c shows the proposed transceiver structure using DPIC.
  • the critical issues were that the required performance would include a BER of 1E-7 and that the margin used in theoretical and simulation studies would be 12dB, while the margin on a measured piece of equipment need only be 6dB.
  • the crosstalk model has a NEXT loss of about 57dB at 80kHz and decreases at about 15dB per decade for frequencies above about 20kHz.
  • Com2000 tm Advanced Multi-Channel Equalization Technology delivers the advanced parallel transmitter and receiver's adaptive filters and algorithms that model cyclostationary signals in a varying cross-talk noise channel model with the response to optimize parallel signal recovery.
  • Our Advanced Equalization system delivers the noise suppression and cancellation schemes used to improve the Signal-to-Noise ratio (SNR) of the multi-channel system.
  • SNR Signal-to-Noise ratio
  • Multi-path propagation is one of the most challenging problems encountered in a wireless data communication link. It cause signal fading, inter-symbol interference (ISI) due to channel delay spread and doppler spread due to the relative motion between receiver and transmitter. For high speed wireless communication (more than 10 Mb/s) , signal fading and ISI due to the channel delay spread , are the main factors that significantly degraded the average bit error rate (BER) performance.
  • ISI inter-symbol interference
  • BER bit error rate
  • An Adaptive Decision Feedback Equalizer (DFE) and DPIC can be optimized, on a symbol- by-symbol basis, using the channel-estimation based adaptation (CEBA) or Direct Adaptation (DA) algorithms.
  • CEBA channel-estimation based adaptation
  • DA Direct Adaptation
  • the CEBA algorithm the channel pulse response (CPR) is estimated, and the DFE filter coefficients are then computed from the CPR estimates.
  • the DFE filter coefficients are directly computed from the received signal samples using the least square algorithm without going through channel estimations.
  • a sequence of training symbols is used for initializing the DFE and DPIC filter coefficients.
  • the filtered received signal must first be sampled at the proper sampling instants.
  • FIR finite impulse response filter
  • the decision delay must be pre-determined (This is done by Multi-Channel DPIC and Delay circuits). The optimization of the sampling instants and DFE decision delay is refereed to as the "Precision Sampling”. In the determination of Precision Sampling approach, the "Sampling Delay” and the “Sampling Phase” are need to be determined.
  • the “Sampling Delay” is obtained using the Propagation delay measurements (CPR) and time-correlation between the sequence of the received signal samples and the transmitted training sequence.
  • the “Sampling Phase” is obtained from the Clock Transfer using the Error Vector Measurement or EVM methods.
  • the sampling instant or “Precision Sampling” is the sum of the "Sampling Delay” and the “Sampling Phase”. It is important to optimize both of the Precision Sampling and the Decision Delays. Optimizing the "Sampling delay” alone improves the robustness of the DFE with respect to the channel delay-spread variations. Optimizing both of the "Sampling Delay” and the “Sampling Phase” provides additional performance gain for the symbol-spaced DFE's.
  • the frequency offset between the transmitter and receiver oscillators is assumed to be negligible.
  • the Doppler spread is significant for out door wireless systems.
  • the Com2000TM Advanced Clock Transfers are used to combat against Doppler spreading.
  • the Doppler spread is insignificant for indoors wireless environments.
  • the Com2000TM Precision Sampling System comprises a method for precisely positioning the phase sampling and measurement windows at the center of the Eye Diagram with minimal error.
  • This system relies on the complete frequency and phase synchronization of one or more network nodes, preferably accomplished using the Clock Transfer system.
  • the clock synchronization can be either relative or absolute and is used as one improvement to deliver a multitude of benefits, such as bandwidth and SNR improvements, ISI suppression and more data bits per frame. This technique is also possible due to the Channel Jitter Suppression and Measurement Technologies.
  • the Com2000TM Coherent Clock Phase and Carrier Recovery Circuits allows the Precision Sampling Technology to sample the receiving signal with a predefined phase error for a extend period of time. This is due to the fact that the crystal frequency drift and phase noise and jitter are less than the jitter caused by the VCO oscillator of the PLL circuits. This feature, therefore, also allows the increasing of the message size or number of data bits per packet load to be sent across a wireless communication channel such as TDMA packet. Through the Com2000TM Coherent Clock Phase and Carrier Recovery Circuits, the recovered carrier frequency remain a clean locked for more than 5x of the normal PLL lock.
  • the Precision Sampling technology is responsible to produce carrier, carrier phase, symbol timing, sampling phase synchronous vector processing receiver and other derived clock signals.
  • the Com2000 Diversity Decision Feed Back technology for Multi-Channel DPIC capitalize on the synchronous nature of the vector receiver.
  • each stream of data for each channel in turn is considered to be the desired signal, and the remainders are considered as interferers.
  • the Com2000 Diversity Decision Feed Back technology for Multi-Channel DPIC take advantage of the non-linear alternative approach which is to exploit the signal parameters synchronization inherent in the synchronous transmit and receiver systems.
  • the synchronous signal parameters are carrier, carrier phase, symbol timing, sampling phase synchronous vectors. As an example, using only the symbol timing synchronization, the symbol cancellation as well as linear nulling to perform the detection (This is better than the Antenna Nulling alone).
  • LMS Least Mean Square Error
  • a wireless and wireline Com2000 tm Multi-channel UniNet system can be described as follows.
  • a single data stream is demultiplexed into M substreams or M multi-channels.
  • Each substreams or channel which behave as a point-2-point connection and has its own precoder equalizer coefficients, is then encoded into symbols and fed to its respective transmitter.
  • Each of the channel transmitter and receiver are synchronously detected in any or combination of the following signal parameters detection processes, but not limited to : Symbol absolute carrier and symbol Phase Sampling and Timing, Symbol relative carrier and symbol Phase Sampling and Timing (Relative to the Reference Channel or substreams), Symbol Carrier Phase and Frequency Offsets (Relative to Reference Channel Carrier Phase and Frequency Offsets, etc...
  • Each of the transmitter operate co-channel at either fractional or symbol rate 1/T symbols/sec with synchronized symbol timing, phase, frequency and others.
  • Each transmitter is itself an ordinary QAM transmitter.
  • the baseband symmetry is maintained for wireline by a selecting the same baud rate and the carrier frequency.
  • the baseband symmetry is maintained via the multi-channel complex DPIC and synchronous receivers.
  • the collection of transmitters comprises, in effect, a vector-valued transmitter, where components of each transmitted vector are symbols drawn from the PAM/QAM constellation.
  • Each of the substreams or channel has the flexibility of having different constellation, and those transmissions are organized into bursts of symbols (as illustrated in Figure 05).
  • Com2000 tm Multi-channel UniNet is essentially a single-user system which uses multiple transmitters for each channel, one can naturally ask in what way the Com2000 tm Multi-channel UniNet data modem deliver the differentiations from a simply using traditionally multiple access techniques in a single user fashion. Some of these difference are :
  • the total channel bandwidth utilized in the Com2000 tm Multichannel UniNet is only a small fraction in excess of symbol rate, i.e. similar to the excess bandwidth required by the conventional QAM system.
  • FDMA Frequency Division Multiplex
  • TDMA Time Division Multiplex Access
  • Com2000 tm Multi-channel UniNet uses the entire system bandwidth and which is used simultaneously by all of the transmitters all of the time, as illustrated in figure 40.
  • Com2000 tm Intelligence (Modem) - Data Flow Transfer Technology utilizes a combination of the frequency division, phase division and time division duplex techniques in signal coding and latency controls to provide new and integrated solutions for next generation universal synchronous networking communications.
  • This scheme supports legacy modulations and also as an integrated platform for 2-dimensional CDMA (Phase), TDMA
  • the Com2000 t Intelligent (Multi-Channel Signal Coding) technology allow to deliver higher data rates in a unique way from a single carrier PAM-M baseband signal frequency.
  • the technology delivers multi-channel (phase division) network architecture that uses parallel bitstream in a novel way. It uses the non-complex or complex baseband symmetry signal with phase division multiplex coding scheme or PDM to deliver the multi-channel requirements which also meets the selected media FCC constraints, illustrated in figure 41 and figure 42 for 2G/bs PAM5 signaling Copper Gigabit 802.3ab Example.
  • the signal coding and decoding is orchestrated in a "Relative" Phase Synchronization manner.
  • the receivers recover the clock and phase from the received signal and use it for the sample timing to recover the data.
  • Our enhanced technique is not only to delivering the "Relative" Synchronization scheme, but it also delivers the "Absolute” Synchronization technique to enable multitude of novel ways to increase bandwidth and intelligence controls that can extend and interoperable with to the WAN networks.
  • the ordinary and single carrier frequency channel can be interpreted in a vector of channels, which can be characterized through precision phase channel measurement and calibration. Every other channel in a multi-channel media will be a non-interference channel with respect to the other channel and the selected M-PAM or M- QAM signal coding can be used to transmit over channels as in the current scheme.
  • a new Com2000 tm data delivery architecture for wireline and wireless is the shared or non-shared medium access with multi-channel networks with the stringent support of synchronous and controlled environment such as SONET.
  • the Com2000 tm Intelligent (Precision Clock Transfer) technology is used to proliferate the synchronous nature throughout the UniNet communication networks.
  • the precision clock transfer and control technology relates to stringent applications such as ITU global and local synchronization level service of SONET and telecom synchronization, as illustrated in figure 02.
  • the phase domain's multi-channel wireline and wireless network utilize the optimal phase division multiplexing (PDM) for multi-channel wireline and wireless network.
  • PDM phase division multiplexing
  • the Com2000 tm Intelligent (Precision Sampling) technology enables to the precision sample of the signal in any combination of the Time (Multi-Time Slot sampling), Phase (Multi-Channel Phase sampling) and Frequency (Multi-Carrier sampling) signal spaces, as indicated in the figure 05.
  • Com2000 tm Intelligence - QoS Transfers technology again utilizes a synchronous and controlled environment via a precision clock transfer and controls resident at the edge and the core of the network, to deliver universal and next generation synchronous, isochronous and asynchronous integrated data services or a novel Synchronous and Distributed Switching and - Routing method in local LAN network or WAN networks, as shown in figure 01.
  • This precision controlled synchronous clock transfer technology is not only enables the physical layer to communicate in increased speeds with a high capacity over a intelligence controlled signaling of multi-channel and shared medium access, but also to provide a basis for true quality of service, or Hard QoS that can be extended into the current telecom backbone, as shown in figure 02.
  • These protocols include ATM, SONET, Frame Relay, and Tl/El,etc,. from the telecom services and IP networking protocols for Internet such as TCP/UDP from data communications.
  • this universal transport protocol mapping covers across the QoS spectrum from a very stringent circuit like requirement to a very unreliable data deliver such as current packet switching method.
  • the QoS service is also applicable to very stringent synchronous services such as SONET, loosely isochronous services such as ATM and Frame Relay, etc, and best effort asynchronous data services such as Internet IP protocols.
  • Com2000 tm Intelligence technology is a highly integrated networks, which are set out to address and resolve the following networking issues:
  • Com2000 t Intelligence technology address and resolve the real-time guarantees, e.g., bounded end-to-end delay and bounded delay variations (jitter); • 2. Com2000 tm Intelligence technology address and resolve the Multicast, i.e., sending data from one sender to many receivers;
  • Com2000 tm Intelligence technology address and resolve the Transaction support, for example support for bursts of messages with short access delay; • 6. Com2000 tm Intelligence technology address and resolve different types of traffic with different demands. Traffic in our future network will be both isochronous/asynchronous and distributive/commutative and the services associated with each will be different;
  • Com2000 tm Intelligence technology address and resolve the capability of a network interface which should depend on the level of service assigned to a service access point, not the capacity of the total network;.
  • the below description focuses on to the modem or physical layer portion of the network.
  • the present invention focuses on how to enhance or to improve the current TDMA, FDM and CDMA multiple access schemes and/or the combination thereof, to deliver a precision control TDM signaling or SONET Quality of Services like data delivery infrastmcture for wireless and wireline private networks, as illustrated in figure 02.
  • This section describes the Com2000 tm enabling technology for Convergence of Data Communication and Telecommunication systems, that allows the IP networks to have the predictable latency control and characteristics of the SONET networks (IP over SONET TDM Like as shown in Figure 02).
  • the Com2000 tm technology incorporates lessons learned in studying data communications bandwidth control and efficiency requirements.
  • Over the Internet data communication channels such as nodes on Small Office or Home Office (SOHO) Networks and Central Offices Switches, there is unpredicted nature in packet-based voice and video data delivery mechanisms that cause errors that reduce the effective use of the real-time applications such as voice and multimedia data messages.
  • SOHO Small Office or Home Office
  • the new network has to be synchronous and can be synchronized to the standard frequency structure as the SONET backbone for extending the precision control to the edge of the network.
  • the precision controlled communication environment is enabled through a
  • Com2000 tm Clock Transfer system This system provides synchronous and precision absolute relative to the world standard or relative time, phase and frequency transfer at the physical signaling layer from one network node to another which proliferates throughout the entire network, as shown in figure 02.
  • the network then in turns, providing a Synchronous Communication Environment that enables a multitude of other enabling technologies, such as increased bandwidth with the capability of capacity dynamic allocation and control solutions for either point to point or point to multi-point network topologies.
  • the Com2000 tm Clock Transfer system are primarily in the area of enabling synchronization infrastructure of SONET-like over UniNet delivery system, improving network throughput and QoS of existing data communication channels with its real time data messages and its challenges of Internet, Intranet and Extranet infrastmcture equipment, long haul WAN network and Telecommunications synchronization, as illustrated in figure 02.
  • the Com2000 tm Clock Transfer system provides the baseline precision requirements for manipulating and controlling signal delays throughout the networks, video and voice synchronization, security, Information Technology Controls, and specific signal characteristics enabling increased data throughput and more efficient bandwidth utilization.
  • the technology provides absolute and relative time reference to the world frequency and time standards that allows synchronous PC platforms to exploit the remote WAN or LAN computing breakthrough capability via clock transfer of the synchronized clocks throughout the network by enabling synchronous Operating System and any Signal Communication schemes, as illustrated in figure 01.
  • the combination of the product 's integrated stratum one frequency reference can be used as a means to suppress the long -term drift and short term jitter. This allows Internet and long distance WAN communication data synchronization problem goes away, as part of the UniNet solution.
  • This precisely controlled communication environment is enabled through Com2000 tm Advanced Signal Coding and Control Technology for any media topologies.
  • This new controlled network environment provides the baseline precision required for manipulating and controlling specific signal characteristics such as multi-carrier (FDM), multi-phase (PDM) and multi-time (TDM) signal coding which are enabling factor of increasing data throughput and more efficient bandwidth utilization.
  • FDM multi-carrier
  • PDM multi-phase
  • TDM multi-time
  • Com2000 tm Channel Measurement , Calibration and Control Technology measures and calibrates the communication channel to determine the highest possible data capacity for a particular medium, and allocate appropriately and intelligently for the nodes on the network.
  • the communications channel must be first characterized so that errors and imperfections, such as frequency and phase distortions, can be identified.
  • Com2000 t s calibration system uses these measurements to improve communication channel resolution by controlling the errors and imperfections of the channel. This system provides scaleable bandwidth transmissions or rate adaptively for each of the node, while allowing the best possible data throughput across the transmission medium, as illustrated in figure 05.
  • Com2000 tm Advanced Signal Coding and Control Technology provides a revolutionary approach for FDM, PDM baseband line signal coding method that increases effective data throughput by increasing the number of symbols per hertz of data transmitted.
  • data rates as an example for Copper Gigabit Ethernet data transmission, can be increased up to 2 Gigabits per second over the existing CAT5, provided there is enough margins on SNR.
  • Com2000 tm 's new Frequency, Phase or Time synchronous signal coding then utilizes uses the multi-phase baseband Synchronous PAM-5 (or SPAM-5, as shown in figure 41) signaling and coding, with appropriate data scrambler to satisfy the FCC power emission requirements (as suggested in the IEEE 802.3ab standard).
  • Com2000 tm Precision Sampling Technology implements the ultra-precise control of specific signal characteristic offset in order to deliver precise signal confrol for multichannel signal detection and tracking condition as shown in figure 05 and figure 41 (SPAM- 5).
  • the Com2000 tm System provides multi-level, multi-dimensional scalability.
  • the Precision phase and amplitude Sampling system ensures that every clock carrier and phase offset signal in each multi-channel system is synchronously transmitted and sampled at the receiver within a predicted synchronous phase interval.
  • the System also provides a precise method of measuring the power of the received signal, as illustrated in figure 03.
  • the precision controlled of the synchronous communication environment is enabled through a UniNetTM Clock Transfer system.
  • This system provides synchronous time, phase and frequency transfer from one network node to another that proliferates throughout the entire network.
  • the network is then in turns providing a Synchronous Communication Environment that enables precision controls and multitude of other enabling technologies to deliver an increased bandwidth and quality of service solutions.
  • the Clock Transfer system provides the baseline precision required for manipulating and controlling specific signal parameter characterization and measurements.
  • the environment is also enabling an large increased data throughput, as later discussed and illustrated in figure 10 for cyclostationary crosstalk-noise controlled environment in a parallel and multi-channels vector processing systems.
  • the synchronous environment also provide more efficient bandwidth determination and dynamic allocation with QoS utilization metering capability for pay per use of bandwidth.
  • the UniNetTM Clock Transfer Technology's synchronous nature further enables the reduction in both self-generated noise and Inter-symbol Interference (ISI).
  • the Com2000TM Clock Transfer Technology provide SNR increase via more optimized method of error detection and reduction between the raw signal samples and the derived symbol sample time. This allows a better and cleaner FFE/DFE Filter coefficient convergence and determinations. For channel measurement and calibration, it is also removing channel distortion, via a completely controlled capability of the transmit and receiving channel signal parameters measurement and characterization. These include time, frequency, phase and power control of the level of radiated EMI emissions through the determination of propagation.
  • the precision synchronization controls enabled by the Clock Transfer Technology also provide mechanisms for the unique Com2000TM security feature, as described later in section 3.0, of a personalized electronic signature for each system node ID (Electronic Deterrence of Network Address (E- DNA)).
  • HDTV high-quality sound and video over the network
  • jitter delay variations
  • the telecommunication existing Circuit-switched networks have many attractive properties for providing real-time guarantees. Since all of the operating nodes of the telecom backbone and telecom edges such as Tl/El nodes or other xDSL nodes are transferred as TDM and all synchronized to the SONET stratum clocks in someway.
  • QoS Quality of Service
  • the UniNetTM network starts out with the stringent requirement of the circuit switching hard QoS.
  • the Circuit Switching resource allocation method needs to be examined.
  • the Circuit Resource is reserved at a constant bit-rate from sender to receiver and therefore, is a deterministic way of transport and multiplexing of data.
  • Infra-stream or virtual circuit synchronization is needed for an isochronous stream, such as an audio stream, to regain the pace at which the data was created.
  • Inter-stream synchronization is also performed between two different data streams to make them synchronized at the transmitter and receiver of the circuit. For example between an audio stream and a video sfream for providing lip synchronization, the inter-data stream needs to be synchronized where the streams are carried over the networks by 2 separated TDM telecom data circuits, as shown in Figure 01 when two remote user of UniNetTM networks interface with each other via a realtime data such as video conferencing via the existing TDM telecom infrastructure.
  • the present invention hereinafter refened to as the Com2000TM Synchronous system, provides a system and method of the environment that can be used to measures the channel, precodes a predefined signal training burst sequence for signal characterization over a communication channel by using, enabling and delivering the precision control of the signal's frequency and phase synchronization, and by adjusting the receiving signal parameters with a predetermine value to eliminate distortions arising from the increased data throughput of channel provided by the new signal. Additionally, the new signal is both scaleable and secure using coding systems that take advantage of the precision synchronous nature and controls.
  • the present invention integrates the subsystems that provide this functionality and may be manifested at either the physical layer interface for improving the communication capacity and controls or at the medium access layer interface for improving the channel allocation, QoS controls, Security and other usages.
  • the channel for all communication system types are including, but not limiting to, Ethernet signaling, cable and xDSL modems, POTS, Satellite and wireless networks.
  • the Com2000 tm Clock Transfer system provides the baseline precision requirements for manipulating and controlling signal delays throughout the networks, video and voice synchronization, security, Information Technology Controls, and specific signal characteristics enabling increased data throughput and more efficient bandwidth utilization.
  • the technology provides absolute and relative time reference that allows synchronous PC platforms to exploit the remote computing breakthrough capability via clock transfer of the synchronized clocks throughout the network via using Synchronous Operating System and Signal Communication schemes, as illustrated in Figure 02.
  • the combination of the product 's integrated stratum one frequency reference can be used as a means to suppress the long -term drift and short term jitter. This allows Intemet and long distance WAN communication data synchronization problem to be resolved at the edge synchronization of the network.
  • the Precision Synchronization Environment is enabled via the combination of the following clock transferring methods :
  • the Clock Transfer System block diagram is responsible for recovering, regenerating and distributing the different clock frequencies and phases required of the PMD and PMA layers of the nodes from the networking master reference node (RN) to the slave plain nodes (PN) in the networks. Burst to burst synchronization between transferring node is also done via the synchronization of the equalization training sequence as shown in figure 45.
  • the physical layer composed of Physical Medium Access Layer or PMA and Physical Medium Dependent Layer (PMD).
  • PMA Physical Medium Access Layer
  • PMD Physical Medium Dependent Layer
  • the synchronizer is done in a separate block from the equalization block. It is aiding from the equalizer (FFE& DFE & DPIC) via interfacing to the equalization block for sampling, symbol timing and carrier clock recovery and synchronization and other controls & purposes as well.
  • the equalizer training sequence is converted into the synchronization sequence that is currently using standard pseudo random or PN sequence now.
  • This periodic synchronization sequence is used to acquire and track the carrier and carrier phase and phase delay of the channel and as the basis for synchronization tuning.
  • the sequence also be converted into new security PN sequence for security and privacy purpose and other special controls as required.
  • the master tone can be used to supplement the synchronization as needed based on the controls during the start up or channel calibration process.
  • the Timing Synchronization and the Equalization algorithm can be thought as of one tracking channel (Equalization Algorithm) and on Acquisition Channel (Synchronization Algorithm). These two algorithm fundamentally are the same as far as filter coefficient convergence concerns. However, the filter coefficients for the synchronization algorithm equalizers are used to determine the channel phase delay of the channel and offsets.
  • the DPIC Equalization as illustrated in figure 30, which behave as the DFE algorithm, is currently as more effective than the standard equalization algorithms. Once the receiver synchronization algorithm in place, the symbol vector can be processed in parallel and the noise are not correlated. The FFE algorithm can then be sampled in T/2 or as fractional space equalizers to take advantage of the cyclostationary cross talk and noise characteristics.
  • the DPIC equalization and the Synchronization equalization algorithm are currently done independently from each other. As we show you in the Gigabit figure 26 and figure 10, the standard algorithm has a lot of deficiencies in handling the ISI and Crosstalks.
  • Our DPIC filter for each single channel equalization scheme can be added to improve the SNR margin up to 8dB relative from 3dB 802.3ab suggested design.
  • the standard 802.3ab implementation is loosely operating in the master and slave frequency synchronization mode. We don't need precision synchronization in this case. However, should we have the precision synchronization, the coupling between DFE and viterbi 's decoder algorithms will further benefits results from the symbol vector processing. Should we want to removed all of NEXT Cancellers, we need to the precision synchronization control for all channels.
  • the Clock Transfer Algorithm are exercised for delivery synchronous network nodes throughout the systems.
  • the functional aspect of the Clock Transfer Technology for step 2 or the calibration and tuning method operates within the Com2000TM State Transition Diagram (STD).
  • STD Com2000TM State Transition Diagram
  • the states, or operating modes, are setup in such a way that the Com2000TM Clock Transfer System can set the desired starting mode through a Confrol Mode command that forces the VHDL logic to go directly to the selected mode.
  • the VHDL logic increments through each of the modes in sequence.
  • Mode 2 its local oscillator to the selected traceable reference source
  • Mode 3 For Master Node (RN), its traceable reference can be 100Hz from external source or from the standard frequency source such as GPS.
  • the communication channel signal protocols are then initialized (Mode 3) to the common heartbeat of the reference, or disciplined frequency and phase, so that the communication channel biases can be determined (Mode 4).
  • the system is now ready for external phase and frequency transfers (Mode 5) that can be initiated through an automatic sense signal on the communication channel's data signal (Mode 6).
  • the received data signal is tracked and decoded (Mode 7) for Station Identification verification and node awareness, and to determine whether the received station identification is synchronized to the traceable reference. If it is not synchronized, the station's Phase and Frequency Transfer process is initiated (Mode 8). The system first determines its phase and frequency offsets relative to the received signal data of the station ID (Mode 8). Once the offsets are determined, the values can be sent back to the requested station ID and used for tuning its local oscillator accordingly (Mode 9). The process continues until the Station ID local reference is within the designated tolerances (Mode 9). The Station ID then does the final full duplex ranging estimates of the offsets (Mode 10) for fine-tuning of the synchronization phase and frequency offsets.
  • the Station ID is declared as a Disciplined Station ID and the process will suspend for a predetermined period before the commencing fine tuning process again (Mode 11).
  • the training process continues until all newly identified station ID's internal oscillators are disciplined. Within a few seconds, this training and calibration process brings the network system into an initial disciplined state that is continuously fine-tuned during normal system communication.
  • the Clock Transfer Technology operates within the Com2000TM State Transition Diagram (STD). Let us describe in detail the VHDL logic interaction for each system mode of the STD. Even though that this technique can be applied for both wireline and wireless applications, for the sake of clarity of the descriptions, we describe the method on the wireline (POTs) UniNet LAN application.
  • POTs wireline
  • Mode 1 - Power Up Within this state the system conducts a proper power up sequence where blind equalization and self-tests are performed to validate the integrity and readiness of the system.
  • the Clock Transfer logic has the option to select from other reference sources if the current LAN communication channel signals are not available.
  • the Com2000TM system has the capability to synchronize its local reference to the phase and frequency of any communication reference source.
  • the system can therefore be used to determine the phase and frequency offsets of its local reference (RN) source relative to any communication node (PN) through the tracking of the communication channel, as illustrated in figure 05.
  • the system can determine the phase and frequency offsets (matrix cell of frequency versus Phase) of one particular communication channel node (RN to PN1) relative to another similar communication channel node (RN-PN2) or an entirely different communication channel node.
  • the input reference standard source is used as a reference source (through RN PLL circuitry) for disciplining the internal RN oscillator and then is used as the standard and disciplined reference source to propagate the absolute phase and frequency across the UniNet LAN communication nodes.
  • the Reference Clocks & Measurements Subsystem includes the Disciplined Signal Generator (11), Oscillator Reference Clock Generator (12), Precision Reference Clock Generator (13), Measurement Source Selector (14), Measurement Reference Clock Generator (141), Corrected Output Generator (15) and The Precision Sampling Logic (16).
  • the Precision Sampling Logic (16) controls all aspects of the Precision measurement and timing tracking functions for frequency, symbol, sample phase and timing for each node of the UniNet LAN network. This includes RN signal clock tracking and management of the Precision signal processing, Phase Estimator Control of the measurements for timing solutions, phase/frequency transfer, security signature processing and PLL controls.
  • the frequency reference (194) for the Precision Reference Clock Generator (13), as illustrated in figure 43 and figure 43b, is selectable (122) from either an internal Tunable Crystal Oscillator (123) or an external reference input (125).
  • the selected Precision reference (194) drives a phase lock loop of the Precision Reference Clock Generator (13) at the Precision Sampling Logic signal input reference rate or Precision reference (194).
  • the Precision reference clock (191) is distributed to the Precision Sampling Circuit logic and the DDS Signal Synthesizer (111) for generating the Precision corrected 125 MHz output (19G).
  • the Precision Sampling Logic performs all of the Phase and Frequency offset comparison functions, signal phase and frequency related processing and tracking of individual frequency and phase errors.
  • the Conected Output Generator (15), as illustrated in figure 43e, produces 2.5, 25, 125, 250 and 500 MHz outputs (159B, 159C) and a 1 and 100 Pulse Per Second (PPS) signal (159A).
  • the corrected output signals are all synchronized to the Precision reference tracking clock (19J).
  • the Precision reference tracking clock is traceable to the World Standard Reference.
  • the Precision Reference Tracking Clock (19J) and the output frequencies (159A, 159B, 159C) are all within 10 parts per trillion.
  • the 100 PPS (19K, 159D and 159 A) is maintained within 4 ns RMS of the Precision Reference Tracking Clock (19J).
  • the DDS Signal Synthesizer (111), as illustrated in figure 43a, is used to generate the 125 MHz Precision corrected reference signal (19G).
  • the output frequency is controlled by the input control value (114) from the Clock Tuning Logic (161) of the sampling circuitry (16).
  • the N bit control value (114) allows the output digital frequency (116) to be controlled to better than 10 parts per trillion.
  • the control value is derived by the Phase Estimator Control solution of the VHDL logic (161). This value is continually updated to maintain accuracy.
  • the DDS Signal Synthesizer (111) flywheels using the last valid control number (1 14).
  • the output digital frequency (116) will then drift according to the aging rate of the oscillator (123), ⁇ 50 PPM drift per day.
  • the output digital frequency of the DDS Signal Synthesizer (116) is a digital sine wave that is converted to analog using a fast Digital-to-Analog (DAC) converter (112).
  • the resulting analog signal (117) is filtered using a narrow bandpass filter (113) to remove the unwanted noise and harmonics.
  • the output Precision corrected 125 MHz is buffered for isolation (19F).
  • the 2.5 and 25 MHz frequency outputs (159B, 159C), as illustrated in figure 43e, are generated from (153,154) the 125 MHz Precision corrected signal (19G). The two frequencies are then filtered to remove spurs and to convert the signals to a sine wave (155,156).
  • the frequency dividers (153,154) are synchronized to the 100 PPS (159D) to insure consistent phase relationships between the output frequencies (159B, 159C) and the 100 PPS signal (159D).
  • the outputs are buffered (157) to achieve an isolation between frequency outputs (159B, 159C) of greater than lOOdB.
  • the 100 PPS signal (159D) is generated from the 125 MHz clock.
  • the counter (152) is initially jam set (159) to properly set the phase, and thereafter maintained through corrections to the DDS Signal Synthesizer (111). Verification of the 100 PPS phase is accomplished by sampling both the 100 PPS (152) and the DDS phase (115). Calibration and alignment of these two registers is performed at power up to achieve a resolution of 125 ps.
  • the method of generating the 100 PPS signal (159A) is critical as it allows all generated clocks such as 500, 125 MHz (19F), 2.5 MHz (159B) and the 25 MHz (159C) to maintain phase coherence with each other.
  • Non-coherent designs can jump the phase of the 100 PPS signal (159A) with respect to the Precision corrected clock outputs (19F, 159B, andl59C) and upset the phase measurement and calibration circuitry.
  • the Precision corrected 100 PPS signal (159D), as illustrated in figure 43e, is derived from the 125 MHz oscillator (123 & 111), the Pulse-to-Pulse jitter is kept to less than 1 ns RMS. Corrections of the 100 PPS (159D) over phase are created by slowly tuning the 125 MHz oscillator (123,111) so that for changes in Precision reacquisition, or other operating conditions, the corrected signals maintain extremely stable outputs. Phase jumps and output discontinuities are therefore eliminated.
  • the Measurement Source Selector (14), as illustrated in figure 43d, allows an external 100 PPS input (149C), or an external 100 PPS derived from the external frequency (19A), to be measured using the Precision corrected reference (19G).
  • the 100 PPS is measured to a resolution of 1 ns and the frequency is measured to a long-term resolution of 10 parts per trillion.
  • a 500 MHz clock (147) can be generated for future applications, as illustrated in figure 43 d.
  • the 500 MHz clock (147) is Precision corrected because it is phase locked, as shown in the Measurement Reference Clock Generator (141), to the Precision corrected 125 MHz signal (19G).
  • Synchronization Circuit (144) for the latch (143) resynchronizes the asynchronous signal input (149C) to the 500 MHz clock (147) while latching (143) the phase of the 500 MHz clock (149A). This allows a measurement resolution of 1 ns to be obtained.
  • the corrected Precision PLL 500 MHz signal (147) is down counted (142) in a series of decade counters to 100 Hz (149A).
  • the 100 Hz and the Precision corrected 100 PPS (149B) are in phase with each other but with some fixed but unknown offset.
  • a one-phase measurement is made by latching (143) the phase of the counter (142) at the Precision corrected 100 PPS signal selection (149B).
  • the received external 100 PPS (149C) is then selected from the multiplexor (mux)(145) and the phase of the counter (142) is again latched (143).
  • the difference is the offset of the Precision conected 100 PPS (149B) relative to the input 100 Hz signal (149C).
  • the measurement continues at a 0.1 second update rate.
  • the external input is divided down (19A) to a 100 Hz signal.
  • the 100 Hz is used by the mux (145) and the Sync (144) to latch (143) the phase of the 500 MHz down counter (142).
  • the one-shot Sync (144) measurement's accuracy of 5 parts per billion is initially obtained.
  • the resolution improves when integrated over time. At 500 seconds, during normal data communication operation, the measurement resolution reaches the specified 10 part per trillion. All counter measurements are averaged for 500 seconds to insure full resolution at each subsequent measurement (100 Hz).
  • the local frequency (19F) is disciplined to the selected reference, as illustrated in figure 43, it is used to generate the corresponding timing and clock signals for the UniNet LAN signal mod and demod such as Synchronous Partial Response PAM or QAM 16 Modulator and Demodulator and the LAN Communication Channel (37).
  • the UniNet LAN signal mod and demod such as Synchronous Partial Response PAM or QAM 16 Modulator and Demodulator and the LAN Communication Channel (37).
  • the Network Com2000TM Transceiver (31), or the LAN Front End Interface shown in figure 47a, 47b, is comprised of a Physical Layer RN Tone, Digital UniNet Transceiver Section and a Receiver Timing Recovery Section.
  • the network system Upon completion of the initialization and training phase, the network system enters the normal data processing phase that maintains the disciplined
  • Transmit Symbol Encoder accepts 8-bit data from the MAC interface such as Mil or GMII and converts it into Quinary encoded symbols for PAM-5 signal modulation transmission.
  • the signal levels of the differential driver (314) conform to the specifications in the lOOOBase-T IEEE proposed standard.
  • the Com2000TM Channel Equalization and Filter Subsystem (312) performs the auto- co ⁇ elation function for the received unique Multiple Access PN (Pseudo Random Noise) sequence of the FFE/DFE equalizer predefined training sequenced data.
  • the clock recovered from the received training sequence of the filter is used to aid in the phase lock loop of the Clock Recovery Controller Logic block (311), and is captured and used to steer the local clock.
  • the RN Transmitter clock reference is the conected and disciplined 500 MHz clock (19F) and is used as the reference source for the Channel Equalization and Filter (312).
  • This clock is derived from the selection of either an internal clock source (123), the received data clock from The Clock Recovery Controller Logic block (311) or an external disciplined clock (121).
  • the derived clock is used as the RN transmitting frequency reference (312). This provides enormous flexibility for the data throughput and synchronization whether utilizing packet-based or cell-based data packages or an external or internal clock source for the transmission frequency reference.
  • the clock transfer is able to deliver frequency and phase synchronization based on the transmit and receive symbol clock pulses (19A).
  • the RN transmitter's clock pulse (37) is the same as the PN receiver's clock pulse (171) (within a minimal phase and frequency offset) with the phase time stamps for the encoders and decoders of each node in the network are within a 1 ns phase delta
  • the Com2000TM system is able to use the network clock synchronization to improve bandwidth and QoS controls throughput over the UniNet LAN network communications channels.
  • the RN transmitting symbol frequency reference of 125 Mbaud (37) is derived from the Com2000TM absolute oscillator clock (19A) (World traceable frequency).
  • This clock pulse (19A), or heartbeat is used for the carrier phase signal of the modulated PAM5 or our Partial Response PAM-5 Coding data sfream (315,313).
  • the receiver further enhances the SNR by improving the vector processing of filter and equalizer operations, virtually eliminating frequency and phase lock loss and improving the complex signal modulation and data demodulation schemes.
  • the improvements, when selecting the reference signal ( 19A) are mostly generated in the lOOOBase-T Function Block .
  • This Block performs legacy CSMA CD functions such as function link integrity test, link failure indication and link reverse polarity conection, SQE test generation at the end of each transmitted packet, and collision detection for simultaneous transmit and receive packets.
  • legacy CSMA CD functions such as function link integrity test, link failure indication and link reverse polarity conection, SQE test generation at the end of each transmitted packet, and collision detection for simultaneous transmit and receive packets.
  • the effective throughput of the 125 Mbaud network would be reduced in capacity due to the signal ISI noise, data retries due to lost data bits and phase lock loss.
  • the Com2000TM System implementation during heavy network loads, the system operates at near maximum capacity. This is due to the elimination and suppression of the relative phase offset between ISI sources, as indicated in figure 49 and DPIC figure 26. It also used to optimize the cunent FFE and DFE equalizers, detection circuitry, and the elimination of the management overhead that a typical unsynchronized parallel vector processing network incurs.
  • the filtered recovered clock (311) is fed to the UniNet LAN Reference Clock Generator (17) for providing the 125 MHz receive reference clock signal to the Measurement Source Selector (14) for measuring the phase and frequency offsets relative to the disciplined reference signal (19A). This is done so the UniNet LAN communication signal, phase & frequency offset calibrations and phase & frequency transfers can commence.
  • the LAN Reference Clock Generator (17), as illustrated in figure 43f, is a Phase-Locked Loop (PLL) Frequency Synthesizer.
  • PLL Phase-Locked Loop
  • This block is the signal synthesizer for the UniNet LAN reference RN signal . It provides a pre-scaler performance (178,172) for high frequency operation, permitting PLL designs that can utilize a smaller VCO division ratio (176).
  • the block 17 design makes possible wider loop bandwidths yielding faster settling phases and lower VCO phase noise contributions (179).
  • the Reference Clocks and Measurements Subsystem provides the system heartbeat and reference sources for the Com2000TM UniNet LAN System, as indicated in figure 43.
  • the control of this subsystem is from the Clock Transfer Precision Logic block (166), which executes the mode 2 VHDL logic algorithms for disciplining the local oscillator of the Com2000TM system.
  • the mode 2 logic is designed for autonomous operation.
  • the Com2000TM has three distinct phases of operation for disciplining the internal oscillator to the absolute phase and frequency reference for RN reference signal. The first phase is the Frequency Jam Control, the second phase is the Phase Jam Confrol and third phase is the Closed Loop Tuning Control.
  • the Reference Clocks & Measurements control logic controls the clock skewing of the local oscillator for disciplining to the Precision clock reference.
  • the Com2000TM System receives the Precision phase measurement (16) for the local oscillator frequency and phase offset values from the Phase Estimator Control Solution (M202). This data is used by the Com2000TM system to determine the frequency value of the local oscillator (23) relative to the tracked Precision coded signal frequency (19J) and the phase of the local oscillator (123) relative to the phase value decoded from the Precision Reference signal (19L).
  • the Reference Clocks and Measurements Control Logic loads the controlled frequency value (the Phase Estimator Control Frequency solution), with certain gain K, into the Numerical Control Oscillator, or NCO, using the received Phase Estimator Confrol Frequency offset value.. This is done every cycle as defined by the Phase Estimator Control Solution rate and the Suspend Time Logic (M216). Once the Phase Estimator Control frequency solution is within 500 ps/s (M203) of the frequency enor, the gain K for the Frequency Jam mode is adjusted (M204) and the Frequency Jam Cycle repeats.
  • the Frequency Jam Mode is performed every cycle at the Phase Estimator Confrol solution rate until the value is within 50 ps/s (M205) of the frequency enor.
  • the Clock Control Logic (M201) then transitions the system into the next state, the Frequency Fine Tune Mode.
  • the gain value K for the Frequency Jam mode is quite large and the Frequency Fine Tune Mode gain value K is quite small.
  • the Phase Estimator Control for the Frequency Fine Tune mode solution value is loaded into the NCO. This is done for every cycle at the Phase Estimator Control solution rate until the value is within 20 ps/s (M206) of the frequency enor.
  • the Clock Control Logic transitions the system into the next state, Phase Jam Mode, upon completion of the Frequency Fine Tune Mode. Using the received Phase Estimator
  • the Reference Clocks & Measurements Control Logic loads the controlled Phase value (The Phase Estimator Control solution), with certain gain K, into the NCO during the Phase Jam mode. This is done every cycle as defined by the Phase Estimator Confrol Solution rate and the Suspend Time Logic (M216). Once the Phase Estimator Control phase solution is within a 1000ns (M207) of the phase enor, the gain K for the Phase Jam mode is adjusted (M208) and the Phase Jam Cycle repeats. This is done every cycle at the Phase Estimator Control solution rate until the value is within 50 ns (M209) of the phase enor. When this is achieved the Clock Control Logic (M201) transitions into the next state of operations.
  • the conected 100 PPS (159A) is adjusted by the amount indicated in the next Phase Estimator Confrol phase offset solution and the Precision sensor is commanded to adjust its internal Precision phase calculation with the same amount as the phase jam value.
  • the logic will transition into the Closed Loop Tuning mode (M212).
  • the NCO is loaded with the 70%, 50% and 30% values of the Phase Estimator Control frequency solutions for a frequency enor of 500 to 400 ps/s, 400 to 100 ps/s and 100 to 1 ps/s respectively.
  • the time (phase) is loaded with the 70%, 50%, 30% value of the Phase Estimator Control phase solutions for a time (phase) enor of 1000ns to 500ns, 500ns to 200ns and 200ns to 50ns respectively.
  • the Valid Data signal (M211) is enabled and the Disciplined Mode is completed.
  • the Channel Equalization Filter (312) and the Clock Recovery Controller Logic (311) select the derived Conected 125 MHz signal source (19F) as the reference signal for the PLL and the decoding (313) and encoding (315) blocks, as illustrated in figure 48.
  • Mode 4 Calculate Internal Communication Channel Bias for calibration.
  • the Com2000TM UniNet communication receiver as illustrated in figure 47a, 47b, is phase locked to the internal transmitter BIT (Wrap around injection) signal with a clock frequency that is traceable to the 125 MHz Reference signal source (19F).
  • BIT Wide around injection
  • the channel phase and frequency offsets are determined. This is a state where the Com2000TM's communication channels are internally locked to the local reference signal (123) and the phase and frequency offsets for the transmitters and receivers of the channels are determined relative to the absolute reference phase and frequency source (123).
  • the Phase and Frequency measurement (14) are performed for the selected communication channel, as illustrated in figure 43 d.
  • the offset of the 100 PPS Reference signal (15) and the 100 PPS derived from the UniNet LAN received signal (9) has to be determined.
  • the 100 PPS phase offset value and frequency offset value of the BIT signal and the LAN reference source is determined.
  • the conected Precision PLL 500 MHz signal (147), as illustrated in figure 43d, is down counted (142) in series decade counters to 100 Hz (149A).
  • the 100 Hz and the Precision conected 100 PPS (149B) are in phase with each other but with some fixed but unknown offset.
  • a one-phase measurement is made by latching (143) the phase of the counter (142) of the Precision conected 100 PPS signal selection (149B).
  • the received external 100 PPS (9) is selected at switch 7 for the Mux input signal (149C) and is selected through the Mux (145).
  • the phase of the counter (142) is again latched (143) and the difference between the precision 100 PPS latched value and the external 100 Hz latched value is the phase offset relative to the Precision conected 100 PPS (149B).
  • the measurement continues at a 0.1-second update rate.
  • switch 5 selects the external input frequency source for the Auto Selector (121) input frequency.
  • the external input is divided down (19A) to a 100 Hz signal.
  • the 100 Hz is passed through the Mux (145) to the Sync (144) to latch (143) the phase of the 500 MHz down-counter (142).
  • the one-shot (144) phase measurement accuracy of 5 parts per billion is initially obtained. The resolution improves when integrated over time. At 500 seconds, during normal channel communication, the measurement resolution reaches the specified 10 parts per trillion resolution. All counter measurements are averaged for 500 seconds to insure full resolution at each subsequent measurement ( 100 Hz).
  • the Com2000TM UniNet communication channels are internally locked to the local reference signal source (123) without transmitting or receiving any data from the communication channel.
  • the system phase is maintained and calibration is done periodically. This phase is performed during IDLE system operation.
  • Mode 6 Select The Communication Channel For Phase and Frequency Transfers.
  • the external Com2000TM communication channels are selected and internally locked to the local reference signal source (123) to be ready for fransmitting and receiving data to or from the selected communication channel.
  • the system phase is maintained and calibration is still done periodically via the synchronization training sequence of the equalizer filter and the reference tone from RN.
  • Mode 7 Establish Communication Channel
  • the Com2000TM communication channels are sending and listening to and from external nodes.
  • This state performs a signal search in two-dimensional space, frequency and phase, for the received data signal. It performs a frequency search and then phase-locks the received preamble training PN sequence of the burst signal.
  • the received signal offsets from the local reference are determined and compared with the expected frequency and phase cell of the sending node.
  • E-DNA node specific electronic signature
  • the transmit reference carrier is phase locked to the local reference signal source (123) and the encoded data is superimposed on the carrier for sending the data out on the selected communication channel.
  • the Com2000TM Transceiver System extracts the station ID (filter PN sequence training preamble) or identification information from the data received from each station node and determines if the station is a proper group member. If the inconect ID is received, the LAN/WAN UniNet fransceiver will keep attempting to extract the ID from the data until the conect or expected station ID is received.
  • Mode 8 Calculate External Communication Channel Offsets or Biases for calibration.
  • the UniNet PN communication receivers are phase locked to the external transmitter signal with a clock frequency and phase that have unknown offsets relative to the internal local reference that is traceable to the 125 MHz Reference signal source (19F).
  • phase and frequency offsets on the transmit and receiver section of the channel are determined relative to the absolute reference phase and frequency source (123). This condition is existed when the user wants to measure the PN receiver's host computer clocks relative the RN fransmitted reference clock.
  • the Phase and Frequency measurements (14) are performed for the selected communication channel utilizing its received derived 100 PPS frequency signal.
  • the Com2000TM UniNet Transceiver unit includes circuitry to count the number of cycles after the "On Phase” mark when decoding the data and resolving down to the " Digital Carrier Cycle Resolution".
  • the unit outputs a 100 PPS pulse synchronized to the phase code "On Phase” mark.
  • This pulse is available as a TTL/CMOS output and can be used to initiate a host (MAC) interrupt that is a precision interval clock pulse for host reference.
  • MAC host
  • This interrupt pulse can be programmed to generate a synchronized pulse from 2000 PPS to 100 PPS.
  • This provides an absolute time reference source capability within the Com2000TM Transceiver's host domain. This can be used as an UTC and World Standard time reference (i.e. year 2000- rollover solution).
  • Mode 9 Perform 1 Way Frequency & Phase Transfer to an External Communication node.
  • the Reference Clocks and Measurements Subsystem performs the phase and frequency transfer between nodes with an absolute reference from the sending node to a receiving node that has no absolute frequency tone signal references from the RN.
  • the TDM tracking and timing recovery is utilized instead.
  • Mode 10 Perform 2 Way Frequency & Phase Transfer to an External Communication node.
  • full duplex phase and frequency transfers can commence. This is done in the full duplex signaling mode such as baseband signal PAM5 over the chaimel CAT5. Since the signaling of QAM is used for UniNet share structure, as illustrated in figure 03, this mode can be only utilized when there is different frequency carrier channel for uplink and downlink. Anyhow, during the Full duplex transfer technique is used for point-to-point phase and frequency transfer to obtain the highest precision and accuracy.
  • Both the Slave and Master receive and transmit stations exchange timing and frequency information through the communication channel protocol employing appropriate coding signals for Category 5 UTP infrastmcture and pseudo noise (PN) coded signals for security.
  • PN pseudo noise
  • the relative phase measurement consists of simultaneous phase interval measurements (14) at both the Slave and Master nodes in which the 100 PPS generated by the local clock (159A) starts both the local phase and frequency counters (142,143).
  • the master 100 PPS signal is encoded and transmitted across the communication channels.
  • the received encoded 100 PPS stops the remote phase and frequency counters (142,143).
  • Tl- T2 The relative phase difference, Tl- T2, between the clocks of both stations is given by the following equation:
  • Tl-T2 1/2(C1-C2)
  • C1-C2 is the difference of the phase counter readings of station 1 and station 2, which are exchanged in order to compute the clock difference.
  • dlU, d2U is the Transmit link delay of station 1 and station 2 dlD, d2D is the Received link delay of station 1 and station 2.
  • dl2, d21 is the path reciprocity terms from 1 to 2.
  • (dl2 - d21) is the difference of the Category 5 UTP infrastmcture or wireline transceiver delays in both signal directions.
  • dlTx - dlRx is the differential delay of the transmit part and receive part (station delays) of station 1 and 2. The knowledge of these station delay differences determines the accuracy of the phase comparison.
  • the Frequency measurement follows. It consists of simultaneous Frequency interval measurements (14), as illustrated in figure 43d, at the master and slave nodes for an extended period of time. This enables clear definition of the slope of the curve of the counter readings relative to the measurement phase interval.
  • the Com2000TM communication channels are externally locked to the system reference signal source (123).
  • the system nodes continuously transmit and receive IDLE or Synchronization symbols to maintain system phase and frequency synchronization within a fixed tolerance.
  • the system returns to normal transmit and receive mode upon receipt of a valid data symbol.
  • the Com2000TM smart algorithm of the Com2000TM Precision Clock Reference (344) improves the quartz based oscillator system performance, making it equal or better than a cesium-based solution.
  • the algorithm (344) compares the oscillator frequency (345) with an absolute signal traceable to the World reference signal. By learning the aging behavior and the environment effects on the oscillator over time, the Com2000TM Smart Clock adjusts the oscillator output frequency accordingly and significantly improves the accuracy.
  • the ensuing discussion deals with the ConxZOOOTM Precision Clock Reference (344), as shown in figure 47b as the OSC and Precision Clock Reference, fast and efficient frequency and phase estimation and transfers in an additive white Gaussian communication channel.
  • the frequency and phase transfers of the Com2000TM Precision Clock Reference (344) from node to node can be associated as calibrating a low precision of a frequency source's node relative with another node with a high precision frequency reference source.
  • the following discusses the Com2000TM Precision Clock Reference (344) efficient phase estimation in an additive white Gaussian noise environment, where the received modulated signal is a function of both phase and frequency enor (Delta Phi, Delta f).
  • This section describes a modified version study of the Com2000TM Precision Clock Reference (344) phase estimator. The comparison is performed in terms of two criteria - estimator variance and phase ambiguity resolution, reference Figure 43a.
  • the Com2000TM Precision Clock Reference (344) In order to take advantage of the Com2000TM Precision Clock Reference (344) , as shown in figure 47b as the OSC and Precision Clock Reference, a gain term is provided for digital coherent communications.
  • the input of the Com2000TM receiver detection device (351,353) is independent of any phase and/or frequency enors (Delta Phi, Delta Frequency). These enors come about as a result of the small discrepancies between the transmitter and receiver oscillator (344) frequencies, or may be introduced by the communication channel.
  • the process of ensuring enor independence is called synchronization, and generally the Com2000TM Precision Clock Reference (344) synchronizers fall into on of two categories.
  • the First category is where the received signal is fed into a tracking loop (353) whose objective is to track the phase and frequency enors, thereby driving some enor signal to zero.
  • a tracking loop 353
  • Two of the common examples of such loops include the re-modulator and Costas loop. Since these loops possess feedback, they suffer from hang up, and thus they tend to have large acquisition time.
  • these Com2000TM Precision Clock Reference (344) synchronizers are not applicable if Delta Phi, or phase, and Delta Frequency are quickly varying, or if the information is transmitted in bursts (as is the case for an Ethernet and TDMA UniNet scheme).
  • the Com2000TM Precision Clock Reference (344) as shown in figure 47b as the OSC and Precision Clock Reference, synchronizers that fall under the second category are more appropriate.
  • the Com2000TM Precision Clock Reference (344) synchronizers can handle both types of data clock modes.
  • the continuous data clock mode such as 100/lOOOBaseT signaling scheme for 802.3ab (IDLE Symbols) and burst type transmission such as TDMA signaling as illusfrated in figure 03. These are classified as feed forward estimators and have the property of a fixed and fast acquisition phase due to synchronization circuitry of the Com2000TM Precision Clock Reference (344).
  • the estimate of Com2000TM Precision Clock Reference (344) derived from the estimated denote Delta Phi Hat and Delta Frequency Hat and is based on a block of received data for equalizers to process and refened to as the observation window.
  • This data is processed in such a way that the Com2000TM Precision Clock Reference (344) estimates for Delta Phi and Delta Frequency are obtained via aiding from the receiver equalizers. These estimates denote Delta Phi Hat and Delta Frequency Hat and are used by a phase rotator to conect the received data through the Com2000TM Measurement Circuitry (343). Since the estimators are feed forward, hang up cannot occur.
  • the receiver PN equalizer is tracking signal RN source and it is used as the reference source for disciplining the local oscillator or Com2000TM Precision Clock Reference (344).
  • the calibration of precision frequency and phase sources of the Com2000TM Precision Clock Reference (344) requires comparison between the oscillator device to be calibrated and a precision reference source. All secondary frequency sources, such as quartz oscillators, require periodic calibration, usually against a local reference standard from another node. For the highest precision reference node, comparison against a national reference standard may be required.
  • the main concern of the calibration process of the Com2000TM Precision Clock Reference is the ability to determine the frequency of a given unit relative to the accepted definition.
  • a means of obtaining "traceable" comparisons is required.
  • the local Com2000TM Precision Clock Reference (344) parameters are the phase and frequency that are maintained at the calibrated node, and are synchronized in phase and frequency with the reference node.
  • the phase and frequency reference signals may be transmitted with digital signals from one site to another.
  • the Com2000TM Precision Clock Reference (344) receiving (phase and frequency) signals are degraded by the propagation delay and induced line noise.
  • a more subtle effect that degrades the Com2000TM Precision Clock Reference (344) reference signal is the environmental performance of the transmission media. The following describes the transmitting and receiving equations for the Com2000TM system implementation.
  • Fs F0 + Fsref * t + Fsenor * t
  • Ps Ps + (Fs/Fsrf- l)*t + l
  • Fr F0 + Fnef * t + Frenor * t
  • Pr Ps + Pr + (Fr/Fnf- 1 )*t + l ⁇ (a) t 2 + Pr_noise + Pr_intrinsic_delay;
  • Advanced Channel Measurement & Control techniques enable any topology media channel calibration for optimal signal controls and intelligence flow, as illustrated in figure 03.
  • Today's cable and wireless communication infrastructures are less than ideal. There are many instances where the highest achievable data rates are not possible due to the imperfections and defects of the communications medium.
  • Com2000 tm Channel Measurement, Calibration and Control Technology perform the following process:
  • the communications channel between each node pair (RN, PN), as illustrated in figure 03, must be first be synchronized and then characterized so that enors and imperfections, such as frequency and phase distortions, can be identified.
  • Com2000 tm s calibration system uses these measurements to improve communication channel resolution by controlling the enors and imperfections of the channel.
  • the channel enors In an ideal world and conditions of the data communication between 2 devices and it is existed when the channel enors in range, power, phase, frequency, timing, or any other signal parameters are negligible just as the two communicating devices are integrated into a single chip size space.
  • the two communicating devices In realistic world of data communication, the two communicating devices are always apart in range and distance via a communication channel, either as the guided medium such as Fiber optics, Copper wires,.. etc, or non-guided medium such as air in the case of wireless communication.
  • the signal enors are therefore induced and effected each of the signal parameters differently while traverse over the established communication channel. To characterize and calibrate the enors is the function of this step
  • the allowable communication channel between (RN, PN) node's operating frequency range is measured. This is done to avoid any frequency interoperable issues.
  • a family member may still want to use the Analog Phone or The 56K modem, The xDSL G.lite modem, The ADSL modem and the UniNet Networking all in the same time. Each of these devices operates over a specified operating frequency range.
  • Analog Phone & 56K modem is at 0-4KHz; G.Lite modem is at 25KHz - 500KHz; ADSL modem is at 25KHZ- 1.1MHZ frequency range.
  • the UniNet will sniff the environment in frequency at the initialization and periodically in order to determine the best and safe operating frequency range for the Networks automatically without contention. This is done determined based on the activity of the channel during measurements, predetermined and pre-configured value from the user of each node.
  • any type of communication channel there is distortion that can cause enors in data signaling thereby reducing effective throughput.
  • the signal's characteristics often changes as the signal propagates along the channel.
  • the imperfections in the communication channel tend to reduce the resolution of the data bandwidth of the signal being transmitted across the channel.
  • the data may not be interpreted conectly at the receiving end of the channel if the transmitted signal's characteristics are outside of a defined signal's parameter range, as illusfrated in figure 03.
  • Com2000 tm Channel Measurement and Calibration Control Technology measures and calibrates the communication channel to determine the highest possible data capacity for a particular medium.
  • Measurement and Calibration (343), as illustrated in figure 44, system are very powerful tools for troubleshooting and calibrating communication channel across any wireline and wireless channels. Once the reference signal has been subtracted, it is easier to see small enors that may have been swamped or obscured by the signal distortion and modulation itself as in the case of filter or equalizer initialization during the training sequence.
  • Com2000TM Measurement (343) Technology is used to measure many parameters that contribute to the propagation delays of communication channel infrastmcture.
  • the Com2000TM Measurement circuitry (343) is also used to measure ranging via phase interval, frequency, period, pulse width, power, sampling phase, rise and fall time and also does event counting. This capability of the Com2000TM Measurement (343) system is then used to determine the frequency and phase enor or drift due to the communication channel assuming the sending and receiving frequencies are synchronized and have the same heartbeat. With built-in frequency and phase counter capabilities, Com2000TM Measurement provide another method for determining the channel transmission medium frequency and phase distortions.
  • non- uniform noise distribution or discrete signal peaks indicate the presence of externally coupled interference.
  • the goal of the Com2000TM Measurement and Calibration (343) system is to ensure that the sending and receiving selected parameters are the measured and calibrated.
  • the five or more parameters measured by the Com2000TM Measurement (343) system are power, frequency, phase, timing and pulse code modulation accuracy
  • the communications channel must also be characterized so that errors and imperfections, such as frequency and phase distortions, can be identified and calibrated.
  • CorhZOOO 1 1 Channel Measurement and Calibration Confrol Technology uses these measurements to improve communication channel resolution by controlling the enors and imperfections of the channel.
  • the channel magnitude and phase response of the channel can be measured using conventional LMS criterion just as the Kalman filtering process does in time.
  • the difference between the Com2000TM received signal modulation PN phase vector and the ideal reference signal PN phase vector is the channel phase modulation enor. It can be expressed in a variety of ways such as Enor Vector Magnitude (EVM), for amplitude magnitude Enor, Phase magnitude enor, and any other measured signal's parameters.
  • EVM Enor Vector Magnitude
  • Com2000TM EVM Residual measurements of the Com2000 tm Channel Measurement and Calibration Control (343) system are very powerful tools for troubleshooting and calibrating communications across any wireline and wireless channels. Once the reference signal parameter has been subtracted, it is easier to see small enors that may have been swamped or obscured by the single individual or a combination of other signal's parameter distortion and enor modulations.
  • EVM Enor Vector Magnitude
  • N 4.
  • M-QAM demodulator (332) to decode the Com2000TM incoming data, the exact magnitude and phase of the received signal for each 4 x baud clock (sampling) transition must be accurately determined.
  • the logic layout of the constellation diagram and its ideal symbol locations are determined genetically by the modulation M-QAM format.
  • the Com2000TM Measurement (343) system can measure the received signal's magnitude and phase. These values define the actual or measured phasor. The difference between the measured and the predefined reference phasors forms the basis for the EVM measurements of the Com2000TM Measurement (343) circuitry.
  • the Com2000TM EVM is defined by the average voltage level of all the symbols (a value close to the average signal level) or by the voltage of the outermost (highest voltage) four symbols.
  • the Com2000TM Measurement (343) system measures of phase enor vector magnitude and related quantities can, when properly applied, provides great insight into the quality of a M- QAM digitally modulated signal.
  • the Com2000TM Measurement (343) system can also pinpoint the causes of any problems related to power and phase by identifying exactly the type of degradation present in a signal and even lead to the identification of the sources.
  • the Com2000TM Measurement (343) system can further resolves the enors into its magnitude and phase enor components. It can be individually or in combination compared to their relative sizes, and when the average phase enor (degree) is substantially larger than the average magnitude enor, it can be determined that some sort of unwanted phase modulation is the dominant enor (Inter-Symbol Interference). This is caused by noise, spurious or cross-coupling problems in the Com2000TM reference frequency and phase lock loops, or other frequency generating stages. This can be used then to calibrate the jitter window. Uniform noise is also a sign of some form of phase noise (random jitter, residual PM/FM)
  • the Quadrature enor when the Q-axis height does not equal the I-axis width, is caused when the phase relationship between the I and Q vectors are not exactly 90 degrees at the time signal arrives the receiver.
  • enors may be conelated to specific points on the input waveform, such as peaks or zero crossings.
  • the Com2000TM Measurement (343) measured EVM in this example case, is a scalar (magnitude-only) value. Enor peaks occurring with signal peaks indicate compression or clipping. Enor peaks that conelate the signal minimum suggest zero- crossing non-linearities. These enor value can be quantified and calibrated accordingly, specially on the wireline communication channel case.
  • Non-uniform noise distribution or discrete signal peaks indicate the presence of externally coupled interference.
  • the goal of the Com2000TM Measurement (343) system is to ensure that the sending and receiving Signal parameters are as close to the same as possible; as an example in the case of frequency and phase.
  • the present invention accurately measures the signal parameters in the wireline or wireless digital data communication system. Measurements include analyzing the Com2000TM UniNet QAM code phase modulator and demodulator, characterizing the fransmitted signal quality, locating causes of high Bit Enor Rate (BER) and monitoring and maintaining link noise budgets.
  • the four parameters are measured by the Com2000TM Measurement (343) system : power, frequency, timing and burst code modulation
  • the Com2000TM Power Measurement (343) system measures the power, which includes carrier power and associated measurements of gain of the transmitter drivers and insertion loss of filters and attenuators at the transmitter side.
  • the signals used in the Com2000TM digital modulation are PN or Pseudo Random Sequence noise-like.
  • the Com2000TM Measurement (343) system measures Band-power or the power integrated over a certain band of frequencies or power spectral density (PSD). PSD measurements are normalized power to a certain bandwidth, usually 1 Hz. frequency counter measurement techniques are often not accurate or sufficient enough to measure center frequency.
  • PSD power spectral density
  • the Com2000TM Frequency Measurement system utilizes a measurement technique that determines the average accumulation of the PSD across a known bandwidth such that the roll-off and center points for a particular bandwidth are determined. This provides the capability to maintain the optimum probability of signal detection by estimating the carrier centroid, which is the center of the distribution of frequency versus PSD for a modulated signal.
  • the Com2000TM Duty Cycle Measurement (343) system measures duty cycle distortion that is made most often in pulse or burst mode. Measurements include pulse repetition interval or PRI, on time, off time, duty cycle, and time between bit enors. Turn-on and turn-off times are also involved with the power measurements.
  • the Com2000TM Phase Measurement (343) system measures Modulation accuracy that involves measuring how close either the constellation states or the signal phase vector trajectory is relative to a reference phase vector trajectory or ideal signal trajectory.
  • the Com2000TM received signal is demodulated and compared with a Com2000TM reference signal parameter source for every parameter measurement case.
  • the received signal phase is subtracted from the reference signal phase and the result is the difference or residual.
  • Modulation accuracy is a phase residual measurement for the signal that propagate over this communication channel.
  • the frequency and phase counter capabilities provide another method of measurement for the Com2000TM Measurement (343) system for determining the channel transmission medium frequency and phase distortions.
  • the Com2000TM frequency counter function of the Com2000 TM Measurement (343) system is a versatile device. Most simply, it is used to directly measure the frequency of a signal applied to its input port, which is derived from the recovery clock of the received signal carrier of the phase lock loop. The accuracy of the measurement is directly related to the internal resolution of the counter (50ps) and the stability of the internal frequency source (344).
  • the performance of the Com2000TM Measurement (343) system frequency counter is significantly improved in both accuracy and stability by using the external precision reference (standard frequency reference such as SONET stratum 1) node's frequency source as an external phase base for the counter.
  • the Com2000TM frequency counter function of the Com2000TM Measurement (343) system are still limited by their internal design resolutions on the order of 50 part per billion. But most high precision frequency sources can still be adequately evaluated by direct measurement with a Com2000TM frequency counter. Another measurement is the stability and the accuracy of the receiving signal. Overall accuracy and stability is governed by the signal with the worst stability. Therefore, unless it is known that the Com2000TM frequency reference source (344) is significantly better than that being measured, we can only conclude that the signal being measured is no worse than the measurement indicates and may be much better.
  • Another method of frequency and phase measurement of the Com2000TM Measurement (343) system is the comparison of two signals that are essentially identical. This involves comparing the change in phase between the two sources. Both signals are applied to a digital linear phase comparator and the result is accumulated as a function of time. The data variation in time is similar to "Direct Phase Interval" variations as a function of the time, but is generally continuous. The slope of the comparator's results in time indicates the difference in frequency of the unknown signal versus the frequency reference (344). This capability of the Com.2000TM Measurement (343) system is then used to determine the frequency drift of the communication channel assuming the sending and receiving frequencies are synchronized and have the same heartbeat relative from the known accurate reference source.
  • the built-in Phase Interval counter of the Com2000TM Measurement (343) system is now available with resolutions on the order of 100 picoseconds.
  • the Com2000TM frequency measurements of a very high precision source (344) can be made against a known frequency reference source.
  • the degree of precision is governed by the signal with the greatest amount of noise, or instability, in the signal.
  • the "Phase-Difference" technique of the Com2000TM Frequency Measurement (343) system is a method for comparing two signals that are essentially identical in frequency.
  • the Start signal for the Com2000TM phase counter feature is derived from the internal reference frequency source (344).
  • the Stop signal for the Com2000TM phase counter is derived from the external unknown frequency signal source (as an example, it can be from the recovered receiving signal clock's phase and frequency of Clock Recovery (353) system.
  • the Com2000TM Measurement (343) system measured phase interval between the start and stop signals can be estimated as a function of elapsed time.
  • the maximum phase interval that can accumulate is the "period " of the highest frequency applied to either the "Start" or "Stop” inputs of the counter.
  • the Com2000TM Measurement circuitry (343) is also used to measure, but not limited to, phase interval, frequency, period, pulse width, phase, rise and fall time and also does event counting.
  • the Com2000TM Measurement (343) circuitry measures the phase interval between two independent signals A and B. This is used to measure the electrical length and time enor of the communicating channel.
  • the CAT5 cable can be configured as end to end or single ended with the remote end shorted to ground or left open.
  • the Measurement circuitry's stable 125 MHz reference signal (344) as stimulus, the propagation delay from one end of the CAT5 cable to the other, or between the incident and reflected rising edge of the pulse and the phase offset can be measured. Knowing that electricity travels at approximately lft per 1.7933 ns, or 136.65 ps/inch, the CAT5 cable length is easily calculated. This technique can be applied to the wireless channel as well.
  • phase distortion or time enor from the transceiver's input to the output is also measured with the Com2000TM Measurement (343) circuitry.
  • Transmission Jitter of the signal is defined as short-term phase variations or phase distortion of the significant instants of a digital waveform from an ideal clock running at the same average rate as the signal.
  • Signal Instant refers to any clearly defined point, such as zero crossing.
  • Pulse Width Measurement Data communications and telecommunications use different modulation schemes to minimize the amount of data transfers and maximize the signal to noise ratio.
  • the Com2000TM transceiver can uses any conventional 3-11 pulsewidth modulation scheme to define the equivalent pulse width of the channel. This scheme produces data patterns with different pulse widths.
  • the Com2000TM Measurement (343) measures the pulse width of any signal and their variations within a specified phase interval between any two independent signals A and B. This is used to measure the electrical pulse length characteristics of the CAT5 channel as an example.
  • the Com2000TM Measurement (343) system measures the transition time.
  • the Com2000TM Measurement (343) system allows a squelch circuit to be triggered with the start and stop voltage thresholds to obtain maximum flexibility in rise and fall time measurements so that any part of a transition may be measured and analyzed.
  • the Com2000TM Measurement (343) system measures a self-generated OSC reference and compares this to the input receiving signal for determining the quality of the input frequency.
  • the Com2000TM Measurement (343) analyzes the source over a set gate phase (Delta T) and then, for that interval, determines the maximum and minimum frequencies and the associated jitter, revealing the quality of the source. Frequency is measured as N/Delta_T and the period is measured as Delta_T/N, where N is the number of cycles and Delta_T is the elapsed phase to complete N cycles.
  • the Com2000TM Measurement (343) circuitry measures the difference in phase between the input and output and a self-generated reference phase.
  • the Com2000TM Measurement (343) circuitry also has the capability to operate as a pulse counter that counts either transmit or receiving electrical pulses at a rate of up to 100 MHz.
  • the resolution of the measurement, or single shot resolution is typically 50ps RMS. This number can be improved by averaging over many measurements, or in the case of frequency and period measurements, increasing the time gate.
  • the absolute enor (the difference between the measured value and actual value) is typically less than Ins for a time interval measurement of less than 1ms. This enor is of interest in determining how far a value is from the actual value. Often only the relative accuracy (the difference between two measurements) is important.
  • the differential non-linearity is a measurement of the relative accuracy of a measurement and is specified as the maximum phase enor for any given relative measurement.
  • the Com2000TM Measurement (343) circuitry differential non-linearity is typically +/-50 ps.
  • the Com2000TM Measurement (343) circuitry measures the short-term stability of an oscillator frequency.
  • the short-term stability is a measure of the changes in the output of frequency of the oscillator on a short time scale (seconds or less). These changes in the frequency are usually random and are due to the internal oscillator noise. These random changes in frequency affect the resolution of the measurement just as other internal noise.
  • the short-term stability of the Com2000TM is lsec in 50 parts per billion. The measurement resolution for an interval 1 second gate or time interval, will be dominated by the short term stability.
  • the Com2000TM Measurement (343) circuitry measures the long-term stability of an oscillator.
  • the long-term stability is a measure of the changes in the output of frequency of the Com2000 TM oscillator on a long time scale (days, months or years). These changes in the frequency are usually due to the internal oscillator's aging rate or physical change of the crystal and temperature response. This drift change in frequency affects the resolution of the frequency measurement of a long phase interval just as other internal noise does.
  • the long-term stability of the Com2000TM in a day (aging rate for one day) is one part per million. The measurement resolution for a lday interval gate or time interval will be dominated by the long-term stability.
  • Freq Drift #Days * Aging Rate * Osc Output
  • the long-term stability of the oscillator does not pose an issue for the Com2000TM system. This is because the Com2000TM provides a common distributed clock reference source throughout the network system. This RN reference source is monitored and conected during the Com2000 TM network system operation. Therefore each of the network nodes is referenced to the same clock RN source which minimizes the relative long-term stability affect, specially the RN reference is traceable to the world frequency standards.
  • the allowable communication channel between (RN, PN) node's operating frequency range is measured.
  • the UniNet will sniff the environment in frequency at the initialization and periodically in order to determine the best and safe operating frequency range for the Networks based on the activity of the channel during measurements, predetermined and pre-configured value from the user of each node.
  • the UniNet determine the highest possible data capacity for a particular medium by measuring the signal to noise ratio or SNR of the most distance locating nodes during the training period.
  • Com2000 tm Channel Measurement and Calibration Technology measures and calibrates the communication channel to determine the highest possible data capacity for a particular medium for the allowable operating frequency spectmm.
  • the Channel Measurement logic as shown in the figure 44, utilize the frequency measurement capability to search in frequency and detect the signal as the squelch and AGC circuit threshold is exceeded.
  • the ordinary telephone line (CAT3 @ 26 AWG or wire gauge) in the house has the typical frequency response out to approximately 35MHz.
  • the UniNet Home networking system is cunently using the frequency spectmm out to 32.5MHz center at 25MHz with the bandwidth of 25 MHz, as illustrated in the section 5.0, figure 47b.
  • the UniNet receiver center frequency has to move to from DC to 25MHz for the filter to see the signal and then be used to determine whether there is any activity in the cunent looking bandwidth .
  • a frequency mixing process of the front end receiver, for down and up converting from the 25 MHz carrier, from a controlled VCO of the Synthezier block (15) output reference , as illustrate in the figure 43, is needed before the filter of the receiver can see the signal in the filter.
  • the AGC circuit is then be used to detect any activity of the signal within the observed window. This capability is very much needed the wireless applications of the UniNet when the signal has to be down converted to the working IF signal.
  • the operating frequency spectrum is defined by Co ⁇ OOO" 11 Channel Measurement and Calibration Technology, it start to measure and calibrates the SNR of the communication channel to determine the highest possible data capacity for the most distanced nodes of a particular share medium, as illustrated in figure 03.
  • the equalizer filter coefficients of all the nodes on the share medium channel need to be defined and measured. This is done in the training period, during which a Pseudo Random (PN) noise training sequence, also available at each of the node's receiver, is transmitted.
  • PN Pseudo Random
  • a synchronized version of the PN sequence is generated at each of the receiver, where the channel input and output signals are used for the identification of the channel equalizer coefficients.
  • a modulated signal is sent for estimating the maximum capacity of the communication channel pairs (RN, PN) as illustrated in the figure 45, from the calculated received SNR after the slicer.
  • the maximum channel capacity or data speed is the measurement of the SNR from the most distanced PN node relative to the Reference Node for a predefined BER. 5) Summary of Channel Bandwidth Allocation Techniques
  • This section of the technology delivers scaleable bandwidth transmissions while allowing the best possible data throughput across the transmission medium. This is done via a Dynamic Capacity Allocation (DCA) algorithms.
  • DCA Dynamic Capacity Allocation
  • DCA dynamic capacity allocation
  • each node can be a Reference Node (RN).
  • RN Reference Node
  • This secondary RN is on stand-by, and replace the RN only when the primary RN fails.
  • the RN has other functions too.
  • the RN coordinates the transmission of all nodes over the bus. Therefore, other nodes wait for the signaling messages to schedule their transmission
  • Dynamic Bandwidth Allocation or DCA is the UniNet Resource management, which is a centralized resource allocation scheme in which it comprises of two components : The Slot bandwidth allocations ( Slot Repetition Interval or SRI ) between nodes and the Channel bandwidth allocations (Channel Repetition Interval or CRI).
  • the resource defragmentation algorithm is part of the RN DCA algorithm which serve the purpose of maintaining the free pool of slots from gathered in fragmenting way.
  • the Reference node's SRI algorithm capitalize on the dynamic nature of the bandwidth allocation and deallocation requests periodically from the PN node, to establish a Request Refresh Interval for bandwidth deallocation or release of resource should the SRI message is not arrived in the proper interval.
  • the Channel Repetition Interval or CRI algorithm is a method of PN to request the total allowable bandwidth dedicated for the PN for a interval period.
  • This PN channel bandwidth or CRI is composed of both Circuit like Constant Bit Rate (CBR) for continuous real-time flow or Variable Bit Rate (VAR) for continuous and real-time flow and Best Effort Traffic like Burst volume flow (Unspecified Bit Rate or UBR).
  • CBR Constant Bit Rate
  • VAR Variable Bit Rate
  • UBR Unspecified Bit Rate
  • the CRI bandwidth allocation status is keeping tracked by the RN. It is broadcast to PN every CRI refresh cycle. Should the PN CRI request message are not arrived to the RN node at the regular and predefined interval, the PN node total bandwidth (CRI) will be deallocated and left with very minimal default value for maintenance and diagnostic data communication only. This also applies to the SRI algorithm of the DCA.
  • the PN node When a node requires more slots to be allocated, the PN node make a request to the RN node at the predefined SRI interval. The RN will then either honor the request or reject the request via a SRI response status. The condition of RN to honor or reject the SRI request is based on whether it has sufficient free slots for the requests. The SRI response status will send to the requested PN with appropriate status. Each of the PN node will maintain the status table for each of the SRI request histogram. Future algorithm of SRI in the RN will have the capability of honoring different priority level schemes for the requests ID and node ID.
  • the request ID and it associated priority are maintained and also dynamically changes based on the number of time on the PN requests of the same request ID and the total time that it was not served and remain in the request pool. This is done so that it can be avoided during the PN node's bandwidth starvation scenarios.
  • the internal RN confrol related table is broadcast periodically over to all of PN for maintaining the RN table up to date. This is very useful when a new designated PN is to be selected as the secondary RN node and when the primary RN node is down.
  • the PN node can also have an intelligently requests of seeing the total bandwidth of the bus in a time snapshot periodically from the RN point of view. This intelligence enables that in the request by the PN, it will minimize the access delay when the SRI stream is created by the RN and PN pair.
  • the CRI and SRI algorithm of the Dynamic Bandwidth Allocation can be different for different types of traffic and environment it operates in. This can be defined during the initialization of the networks and the pre-configuration tables.
  • the CRI and SRI algorithms provides the Quality of Service or QoS of the UniNet network. There will be different level of accepting and rejecting the requests.
  • the PN node has to make its assessment when the request bandwidth is not honored by the RN. There will be different exception handling mechanism for CRI and SRI algorithms.
  • the form of the Equalizer is considered a combination of LMS (Least Mean Square) based Adaptive Equalizer followed by a non-linear estimator.
  • LMS Large Mean Square
  • the filter coefficients are adjusted to minimize the mean square distance between the filter output and the desired training signal (102).
  • the desired signal which is the channel input, is not available.
  • the Com2000TM Equalizer is comprised of two distinct sections: An adaptive equalizer (FIR Filter) (101), that removes a large part of the CAT5 channel distortion, followed by a Non-Linear Estimator (Decision Device) (103) for an improved estimate of the channel input.
  • the output of the channel's non-linear estimator (103) is the final estimate of the CAT5 channel input, and is used as the desired signal to direct the equalizer adaptation (101).
  • This Blind Equalization method ensures that the equalizer (101) removes a large part of the channel distortion. This method uses a cold start up (104) period during which no training signal is transmitted, and a warm start period during which a training signal sequence is transmitted.
  • Each of the (RN,PN) will be considered as a different and unique communication channel in a multi-channel communication environment. It has its own impulse channel response and its own FFE/DFE coefficients for Equalizer Precoder.
  • a Decision Feedback Equalizer or DFE has better performance compared with a linear equalizer. Also, a DFE with a fractionally spaced Forward Feedback Equalizer or FFE has the best performance.
  • the draw back of a DFE is the enor propagation problem. Because the tail cancellation signal from the DFE is generated according to the estimated signal, a wrong estimation of the signal could reduce the chance of conect estimation of subsequent signals.
  • the channel with severe inter-symbol interference which can be characterized by a channel impulse response with a long tail or a long DFE with significant magnitudes, multiple enors do occur because of the phenomenon of enor propagation. It might take many more symbols intervals for a DFE to recover from the enor propagation.
  • the Tomlinson/Harshima Precoding method for (point-to-point signaling) can be used to avoid the DFE enor propagation problem.
  • the DFE is moved into the transmitter to filter the original data symbols.
  • the section describes the method of Advanced Equalizer Precoding method for point-to-point , point-to-multipoint, or bus signaling topologies, as illustrated in figure 03. It is used to communicate between nodes in a shared medium topology. It is also used to avoid the DFE enor propagation problems.
  • the DFE coefficients are also moved into the transmitter to filter the original data symbols.
  • the conesponding DFE coefficients for each of the node to node path (impulse response) are calculated and transmitted to the transmitter for each of the received impulse response channel/node.
  • DFE here means DFE + DPIC.
  • the process of receiver filtering synchronization, and optimization is defined before the Equalizer Precoding method of measuring the DFE filter coefficient values, freeze and send to the transmitter portion of RN can be exercised.
  • the equalization system capitalizes on the synchronous nature of the signal and optimize the channel response estimations to reduce channel noise.
  • High speed transmission of digital data over the wireline and wireless communication channel requires adaptive equalization to reduce coding enors caused by channel distortion.
  • wireline cable such as POTs, as illustrated in the figure 02, the channel distortions are mostly due to the non-flat magnitude response (amplitude distortion) and nonlinear phase response (time dispersion) of the wireline channel.
  • time dispersion distortion affect is perhaps the most important as time dispersion distortion causes the smearing and elongation of the duration of each symbol.
  • time dispersion results in an overlap of successive symbols, an effect known as inter-symbol interference (ISI).
  • ISI inter-symbol interference
  • the Equalization system in concert with a Synchronous Communication Environment alleviates the relative phase dispersion of the interfered and interfering signals that greatly reduces ISI. This is a critical factor affecting the wireline receiver performance, as illustrated in figure 49.
  • the ECHO and NEXT Canceller's filters are initialized in the Blind Equalization phase. In this phase almost all of the enor signal is ISI and channel noise.
  • the Com2000TM Blind Equalization process utilizes the frequency and phase knowledge obtained from the 5-ary PAM signal input in conjunction with a Synchronous Communication Environment, and a statistical model of the CAT5 channel to estimate the channel impulse response in order to alleviate these noise contributors. The following and the order of the steps define the optimization method for equalizers : 2.
  • the Frequency and Phase clock synchronization ensures the enor signal, e(m), for recursive coefficient calculations noise is relatively small and primarily derived from the CAT5 channel synchronized received data and locally stored patterns during the autoconelation process, as illustrated in figure 45.
  • the memory span is a function of Com2000TM propagation round trip delay measurements, which performs by the Com2000TM Channel Measurement and Calibration Technology.
  • the memory spans determine the number of real filter taps necessary to achieve optimized filter coefficients for tuning, calculations and fast filter convergence resulting in a positive SNR margin. This also ensures the enor signal, e(m), as shown in figure 45, for recursive coefficient calculations noise is relatively small and primarily derived from the CAT5 channel synchronized received data and locally stored patterns during the autoconelation process.
  • PN sequence code is used as the preamble bits for Master and Slave to perform as the background Sounding sequence autoconelation for channel adaptation and also as a station code ID for security access purpose. Please refer to the section of E-DNA Technology for more details.
  • This node ID is also used as Security Spread PN Coding for a Secured Signal Signature. This autoconelation is done to ensure the minimum enor signal, e(m), for filter's recursive coefficient calculations is adaptively to the communication channel response, as shown in figure 45.
  • These sounding sequences or node ID are selected in such a way so that the security, synchronization and filter adaptations can be benefits from them.
  • the conelation is done and the enor derived from the appropriately synchronized received and locally stored PN sequence (Sounding) patterns that are used to update the filter's coefficients recursively and dynamically in order to reflect the CAT5 time-variant channel distortions.
  • PN sequence Sounding
  • Optimize FFE/DFE Equalization Filter Convergence by providing a method of suppressing the ISI caused by relative phase distortions. (Note: This provides an increase in the SNR, filter's convergence level, by optimizing the Com2000TM relative phase). With the symbol and sample clock of the Master and Slave synchronized, the difference of the relative clock phases of the disturbed and disturbing signals are relatively small. Phase offsets from Near and Far cross talk at the receiver from other local and /or remote sending terminal signals is relative phase difference between the desired receiving signal and the interference symbol. Hence, due to the relative phase's ISI is suppressed and the front end receiver benefits the increased SNR. This is due to the filter's converges cleanly with an SNR that has up to 6dB signal SNR additional gain, as shown in figure 51.
  • the measured delta frequency offset is used to provide an optimum Square Root pulse shaping Com2000TM transmit filter with doppler frequency offset compensation, while maintaining the in-band differential mode signal.
  • Another method measures the channel distortions and uses filters to compensate for this distortion, specifically this is done by using a transmit pulse shaping filter and by receiving ECHO, NEXT, FFE and DFE filters.
  • the method equalizes the desired signal in such a way mat the impulse response from the transmitter to the receiver is as close as a Nyquist pulse, which goes through zero at all multiples of the symbol period except at the origin. It also equalizes the NEXT ECHO signal (from local transmitters) in such a way that the impulse response from the local transmitter and local receiver goes through zero at all multiples of the symbol period, including the origin, as shown in figure 51. After passing through a 100m
  • the amount of inter-symbol interference (ISI) at the input of the receiver is larger than the amount of NEXT.
  • ISI inter-symbol interference
  • the initial filter convergence curves of the solid and dashed lines follow the dotted line (see figure 51), which is the convergence curve of the FFE/DFE filter in the presence of inter-symbol interference only.
  • the convergence time with the worst phase is about twice as long as the one achieved with the optimum phase.
  • SNR margin is a measure, in dB, of how much additional noise a system can tolerate or how far the system is from not working properly.
  • the receiving signal jitter has to be confrolled. This is done through a Phase Transfer Technique of Synchronous Communication Environment so that the Com2000 TM Equalizer phase jitter of the signal, between the sending and receiving node, is bounded within 1/64 of the baud period (125ps).
  • This level of phase accuracy enabled by the Com2000TM Master/Slave clock synchronization methods described above, provides additional SNR enhancement for the SPAM-5 signaling, as illustrated in figure 41.
  • the jitter degrades the performance of the ECHO and NEXT cancellers and FFE/DEF filters because it creates a transient mismatch between the samples of the ECHO or NEXT impulse response and the taps of the canceller, as illustrated in figure 53.
  • the ECHO ECHO
  • NEXT cancellers NEXT cancellers
  • FFE FFE
  • DFE filters The Com2000TM Adaptive Filters, or Equalizer, is the combination of filter's optimization techniques and designs used to decrease the channel response length while simultaneously preserving a good SNR in the resultant controlled inter-symbol interference channel.
  • the following steps are taken : (a) Broadcast the predetermined time, frequency and phase training sequences. This is done so that the all of the adjacent sending nodes are sending at the same time interval with the predefined phase and frequency matrix cell, (b) Measure the received EVM phase and power enor vector for phase noise magnitude determination. This will be used to define the maximum and minimum signal level for a specific phase sector angles so that the EVM can compensated for the phase noise enor during normal data transfer mode, (c) Clock Tune and Phase align local stored training pattern to minimum EMV rms enors. This is done so that the local clock's phase and frequency are compensated for this phase noise enor.
  • the RN receivers are able to receive all of the PN node communications.
  • the PN will and can only talk to the RN node.
  • the PN, PN peer to peer communication can only enabled via the RN message relaying.
  • it can broadcast the message to all PNs, which means that the PN receiver will utilize the FFE/DFE and DPIC filters to receive the signal over the bus. All of the PN can receive the RN data signal.
  • the designated PN training sequence for each burst which destine for each of the PN node will be defined and used to converge the FFE/DFE filter with.
  • the sequence is used for the privacy of the multiple access share environments.
  • Each of The PN training sequence definition can be defined and updated in the PN ID table of the RN.
  • the PN ID sequence is dynamically updated and distributed by the conesponding PN periodically should it requires.
  • Com2000 tm Channel Adaptive Equalization Technology measures and calibrates the communication channel to determine the highest possible data capacity for a particular medium.
  • the equalizer filter coefficients of all the nodes on the share medium channel needs to be defined and measured. This is done in the training period, during which a Pseudo Random (PN) noise training sequence, also available at each of the node's receiver, is fransmitted.
  • PN Pseudo Random
  • a synchronized version of the PN sequence is generated at each of the receiver, where the channel input and output signals are used for the identification of the channel equalizer coefficients.
  • a modulated signal is sent for estimating the maximum capacity of the channel from the calculated received SNR after the slicer. The maximum channel capacity is measured from the SNR of the most distanced PN node relative to the Reference Node.
  • the transmitting and receiving portion for each transceiver nodes are trained so that the conesponding DFE coefficients, for a single impulse response channel of the receivers can be calculated.
  • Receiver A will have the DFE coefficients for the impulse response of the channel from A to B.
  • the receiver B will have another set of DFE coefficients for the impulse response of the channel B to A.
  • the Advanced Medium Adaptation & Equalization Precoding method for (point-to-point, point-to-multipoint, or bus signaling) is a method of initializing the DFE coefficients for each node-to-node communication from one transmitter at a time and then moved the data into the transmitter in order to filter the original data symbols.
  • every (RN,PN) communication pair will constitute a communication channel in a multi-channel environment.
  • RN transmitter can send data to either one PN node or to all of the available PN nodes on the bus.
  • RN receiver will only receive one PN node data at a time.
  • Every PN Transmitter will have the setup of the Precoder Equalizer of Tomlinson characteristics. This is done so that RN receiver can only receive one PN at a time without have to do anything to the filters and continue to use FFE filters as to adapt to the channel, as shown in figure 03 and 26. This also means that every PN receiver will also have the ordinary FFE/DFE/DPIC filters, as shown in figure 03 and 26, so that all of them can receive the RN broadcast data messages from the RN transmitter . This is done without Precoder Equalizer .
  • Step 01 Implement the full DFE in the RN receiver
  • Step 02 Disable the Tomlinson filter in the PN transmitter
  • Step 03 PN Transmitter A sends out a fraining sequence signals during coarse training period.
  • Step 04 RN Receiver will adapt its own FFE/DFE data coefficients and store the FFE/DFE coefficients into the internal table for PN transmitter ID.
  • Step 05 Repeat and Go back to steps 03 until all of the PN transmitters A, B, C ...and so on the line are transmitted with the coarse training sequence signal.
  • Step 06 Calculate and determine the best weighted average FFE filter coefficient out of the stored FFE/DFE sets and use it to initialize the FFE filter regardless the channels and Reset the
  • Step 07 PN Transmitter A sends out a fraining sequence signals during coarse fraining period.
  • Step 08 RN Receiver will adapt its own FFE/DFE data coefficients and again store the
  • Step 09. Repeat and Go back to steps 07 until all of the PN transmitters A, B, C...and so on the line are transmitted with the fine training sequence signal.
  • Step 10 Send the value of the DFE feedback coefficients from the RN receiver to the every PN transmitter for each of the every (RN,PN) channel pair
  • Step 11 Setup the Tomlinson filter at the PN transmitter, using these DFE coefficients
  • Step 12 Disable the feedback section of the DFE filter in the RN receiver
  • Step 13 Begin sending data from PN to RN receiver during normal data operation, it should be satisfactory to continually adapt only the linear RN receiver FFE filter.
  • the equalizer coefficient file realizes equalization over the channel. It can be derived and utilized based on the following assumption:
  • N(i) [«,(-) , «.(-) n L (i) ] ⁇ is the noise vector.
  • V ⁇ H (D)
  • R the noise correlation matrix
  • ⁇ H (D) is the D-th column vector of ⁇ H
  • D is the decision delay
  • ⁇ THP is the sub-matrix generated from ⁇ H by selecting the column vectors from (D+1) to (D+ N THP ).
  • ⁇ THP ⁇ H (D + ⁇ : D + N mp ) . Note: By using the above expressions for A and V , we have already assumed that the signal power and noise variance have been absorbed into ⁇ A ⁇ and R , respectively. It suggests that in practical systems, the power used to measure the channel should be equal to the power used to transmit the information bearing data.
  • ⁇ c (i,D + 1 : D + N THP ) denotes the sub-matrix of ⁇ c (z ' ) by selecting the column vectors from (D+1) to (D+N THP ), and ⁇ C (/,E>) denotes the D-th column vector of ⁇ c ( -
  • the optimum weight coefficients for FFE and THP are
  • the correlation matrix of the received samples in the conventional FFE and the correlation vector of the desired symbol with the received samples are required.
  • A T ⁇ ⁇ C (O ⁇ c (0 - ⁇ -7./. ⁇ -W.
  • ⁇ c (i,D + 1 : D + N THP ) denotes the sub-matrix of ⁇ c ( ⁇ ) by selecting the column vectors from (D+1) to (D+ N mp ), and ⁇ c (i,D) denotes the D-th column vector of ⁇ c ( ⁇ ) .
  • the Com2000TM UniNet delivery system is a universal Physical Layer manifestation that delivers a robust high performance and multi-channel high speed data delivery system, as illustrated in figure 03.
  • the Com2000TM UniNet multi-channel signal coding is the selecting signal or a combination of signals from any one of the following selections : (a) Precision Phase Control & Multi-Level Amplitude (Synchronous PAM-M, as illustrated in figure 41), (b) Precision Frequency Confrol & Multi-Level Amplitude signals (Synchronous FDM/PAM-M), (c) Precision Frequency & Phase Confrols & Multi-Level Amplitude signals (Synchronous QAM-M), (d) Precision Frequency, Phase, Time and Multi-Level Amplitude signals (Synchronous TDM/QAM-M).
  • This precisely confrolled communication environment is enabled through Con ⁇ OOO 1 " 1 Signal Confrol Technology.
  • This system provides precise confrol of signal parameters that transfer from one network node to another and propagate through the entire network.
  • This new controlled network environment provides the baseline precision modulation and demodulation required for manipulating and controlling specific signal characteristics such as multi-carrier (FDM), multi-phase (PDM) and multi-time (TDM) signal coding, as illustrated in figure 55.
  • FDM multi-carrier
  • PDM multi-phase
  • TDM multi-time
  • Com2000 tm Signal Coding Technology provides a revolutionary approach for FDM, PDM baseband line signal coding method that increases effective data throughput by increasing the number of symbols per hertz of data transmitted.
  • the data rates as an example for Ethernet data transmission can go up to 2 Gigabits per second. This can only be achieved by new Com2000 tm 's Frequency, Phase or Time synchronous signal coding (Synchronous PAM5 or SPAM5, as illustrated in Figure 41, and 54).
  • This technique applied to the multi-phase single carrier baseband Synchronous signal coding which is able to satisfy the FCC power emission requirements (as suggested in the IEEE 802.3ab standard).
  • the GPHY4 Ethernet system delivers multi gigabit data communication over the same standard 8-wire (2 Gbps over 8 wires) Unshielded Twisted Pair (UTP) CAT5 cable as 100Base-T through the insertion of the Com2000TM technology.
  • the GPHY4 system is implemented at the media Physical Interface to deliver a revolutionary bandwidth efficient coding scheme to support Multi-Gigabit signaling over the existing CAT5 cabling infrastmcture.
  • the selected multi-channel baseband signal scheme is SPAM-5 , which capitalize the precision phase and amplitude controls of the signal, uses both Synchronous and Partial Response or phase delay features of the multi level Pulse Amplitude Modulation signal scheme.
  • the SPAM-5 and/or multi-channel (1 to 20) Synchronous Partial Response NRZ or SNRZ Code Signaling deliver multi-gigabit signaling and scalable network data transmission from 100Mbps to 2000Mbps data rate for Ethernet data over existing UTP Category 5 cable.
  • the base band signal is then multiplied by a carrier, which is a high frequency sine or cosine. After this multiplication, the signal is called a passband signal. This process is called modulation and has the effect that the baseband signal is shifted up in frequency, up to the pass-band.
  • the center frequency of the passband is the frequency of the carrier as in the case of UniNet QAM16 that operates at the center frequency of 25 MHz.
  • the received baseband signal is complex even though the transmitted baseband signal before mixing is real. But then the transfer function from transmitted baseband signal to received baseband signal must be complex- valued ! .
  • the real part of this transfer function is called the In-Phase channel or I-channel, where as the imaginary part is call the Quadrature channel or Q-channel.
  • the SPAM-5 can, therefore, be thought of as an baseband version of QAM/CAP- 1024 signal with the precision control of DC frequency point, and a precision DPIC Precoder Equalizer on the transmitter side for maintaining the symmetry and the real value properties.
  • the conjugate of the complex j component of transfer function can be measured, defined and built-in into the Precoder Equalizer at the transmitter, so that the received baseband signal will be real. This technique maximize the utilization the precision control of the synchronous environment at signal coding level.
  • the Synchronous Partial Response PAM-5 signaling is a Bandwidth efficient coding schemes and a method of increasing the bandwidth efficiency and includes:
  • Pulse shaping (or filtering) 4. Combination of (1), (2) and (3)
  • 10/100/1000/2000Base-T (802.3ab+) achieves the full duplex throughput of 2000 Mb/s by transporting data over four pairs from both ends of each pair simultaneously.
  • Each pair carries a dual duplex 500 Mb/s data signal encoded as Synchronous Partial Response 5-level Pulse Amplitude Modulation (SPAM-5). See figure 41.
  • SPAM-5 Synchronous Partial Response 5-level Pulse Amplitude Modulation
  • each pair carries a 500 Mb/s full duplex data sfream and can be scaled utilizing the system clock adjustment in order to deliver scalable data transfer rates for interim non-compliance to lOOOBase-T CAT5 capacity.
  • the 10/100/1000/2000Base-T Co ⁇ OOOTM Multi-Gigabit signaling is compatible with the 100Base-TX signal so as to facilitate the development of a four data rate 10/100/1000/2000Base-T transceiver.
  • the symbol rate of 1000/2000Base-T is the same as that of 100Base-TX - 125 Msymbols/s.
  • one advantage of having equal symbol rates for 100 and 1000/2000 Mb/s operation is that common clocking circuitry can be used with both data rates.
  • Another advantage is that the spectra of both signals are similar with a null at 125 MHz (figure 7a). The null in the spectmm of a baseband signal occurs at the frequency equal to the symbol rate.
  • 1000/2000Base-T and 100Base-TX both operating at the same symbol rate and using baseband signaling, have similar signal spectra. This reduces the complexity to match the spectmm of 1000/2000Base-T to that of 100Base-TX almost exactly through some additional filtering.
  • the advantage of having similar spectra for 100 and 1000/2000 Mb/s signals is that common magnetic and other emission suppression circuitry can be used regardless of the data rate.
  • a PAM-5 eye pattern for lOOOBase-T is shown in figure 52.
  • An eye pattern is a trace produced by a modulated random data waveform, with each symbol period tracing from left to right and starting in the same place on the left.
  • An eye pattern appears on an oscilloscope if the modulated random data signal is viewed while triggering the oscilloscope on the data clock.
  • the eye pattern of the PAM-5 signal deviates somewhat from this classical 5-level eye pattern because the waveform of the PAM-5 signal has been shaped to make the spectmm of lOOOBase-T match the spectmm of 100Base-TX.
  • a Synchronous Partial Response PAM-5 eye pattern for 2000Base-T is shown in figures 24 and 27.
  • a Synchronous Partial Response PAM-5 eye pattern appears on an oscilloscope if the modulated random data signal is also viewed while triggering the oscilloscope on the data clock.
  • the eye pattern of the Com2000TM Partial Response PAM-5 has twice as many eyes as the PAM-5 signal.
  • the eye's vertical noise voltage threshold is reduced in half relative to the PAM-5 eye.
  • the Com2000TM Partial Response PAM-5 signal is 6 dB less than the lOOOBase-T signal and has been shaped to make the spectmm of the newly proposed 2000Base-T match the spectmm of 100Base-TX. (See figure 24).
  • the Com2000TM Advanced Signal Equalization system improves the SNR up to 8dB relative from cunent 3dB IEEE 802.3ab suggested designs, as illusfrated in figure 28. This enables the front end to recover the 6dB of signal degradation and achieve an extra 2dB for Noise margin improvement over the lOOOBaseT.
  • Partial Response Multi-Level Coding (SPAM-5 & SNRZ)
  • Com2000TM partial response coding involves combining two distinct PAM-5 data signals into one channel, each operating at the same data rate as the combined signal (SPAM-5). These two PAM-5 baseband signals, with one signal staggered in time (4ns) with respect to each other, are combined and fransmitted simultaneously over the ( Figure 16). Since each data signal operates at the same data rate of the partial response signal, the combined 2-phase partial response signal (spam-5) requires the same bandwidth of the original PAM-5 signals.
  • phase offset between the two original signals must be known (equal to a multiple of 90°).
  • the 4ns (180 degree) power sampling level and its previous level with the direction of the transitions must also be known (see figure 11a, l ib).
  • the NRZ signal is HIGH and the NRZ' signal is LOW. If amplitude level is negative (01), then the NRZ signal is LOW and the NRZ' signal is HIGH. If the amplitude level is zero (11 or 00) and if the previous signal level & direction of transition is down, then the NRZ signal is HIGH and the NRZ' signal is also HIGH. Otherwise, if the transition is up, then the NRZ signal is Zero and the NRZ' signal is also Zero.
  • the predetermined phase offset value (4ns) is used to regenerate the NRZ and NRZ' signal from the receiving composite signal (PAM-3).
  • the received signal will have 9 amplitude levels.
  • Each of the sampled amplitude levels will equate to a particular combination of original PAM-5 and its 4ns -delay version.
  • the knowledge of the previous amplitude and its transition direction will dictate the level of the present signals.
  • the Partial Response signaling method is a bandwidth efficient coding scheme employing only multi-level signaling and no phase modulation and is known as a one-dimensional (1-D) coding scheme.
  • Figure 16 demonstrates two possible coding methods - 1-D and Partial Response 1-D - of transmitting 500 MB/s over a 100 MHz channel.
  • the 1-D method generates 2 bits per symbol with a symbol rate of lOOMega-symbols per second.
  • the Partial Response 1- D method generates 4 bits per symbol in order to keep its bandwidth within 100 MHz.
  • the Partial Response 1-D method is capable of fransmitting up to 500 Mb/s in the same channel where the 1-D method is limited to 250 Mb/s 12 .
  • the 2000 Base-T proposed signaling methods are also a 1-D based coding scheme.
  • the signaling method is Partial Response of the composite 1-D signal.
  • the composite 1-D signal is the difference of a multi-level signal with a controlled phase offset by half of the 125Mbaud period.
  • a more detailed description of the Com2000TM signaling system is provided below.
  • the Partial Response of the composite 1 -D signal coding scheme described below is designed to generate 500 Mb/s plus control symbols.
  • the circuitry implementing such transceivers would have to be present at both ends of each pair of the category 5 channel to achieve 500 Mb/s. 250 Mb/s would be achieved with a single Com2000TM transceiver operating with an 802.3ab compatible transceiver. See figure 16.
  • the Com2000TM Coding system codes the signals using(Synchronous PAM-5) a Partial Response of the composite 1-D signal.
  • This 1-D coding method optimizes the multi-level encoding of the transmission signal so as to minimize Inter Symbol Interference (ISI). Partial Response of the composite 1-D signal coding at the transmitter helps to minimize the distortion caused by channel attenuation.
  • ISI Inter Symbol Interference
  • Scalable Com2000TM Signal Coding SPAM-5 is also a Partial Response of the composite 1-D signal.
  • the scalable Com2000TM SPAM-5 coding can be scaled by either slowing down the clock or the SNRZ signal encoding or SPAM-5 signal encoding or the combination all of the above.
  • a bandwidth efficient data signal is typically more sensitive to channel noise and distortion than a binary signal.
  • a good indicator of network robustness is the opening in the eye pattern of the data signal.
  • the size of the opening indicates the signal's immunity to noise - it is proportional to the noise voltage required to cause a bit enor in the receiver.
  • the horizontal opening of the eye pattern typically indicates the signal's immunity to jitter. It is a measure of how much jitter can be added to the data signal by the channel before timing-related bit enors are likely to occur. See figure 7.
  • the coupling between the two channels further compromises noise immunity.
  • the amount of signal coupling between the two channels is related to the enor in the X phase offset between these channels. Any deviation from the perfect sending phase offset (X degree relationship) between the two channels results in cross channel coupling (i.e. one channel "leaking" into the other channel).
  • X degree relationship the higher the efficiency, in bits per Hz, of the data signal, the more vulnerable the signal is to the noise and distortion in the channel. This means that the higher the data rate we attempt to transmit through a category 5 channel the more work we need to do to counteract the system's vulnerability to bit enors.
  • the Channel Equalization Section and Channel Measurement & Calibration Section address these issues.
  • a 4-level PAM-5 signal has voltage transitions every 2 bit periods while a binary (2 level) signal could have voltage transitions every bit period. Therefore, the rate of transitions, or symbol rate, of a 4-level signal PAM-5 is half the frequency of a binary signal.
  • a 250 Mb/s data signal (PAM-5) can be transmitted at a rate of 125 Msymbols/sec using 125 MHz of channel bandwidth with only 4 voltage levels.
  • a 8 level signal (SPAM-5) is a 500Mb/s data signal, is transmitted at a rate of 125 Msymbol/s using 125 MHz of channel bandwidth with only 8 voltage levels.
  • the 5 th level in the PAM-5 system or 9 th level of the SPAM-5 system allows for redundant symbol states that are used for enor-conection encoding.
  • the enor conection method includes Trellis coding [9] in combination with Viterbi decoding.
  • the enor conection logic further enhances the system's Signal to Noise Ratio (SNR) margin by up to 6 dB.
  • SNR Signal to Noise Ratio
  • the extra 6 dB of SNR margin gives the 5 level PAM-5 signal the noise immunity of a 3 level signal.
  • the PAM- 5 signal also incorporates enor conection coding to improve the BER performance of the system. The same applies for SPAM-5 with 9 signal levels.
  • the spectmm of the PAM-5 and SPAM-5 transceivers closely resemble that of a 100 Base-T MLT-3 transceiver facilitating a design that would use 100 Base-T magnetic allowing the design of a scaleable 100/ 1000/2000 Base-T device.
  • Digital signal modulation in general, transforms input digital signals into waveforms that are compatible with the nature of the communication channel medium. Through modulation, baseband communication channel signals are modified to carry the desired information.
  • the SPAM-5 Modulator (327) and Demodulator (332), as illustrated in figure 56, are the methods of delivering baseband digital signal modulation that uses a variation in the amplitude and phase of the carrier to transmit information. The phase variation is accomplished with the Phase Modulation technique and the amplitude variation is performed with the Pulse Amplitude Modulation (PAM-5) technique.
  • the SPAM-5 signal modulation is a unique and advanced baseband modulation technique that conveys multiple (4) bits of information simultaneously (at 125 Mbaud Symbol Rate) by providing multiple states in each symbol of transmitted information. Each time the number of states per symbol increases, the bandwidth efficiency also increases. This bandwidth efficiency is measured in bits per second per Hz.
  • the standard lOOOBase-T signal operates on the same frequency band as the 100Base-T square wave digital signal with all of the above offsets and delays.
  • the new 2000Base-T SPAM-5 is also an amplitude modulation coded signal that operates on a baseband signal frequency of 125 MHz. This is similar to a PAM duo-binary and partial channel response-coding scheme.
  • lOOOBaseT is in effect allows 5 bit of PAM5 (4 information and 1 enor conection bits) times higher in bit rates over a 1 hertz operating frequency range with the optimal bit enor rates. In effect, 2 amplitude levels for the Quinary symbol rate are decoded on each transition of the 125 Mbaud symbol rate.
  • the fransmitting and receiving of the new 2000Base-T SPAM-5 are also baseband signals.
  • the SPAM-5 signals (Partial Response PAM-5) modulated by a 125 MHz clock rate that is modulo-2 added to the PAM-5 modulated data A, to form the A+B composite data signal AB.
  • This signal AB still maintains the baud rate of 125 Mbaud.
  • the phase shift signal B is maintained via a precision source of reference and frequency/phase controls which are addressed in details by the Clock Transfer Technology section.
  • the SPAM-5 in general is explained as a multi-level baseband signal which is the composite signal from the two multi-level I axis and multi-level R axis baseband signals.
  • the R axis signal is the rotated (multiple of) 90 degrees in phase with the I version signal.
  • SPAM-5 can be thought of as an emulated baseband version of CAP- 1024 signal with the precision confrol of DC frequency point for maintaining the symmetry properties.
  • the SPAM-5 (Partial Response PAM-5) Modulator and Demodulator, as shown in figure 56, are responsible for maintaining the system within the required FCC Spectmm and Amplitude signal modulation limitations for sending and receiving data over the 4 twisted pair wires.
  • SPAM-5 Baseband Digital modulation transforms input digital signals into waveforms that are compatible with the nature of the baseband communications channel that are used to carry the desired information.
  • the SPAM-5 Partial Response PAM-5) Modulator (327) and Demodulator (332) , as shown in figure 56, implement a method of delivering digital signal modulation that uses variations in amplitude and phase of the carrier to transport information.
  • the phase variation is accomplished through precision control of the multiple of 90-degree phase offset and the 5 level amplitude variation is accomplished through Pulse Amplitude Modulation (PAM-5).
  • the Com2000TM baseband SPAM-5 signaling technique is a simple yet advanced baseband modulation scheme that conveys multiple (4) bits of information in a full duplex scheme (at 125 Mbaud Symbol Rate) for each cable pair.
  • Synchronous Pulse Amplitude Modulation increases the number of states per symbol.
  • Each of the SPAM-5 states are defined as a specific amplitude and phase. This means that the generation and detection of symbols is more complex than a simple phase detection or amplitude detection device.
  • the Com2000TM Partial Response PAM or baseband SPAM-5 Modulator (327) delivers high bandwidth efficiency through the transmission of 4 bits per second per Hz.
  • the Com2000TM baseband SPAM-5 Modulator (327) in the Electrical Transmitter section of the transceiver adds a channel PN coding training preamble header to the data sfream in such a way as to minimize the effects of noise and interference in the CAT5 communication channel.
  • the channel PN coding fraining symbol adds extra bits to the input data stream and removes redundant ones. The added bits are used for enor conection or to send specific system training sequences for identification or equalization. This can make synchronization (or finding the symbol clock) easier for the Com2000TM SPAM-5 Demodulator (332) of the Electrical Receiver.
  • the symbol clock frequency represents the exact timing of the transmission of the individual symbols.
  • the reciprocal of this is the symbol clock frequency of 125 Mbaud.
  • the symbol clock phase can be resolved up to 1/8 of the received carrier signal phase and is conect when the symbol clock is aligned with the optimum instant(s) (2ns and 6ns relative to the beginning of the baud period) to detect the symbols.
  • This feature is uniquely impacting on the convergence of the front end filters such as Feed Forward Filter (FFE), Decision Feedback Filter (DFE), ECHO and Near End Cross Talk (NEXT) canceller filters.
  • FFE Feed Forward Filter
  • DFE Decision Feedback Filter
  • NEXT Near End Cross Talk
  • Additional FSFE-DPIC filters was invented to capitalized on the crosstalk and noise that has the cyclostationary phase offset properties, to enhance the additional 6dB signal to noise ratio (SNR) which requires for the 2Gb/s Multi-Channel signal coding SPAM-5.
  • SNR signal to noise ratio
  • the UniNet Com2000 t family of technologies provides a "Columbus Project" system with a method that measures the channel, codes a new signal by precisely controlling the signal's parameters, and then adjusts the signal to eliminate distortions arising from the increased data throughput made possible by the improved signal.
  • the improved signal is both scaleable and secure by employing proprietary coding systems that take advantage of this more precise control as shown in figure 09..
  • the technology is responsible to produce carrier, carrier phase, symbol timing, sampling phase synchronous vector processing receiver and other derived clock signals.
  • UniNet uses a plesiochronous mechanism for obtaining bit synchronization, i.e., the clock is derived in the combination of the RN reference tone and the preample training data synchronization stream for equalizers. It is in the header of each data burst.
  • Typical Clock and Timing Recover system is used in Cable modem, xDSL or any other public referenced design information.
  • the Com2000TM Precision Sampling System comprises a method for precisely positioning the phase and time sampling and measurement windows at the center of the Eye Diagram with minimal enor for any deploying signal coding scheme, as illustrated in the figure 09.
  • this signal precision sampling scheme can be any or combination of TDMA, CDMA as Frequency Hop, CDMA as Direct Sequence, and FDM.
  • This system relies on the complete frequency, phase and time synchronization of one or more network nodes, preferably accomplished using the Clock Transfer and Measurement & Calibration systems, to have the carrier, symbol timing, sampling and other timing at the receiver are fully recovered.
  • the clock synchronization can be either relative or absolute and is used as one improvement to deliver a multitude of benefits, such as bandwidth and SNR improvements, ISI suppression and more data bits per frame. This technique is also supporting other possible measurements for Channel Jitter Suppression and Measurement Technologies.
  • the filtered received signal must first be sampled at the proper sampling instants.
  • FIR finite impulse response filter
  • the decision delay must be pre-determined (This is done by FFE/DFE with DPIC and Delay circuits). The optimization of the sampling instants and DFE decision delay is refereed to as the "Precision Sampling”. In the determination of Precision Sampling approach, the "Sampling Delay” and the “Sampling Phase” are need to be determined.
  • the "Sampling Delay” is obtained using the Propagation delay measurements (CPR) of the Com2000 Measurement and Calibration technology and time-conelation between the sequence of the received signal samples and the transmitted training sequence for sub-carrier phase cycle or delay enors.
  • the "Sampling Phase” is obtained from the Clock Transfer using the Enor Vector Measurement or EVM method or can also be derived from FFE/DFE/DPIC filter coefficients and Delay Circuits.
  • the sampling instant or "Precision Sampling” is the sum of the "Sampling Delay” and the "Sampling Phase". It is important to optimize both of the Precision Sampling and the Decision Delays.
  • the Com2000TM Coherent Clock Phase and Carrier Recovery Circuits allows the Precision Sampling Technology to sample the receiving signal with a predefined phase enor for a extend period of time. This is due to the fact that the crystal frequency drift and phase noise and jitter are less than the jitter caused by the VCO oscillator of the PLL circuits. This feature, therefore, also allows the increasing of the message size or number of data bits per packet load to be sent across a wireless communication channel such as TDMA packet. Through the Com2000TM Coherent Clock Phase and Carrier Recovery Circuits, the recovered carrier frequency remain a clean locked for more than 5x of the normal PLL lock.
  • the Com2000TM Precision Sampling Techniques provides both an SNR improvement while also providing a method and means for maintaining the receiving signal phase and frequency much longer (5x) over the conventional PLL/NCO lock loops, as illustrated in figure 57.
  • the precision sampling system uses the Coherent Clock Phase and Carrier Recovery Circuits to maintain the carrier signal phase and frequency.
  • the Coherent Clock Phase and Carrier Recovery circuits uses the quality crystal frequency and phases rather than the VCO frequency and phases.
  • the long term drift of the crystal are bounded by the Clock Transfer Technology with reference to the extreme stable source.
  • the short drift of the crystal are also bounded by the crystal short term drift criteria instead of the VCO short term drift. This is roughly 100 times worst than the crystal version.
  • the carrier signal regeneration is also a much cleaner signal with less jitter.
  • the Com2000TM Coherent Clock Phase and Carrier Recovery Circuits allows the increasing of the message size or number of data bits per packet load to be sent across a communication channel such as Ethernet packet.
  • the recovered carrier frequency remain a clean locked for more than 5x of the normal PLL lock. It is therefore, as an example for Ethernet, the new packet size can be roughly 5x of the normal Ethernet size (1500 bytes), should this capability is exercised.
  • Static Position Enor or Jitter is caused by the enor associated with the signal sampling accuracy or the proximity of the timing pulse to the optimum sampling point or to the center of the eye.
  • the Com2000TM Precision Sampling uses a combination of technologies, such as Channel Calibration and Measurement system (and Measurements circuits 330, 343 as shown in Fig.56) and Precision Sampling system, for placing the sampling window within a specified tolerance of the center
  • the Com2000TM Post Equalizer signal delivers a clean and wide-open eye diagram.
  • a Non- Linear Estimator such as a multi-level Quantiser M-PAM or M-QAM Demodulator (74) accurate to a level of Ins , therefore the Com2000TM can allow more symbols per baud on the existing N Mbaud symbol rate.
  • TS time-slots
  • the frame can be further divided into two sections: downstream (from Reference Node, RN to other regular Nodes) and Upstream (from regular Nodes to RN) as shown in Figure 59.
  • the boundary between 2 sections is movable and can be changed from one frame to another by the RN based on the DCA.
  • the EMPTY ZONE occupies a number of Time-Slots (nTS) sufficient to cover the twice the longest distance in time between the RN and a regular Node. The reason for this zone will be explained later in Section 5 on Ranging.
  • the TDMA frame structure discussed in Figure 59 is actually a TDMA/TDD (Time Division Duplexing) structure.
  • the downstream is for point to multiple points while the upstream is for multiple points to point.
  • Each TS can accommodate one burst and a burst contains the pre-amble and cell as shown in Figure 60 below.
  • Figure 60 only illustrates an example for discussions. We will need more investigations to design the detailed structures of the Burst and Cell 1 .
  • the pre-amble consists of:
  • ⁇ G guard time (i.e., no Tx, idle) to avoid overlapping of two consecutive bursts (Its length is therefore derived to cover the "quantization" enor in ranging as discussed later)
  • ⁇ UW unique word to identify the beginning of the burst. The UW of the reference node (to be discussed later) is used by the Rx Framer to identify the frame marker, and
  • ⁇ T training pattern to adjust the frequency (if sent by the reference node) or to adjust the phase/timing (if sent by a regular node).
  • the cell contains a header (H) and a payload.
  • the N time-slots, TS#1 to TS#N, are shared by all nodes.
  • the transmission in a particular TS is coordinated by the primary reference node (RN).
  • RN primary reference node
  • the secondary RN becomes the active RN only when the primary RN fails.
  • the time relationship described above is shown in Figure 61 below.
  • Node #A needs only one parameter D A .
  • the RN has to perform ranging during the initialization or re-configuration for a newly entering Node #A in the following sequence.
  • (a) RN sends a request in its Reference Burst to ask Node A to transmit a probing burst.
  • the RN does not know the "time" distance between itself and Node A and we do not want that the probing burst of Node A collides an active burst of another Node or of the RN.
  • no Node is allowed to send its burst before completely receiving the end of the downstream section. This is the reason for the EMPTY ZONEin Figure 59. This zone appears to be equivalent to 2T ma ⁇ where T max is the longest "time" distance between the RN and a regular Node 3 .
  • the RN can keep the first time-slot after the EMPTY ZONE to assign it to the newly entering Node A to send its Probing burst.
  • Node A has to establish the Rx Frame Marker in order to receive the cells. It then receives the command from the RN and prepares to send its probing burst. For this, the Node A waits
  • the Frame Marker can be equivalently denoted by the position of the RUW since the Node performs UW detector to de ⁇ ve the Frame Marker
  • the Tx Framer receives the Rx Frame Marker and Rx Frame Sync status signals from the Rx Framer. It also receives the Tx allocated time-slot numbers from the Dynamic Capacity Allocation block. From these inputs, the Tx Framer generates the gating signals to control the transmission of the Burst-Mode Modulator.
  • FIG 63 shows the block diagram of the Rx Formatter. Its functions are:
  • RRx Data passed to the UW Detector and the Phase Ambiguity Remover.
  • the UW Detector is in the open search mode. It looks everywhere for the reference UW position. When a pattern recognized as the reference UW is first detected, the UW Detector changes to the tracking mode by generating the timing window signal to focus on the expected position of the reference UW. If X consecutive reference UW's are detected (within the expected window), then the UW Detector declares that Rx Frame Sync is established and maintains the tracking mode. Otherwise, it has to come back to the open search mode. This iterative process can be done for up to Y iterations. After Y times, if the Rx Frame Sync can not be established then alarm must be generated. Note that in the open search mode, all data are considered, therefore false alarm (i.e., reference UW is not there but some data pattern looks identical) may happen often. To improve the performance, we only declare a UW detected if the pattern is 100% identical.
  • the node already knew the vicinity of the UW, hence the confrol signal provides only a nanow window for UW detection in order to reduce the false detection probability.
  • a pattern of L bits is declared to be a UW if there are M ⁇ L identical bits. M ⁇ L to cover the case of bits in enor due to noise. We need a short analysis 5 to determine M, L.
  • UniNetTM is an effort to deliver a high capacity network with packet/circuit switched transport with an integrated service environment, as illustrated in figure 02. 2.2.1 Protocols Transfer Environment : Protocol Sync Circuit Switching Tech
  • IP Internet Protocol
  • Best-effort IP allows the complexity to stay in the end-hosts, so the network can remain relatively simple [e2e]. This scales well, as evidenced by the ability of the Internet to support its phenomenal growth. As more hosts are connected, network service demands eventually exceed capacity, but service is not denied. Instead it degrades gracefully. Although the resulting variability in delivery delays (jitter) and packet loss do not adversely affect typical Internet applications—email, file transfer and Web applications — other applications cannot adapt to inconsistent service levels. Delivery delays cause problems for applications with realtime requirements, such as those that deliver multimedia, the most demanding of which are two-way applications like telephony.
  • IP services must be supplemented. This requires adding some "smarts" to the net to distinguish traffic with strict timing requirements from those that can tolerate delay, jitter and loss. That is what Quality of Service (QoS) protocols are designed to do. QoS does not create bandwidth, but manages it so it is used more effectively to meet the wide range or application requirements. The goal of QoS is to provide some level of predictability and control beyond the cunent IP "best-effort" service.
  • QoS Quality of Service
  • QoS Quality of Service
  • a network element e.g. an application, a host or a router
  • Some applications are more stringent about their QoS requirements than others, and for this reason (among others) we have two basic types of QoS available, as illustrated in figure 64:
  • Resource reservation integrated services: network resources are apportioned according to an application's QoS request, and subject to bandwidth management policy.
  • Prioritization differentiated services: network traffic is classified and apportioned network resources according to bandwidth management policy criteria. To enable QoS, network elements give preferential treatment to classifications identified as having more demanding requirements. These types of QoS can be applied to individual application "flows" or to flow aggregates, hence there are two other ways to characterize types of QoS:
  • a "flow” is defined as an individual, uni-directional, data stream between two applications (sender and receiver), uniquely identified by a 5-tuple (transport protocol, source address, source port number, destination address, and destination port number).
  • Per Aggregate An aggregate is simply two or more flows. Typically the flows will have something in common (e.g. any one or more of the 5-tuple parameters, a label or a priority number, or perhaps some authentication information). Unlike circuit-switched networks, a pure connection-less packet-switched network, as illustrated in figure 64 and 65, cannot in itself provide real-time guarantees. This is mainly due to dynamic buffering and that nodes send data into the network at uncontrolled rates. One way to provide services with real-time guarantees is to let applications reserve network resources before they transfer their data. Applications, network topology and policy dictate which type of QoS is most appropriate for individual flows or aggregates. To accommodate the need for these different types of QoS, there are a number of different QoS protocols and algorithms:
  • RSVP Resource Reservation Protocol
  • Integrated Services Provides the signaling to enable network resource reservation (otherwise known as Integrated Services).
  • RSVP is also used to reserve resources for aggregates (as we describe in our examination of QoS architectures).
  • routers inside the network must implement schemes to actually support resource reservation, e.g., buffer allocation and queueing/ policies.
  • DiffServ Differentiated Services
  • MPLS Multi Protocol Labeling Switching
  • Subnet Bandwidth Management Enables categorization and prioritization at Layer 2 (the data-link layer in the OSI model) on shared and switched IEEE 802 networks.
  • a connection-oriented packet-switched network for instance an ATM network, as illusfrated in figure 07 and 02, resources are reserved when connections are created. If the network cannot allocate the requested resources, the sender is either blocked or offered a lower service quality.
  • This admission control is based on a traffic description from the sender that describes for example the average bitrate, the peak rate, largest burst, etc.
  • policing and shaping functions such as leaky bucket schemes, are needed to ensure that senders do not exceed the re-sources they have reserved.
  • leaky bucket schemes In a simple leaky bucket scheme, data is put in a queue, the bucket, and at regular intervals, data is taken from the queue and put onto the medium.
  • Tokens (the right to send data onto the medium) are put with a specified rate in a bucket. If no data is sent, tokens will gather in the token bucket. If a burst of data then arrives, data can be sent as long as there are tokens in the bucket.
  • One problem with this scheme is that a token bucket may release all its tokens at once in one burst. If several senders do this simultaneously, there is a risk that much data will arrive simultaneously at switch points in the network, as illustrated in figure 65. To prevent that congestion occurs, many resources have to be reserved for each connection, which may reduce utilization.
  • This effect can be limited by using a leaky bucket that ensures smooth-ness following the token bucket .
  • This leaky bucket mechanism is Sometimes called a spacer, since it separates packets with a space.
  • Queuing policies can be used to provide different services. Typically, packets belonging to different fraffic classes are put in separate queues in the network with priority given to the queues with real-time traffic. Instead of using simple first in first out (FIFO) schemes for these queues, other more suitable scheduling schemes for providing service guarantees can be applied, such as Earliest Due Date (EDD), Weighted Fair Queuing (WFQ), etc.
  • EDD Earliest Due Date
  • WFQ Weighted Fair Queuing
  • the delay bounds provided by WFQ tend to become long since they are based on the worst case. It is shown that by applying schemes that make use of statistical multiplexing, it is possible to provide statistical delay bound guarantees — the probability that all packets are delivered within a given delay bound is high. This statistical delay bound is much shorter than what is provided by WFQ.
  • the cunent "Soft QoS” or Best Effort QoS standards for Ethernet such as IEEE 802.1P & 802. IQ for layer 2 and MPLS, RSVP for layer 3 &4 are only the emulation of the ATM "QoS" for IP networks at the upper layers and are cunently implemented in software by many network core equipment manufacturers within LAN/WAN Switching Hubs and Routers by CISCO, 3COM and Bay Networks.
  • Com2000TM QoS is "Hard QoS" or Guaranteed QoS for UniNet networks, as shown in figure 06 and 07.
  • Com2000TM QoS can fundamentally be interpreted as a universal transport QoS mechanism for integrated services, as illustrated in figure 02, that seamlessly maps into and out of any new or cunent and legacy data com and telecom protocols and QoS services. These protocols include ATM, SONET, Frame Relay, and Tl/El,etc,. from the telecom services and IP networking protocols such as TCP/UDP from data communications.
  • this universal transport Com2000TM QoS mapping or Fast Protocol Synchronous Circuit Switching which is anything over anything transport mechanism such as IP over ATM, IP over SONET, ATM over IP, ATM over SONET, PPP over SONET, ..etc. is applicable to all protocols from a very stringent synchronous services such as SONET, loosely isochronous services such as ATM and Frame Relay, etc, to a very loosely and best effort asynchronous data services such as Internet IP protocols.
  • the following paragraphs describe the Com2000TM QoS Control enabling technology for seamless LAN/WAN Data Communication and Telecommunication systems integration, as shown in figure 02.
  • This allows the Ethernet Signaling to have the predictable latency confrols and nature as of the SONET (Synchronous Services) or ATM (Isochronous Services) networks.
  • the Com2000TM program incorporates lessons learned in the data communications bandwidth confrol and efficiency requirements.
  • the design of the Com2000TM QoS product for Internet QoS are primarily in the area of enabling SONET/ATM like QoS over IP Ethernet Signaling, protocols, improving network throughput of existing data communication channels and its challenges of Internet, Intranet and Extranet infrastmcture equipment, long haul WAN network equipment and Telecommunications equipments.
  • the WAN SONET Synchronous Services
  • IP Ethernet networks or SOHO networks can deliver a equivalent of SONET (Synchronous Services) or ATM (Isochronous Services) network Quality of Services at the physical layer such as latency controls, propagation delay confrols, and predictable nature of the networks.
  • UniNetTM Centralized switches are likely to become bottlenecks in packet or circuit switching networks when the edge of the network's transmission capacity is increased.
  • UniNetTM therefore uses a distributed switching scheme based on the shared medium to avoid the switch bottle-neck.
  • a shared medium network such as a UniNetTM bus, as shown in figure 06, does not normally use a physical switch. Instead, the shared link itself implements the switch, where a node's attachment to the link can be seen as a switch port. This reduces the amount of data that must be passed through switch nodes, but still data has to be switched when passed from one medium to another.
  • UniNetTM implements a Per Request Burst Switching Scheme with built-in Synchronous Switching Intelligence
  • the concept derived from the lesson learned of the packet based and circuit based switching networks and the wish of defining the most optimized way for data delivery at the edge of the network which seamlessly interoperable with the backbone, as illustrated in figure 02.
  • the UniNetTM Synchronous Switching can be used as the universal transport and can be able to map in and out of legacy IP, ATM,..etc switching with the most optimized way. It benefits is also derived from the shared medium topology and the synchronous TDM cell message scheme of the UniNetTM.
  • a cluster of UniNetTM switch elements form a high-capacity switch node, as shown in the figure 06.
  • Several switch elements are then connected to the same buses and switch a portion each of the total amount of data.
  • the internal switching capacity of one switch element can be quite modest (much less than the transmitted capacity on the copper) and designed to be cost- effective. Even though several UniNetTM switch elements form a switch cluster, the added switching delay continues to come merely from the one switching element that does the actual switching.
  • This scheme can be used both in a single- or a multi-stream environment, and the distribution granularity of switching capacity (i.e., the number of slots to switch) among the switch elements can be set according to performance and demand.
  • the distribution can either be set up initially, e.g., by starting with a range of slot numbers or a bitstream each, or dynamically through signaling on a per channel basis.
  • traffic may also be rerouted using the other switch elements.
  • the UniNetTM Network deliver the IP over TDM signaling for Voice network, Voice over IP and other services in the private network environment.
  • the distributed networking process functions and IP switching fabric, as shown in figure 64, is now handle by each of the UniNetTM element in the network as shown in figure 06.
  • This distributed intelligence and processing on the TDM signaling enable this network to be deterministic as the Circuit Switching and as flexible as the Packet Switching.
  • the UniNetTM networks deliver the real-time voice quality as the telecom TDM backbone. When it communicate with the IP/TDM switching in the backbone, as shown in figure 02, it will assemble the IP Packet in the same manner as Internet Protocol requires, and tag them with appropriate IP QoS flag and send out to the IP networks.
  • the UniNetTM also can its own QoS scheme into the ATM QoS and send it out over the xDSL access as also shown in figure 02.
  • Today's network architecture consists of three main elements: Hosts (H), LAN Switches (S), and Routers (R).
  • the Hosts are a collection of computer systems that execute network applications.
  • the LAN Switches are the network elements that provide communication between hosts within a LAN.
  • the Routers are the network elements that provide interconnection between LANs. Routers are also used to provide interconnection between routing domains 6 .
  • the main functionality of a switch is to forward packets among hosts and between hosts and a router.
  • the main functionality of a router is to route packets. Routing packets involves route selection (using routing protocols) and packet forwarding (using forwarding engines).
  • Today's network architecture is designed to support the delivery of best-effort traffic.
  • the network elements In order to support the delivery of QoS traffic, the network elements (switches and routers) must also support packet policing and shaping. This means in order to support end-to-end QoS network solutions, LAN switches must support forwarding and policing and shaping, whereas routers must support forwarding, policing and shaping, and routing.
  • circuit-switched Telecom
  • packet-switched Data Communications
  • Routing Domain is a collection of several LANs that are interconnected by Routers. packet switching such as ATM) because resources could not be allocated in the network. The data then has to be buffered at the sender until resources can be allocated. Data may also have to be buffered at the sender if the rate of the generated data temporarily exceeds the circuit rate, for example during a data burst.
  • packet switching such as ATM
  • Co ⁇ -2000 Per Request Burst switching (Fast Data Synchronous Circuit Switching Tech ) is a new form of circuit switching and also is the extension of SONET Fiber backbone Circuit Switching that applies into the Edge of the wireless and wireline networks and also seamless integrated into the existing SONET networks and interoperable with data communication and telecom legacy protocols, as shown in figure 02.
  • a burst (consisting of a header, an arbitrary amount of data and a termination character) is sent in a time-division (TDM) channel of fixed bit-rate and is thus interleaved with other bursts.
  • TDM time-division
  • ATM fast packet switching
  • Com2000 or UniNet burst switching differs from other burst switching in that control and data are separated and it uses multicast, multi-rate, high capacity channels in order to support a variety of different traffic classes with a dynamically bandwidth allocation scheme or DCA.
  • a UniNetTM user generates data at many different rates depending on the end equipment and the applications. The user therefore needs a network that can handle data at multiple rates.
  • the UniNetTM Per Request Burst switching networks can handle TDM such as the telephone network only provide fixed bitrate service and also much more bandwidth flexible (via the Dynamic Bandwidth Allocation Scheme) to handle Packet-switched networks, as they provide an asynchronous service, where a node can send data as long as the link has free resources. This often means that the problem of networks which either the circuit provides insufficient capacity, or the capacity may be inefficiently used are overcomed with The UniNetTM Per Request Burst switching networks.
  • the "UniNetTM Regulator (R)” is the collection of external Ethernet interface multi-port "UniNetTM Ethernet” PHY which, in turn, interconnect with each other in a high speed bus, acting as the fabric switch engine, via the UniNetTM PHY and that has all of the intelligence of the Traffic Management as shown in the figure 65.
  • the regulator is designed as part of the Host (H) transceiver at the Physical Layer to police the traffic, routing and forward packets to Synchronous Bus Ethernet protocols. (Distributed Routing & Switching)
  • the ultra high speed bandwidth and network element intelligence such as the fast digital synchronous circuit switching fabric intelligence, which performs the tasks such as fragmentation/defragmentation of the received packet based into Cell based for QoS controls and other network element intelligence such as the Switching/Router Functional intelligence , which performs for tasks such as addressing, switching, routing, policing and shaping, sequencing and flow confrols for each switching node , can be migrate to the edge node systems or Com.2000TM PHY in this case.
  • the network connection between the end node(s) and the core node is just the extension of the "QoS" switching fabric.
  • Distributed Routing and switching techniques enable internet processor to regulate the data flow and controls (Distributed Switching & Routing via Advanced Synchronous Switching Transfer Techniques).
  • Multicast In Distributed multimedia applications often use multicast distribution of data, i.e., sending the same data to several receivers. So far, multicast has been used mostly for network control and management, but multimedia applications use it for data distribution as well. This, in combination with distribution of information in the public network, such as distribution of TV, public information and advertising means that efficient multicast is important in future networks.
  • Efficient multicast capability in a network depends on whether a shared medium or point-to- point links are used, i.e. on the topology.
  • a shared medium such as a bus or a ring, has the advantage that several nodes can read the same information.
  • multicast data has to be replicated in switch points. Multicast is supported both in the Internet and in ATM networks, even though a complete multicast standard has not yet been defined in ATM.
  • a multicast routing algorithm including a group membership protocol that is used for routers and switches to learn the existence of new members.
  • Copying of data messages is often implemented in ATM switches by special copy networks that are used for the duplication of cells.
  • a con-sequence of this is that resources have to be reserved on several links, which may complicate resource reservation.
  • An issue with multicast in large, wide-area networks is scaling. There are three main costs associated with multicast algorithms in large networks.
  • the number of table entries within routers/switches tend to become very large and should be minimized. Only the entries that are actually used must be resident within the router/switch.
  • the amount of confrol in-formation that is sent between nodes to update routing and membership in-formation needs to be kept low. Broadcast of information should be avoided. At the same time, it is important that new information efficiently and swiftly will be sent to concerned parties.
  • multicast data should only be sent on links that lead to receivers, and it is preferable that data is replicated as close to the receivers as possible to reuse link capacity. Another major factor is the processing cost of computing delivery paths for all active multicast sources.
  • Centralized switches are likely to become bottlenecks in legacy networks where the transmission capacity is increased.
  • Fast Synchronous CircuitSwitching therefore uses a distributed switching scheme based on the «hared medium to avoid the switch bottle-neck.
  • a shared medium network such as a UniNet bus, does not normally use a separate physical switch device. Instead, the shared link itself implements the switch, where a node's attachment to the link can be seen as a switch port. This reduces the amount of data that must be passed through switch nodes, but still data has to be switched when passed from one medium to another.
  • UniNet therefore also implements a modular switching scheme based on benefits from the shared medium topology and the synchronous TDM scheme in UniNet Systems.
  • a cluster of switch elements form a high-capacity switch node.
  • Several switch elements are then connected to the same buses and switch a portion each of the total amount of data.
  • the internal switching capacity of one switch element can be quite modest (much less than the transmitted capacity on the copper channel) and designed to be cost-effective. Even though several switch elements form a switch cluster, the added switching delay continues to come merely from the one switching element that does the actual switching.
  • This scheme can be used both in a single- or a multi-stream environment, and the distribution granularity of switching capacity (i.e., the number of slots to switch) among the switch elements can be set according to performance and demand.
  • the distribution can either be set up initially, e.g., by starting with a range of slot numbers or a bitstream each, or dynamically through signalling on a per channel basis. In the case of failure of one switch element in the logical switch, traffic may also be rerouted using the other switch elements.
  • Circuit-switched networks provide a simple data transfer without processing of the data stream, congestion control, etc. This allows large volumes of data to be transfened efficiently.
  • the main limiting factors in packet-switched networks are traffic confrol mechanisms and the data manipulation capability of network components, such as routers and switches.
  • cunent packet-switched networks can support Gbit/s bitrates
  • the data transfer capacity in circuit-switched networks are primarily limited by the high-speed electronics in media access parts.
  • one important factor in circuit-switched networks that does not directly affect the data transfer rate but determines much of the utilization of network resources is the signaling delay associated with creation and tear-down of circuits.
  • Increased network capacity can either be achieved by raising the bitrate of the link or by sending several bitstreams in parallel. This is independent of the choice of packet switching or circuit switching, even most parallel systems give a circuit-switched service.
  • Increasing the number of parallel bitstreams in the network seems a promising technique to obtain high capacity in a cost-efficient way, since it makes it possible to increase transmission capacity without increasing the speed of electrical components in the network. These components will only operate at the speed of a single bitstream, while the total amount of data on the copper channel can be much larger.
  • Parallel bitstreams can be achieved by phase division multiplexing (PDM) techniques, or by space division multiplexing (SDM) with several virtual cables in parallel, as shown in figure 55.
  • PDM phase division multiplexing
  • SDM space division multiplexing
  • UniNet is designed for a shared medium topology. This facilitates distributed switching, avoiding large cenfral capacity in a cost-efficient way, since it makes it possible to increase transmission capacity without increasing the speed of electrical components in the network. These components will only operate at the speed of a single bitstream, while the total amount of data on the copper channel can be much larger.
  • the shared medium also has inherent multicast capability, i.e., the same data element can be read by several receivers. Furthermore, the shared medium provides a means for efficient sharing of resources.
  • Nodes access fibers according to a Time Division Multiplexing (TDM) scheme using 125 us cycles ( 20*6.25 us or 10 nodes in the UniNet network), as shown in figure 05, i.e., the same cycle duration as in current telephone networks. These cycles are further divided in 64-bit slots. A slot does not contain any headers or control bits. On the contrary, data and control are separated, and control information is sent in control slots and data in data slots. A slot is addressed through its number in the cycle.
  • TDM Time Division Multiplexing
  • UniNet provides a service based on multicast channels (or channels for short).
  • a UniNet channel is a set of slots in the cycle with a sender and an arbitrary number of receivers. Channels are synchronous, and can be seen as continuous streams of data from senders to receivers. When a host establishes a channel, it reserves resources for a data transfer with constant through-put and delay from sender to receiver.
  • the channel abstraction in UniNet differs from ordinary circuits in that channels are: Simplex, a channel is only set up from sender to receiver.
  • a duplex connection consists of two channels, one in each direction.
  • Multirate channels may be of variable size and are increased in steps of 512 kb/s (i.e., an additional slot per cycle).
  • Multicast a channel can have several receivers. Channels can be both sender and receiver initiated to accommodate efficient resource reservation, especially for group communication.
  • UniNet uses a strict dynamically resource reservation scheme, where a new connection is admitted only if there is enough free bandwidth and if a suitable route can be found. Once a channel is established, the user of the channel is guaranteed the reserved bandwidth until the channel is closed, which can be done at the period rate.
  • the UniNet network thus provides channel separation (i.e., fraffic on one channel does not disturb traffic on other channels). Since resources are allocated for each hop from sender to receiver, and since UniNet uses synchronous switching, there is a constant delay (low jitter) from sender to receiver. This also means that there can be no congestion in the network. There can still be overflow in slow receivers, so UniNet does not eliminate the need for end-to-end flow control
  • UniNet has been shown that the signalling delay associated with creation and tear-down of communication channels determines much of the efficiency of fast circuit-switched networks.
  • UniNet is therefore designed to create channels quickly, within a few hundred microseconds. Even though a UniNet network may have the potential to create a channel for every message, we do not believe this approach to be suitable for all traffic classes.
  • UniNet has been shown that the signalling delay associated with creation and tear-down of communication channels determines much of the efficiency of fast circuit-switched networks.
  • UniNet is therefore designed to create channels quickly, within a few hundred microseconds. Even though a UniNet network may have the potential to create a channel for every message, we do not believe this approach to be suitable for all traffic classes. Rather, it is the user's decision whether to establish a channel per information burst or to keep the channel established even during idle periods.
  • the UniNet network is designed for a unidirectional medium with multiple access, i.e., a medium shared by all connected nodes.
  • the UniNet protocols and medium access technique can, in principle, be used on several different topologies, such as ring, folded bus or dual bus. We have chosen the dual bus topology since it has a lower average inter-node distance than both a bus and a ring.
  • UniNet' s synchronization scheme is also easier to implement on a bus structure than on a ring. In an access network environment, where distances are short, a single bus or ring topology may be prefened to reduce copper access costs.
  • a UniNet network can be expanded by interconnecting several buses with switch nodes.
  • UniNet uses decentralized switching in the sense that any node connected to two or more buses can switch data between these.
  • One advantage of this is that the switching capacity can be increased gradually by adding more switch nodes.
  • a switch node can buffer one cycle of data for each of its buses, there cannot be any congestion or overflow in the node. Since the cycle time and the slot length is constant throughout the UniNet network, buses running at different bit rates can be connected to the same node and switching can be done between these buses. This makes it possible to update and increase the speed of parts of the network without forcing all nodes to
  • switch nodes allocate slots for a channel on behalf of the sender.
  • the switch nodes then start switching the channel, by copying the channel's slots from the incoming to the outgoing bus.
  • An attempt to establish a multi-hop channel fails if any of the switch nodes involved is unable to allocate the required amount of slots. In this case an-other route has to be tried.
  • crankback routing If an intermediate node cannot find an alternative path, a message is sent upsfream in the routing tree and nodes upstream are then responsible for trying other paths. This provides an exhaustive trial of all possible routes. Which path a node should try first can either be decided statically, i.e., paths are always tried in a certain order, or dynamically, i.e., the decision is made depending on the cunent status, for example the load on different links, which decides what path to try next. Within the UniNet prototype network, dynamic routing decisions are made based on a simple load-balancing scheme for two hops.
  • switch nodes use status messages to send information about the amount of free slots on their outgoing buses. For example, as shown in the figure 06, there are two possible routes between node 1 and node 4, so if node 1 wants to set up a connection to node 4 it can choose between using switch node 2 and switch node 3. Node 1 receives status information from node 2 and 3, and can make its routing decision based on this information. This algorithm works well for dense grid networks, where most routes use only two hops. In this case, the sender has decision is made depending on the cunent status, for example the load on different links.
  • the drawback with these algorithms is that each connection set-up may lead to an exhausted path search. This may result in increased signaling and, if resources are reserved without being used, decreased network utilization.
  • the UniNet protocol supports two address schemes, one with arbitrary ad-dresses and one where addresses (and nodes) are structured in geometric (x,y,z) coordinates.
  • the latter address scheme can, if the network is structured in a conesponding way, simplify routing. Similarities can be seen with the Manhattan Street Network that all full information of possible paths to the receiver and is responsible for finding the path. For more arbitrary topologies, variants of the sequential office control or the crankback algorithms are possible.
  • the routing algorithm does not use any routing tables, since the route can be determined from the address coordinates. In case a link is blocked, the packet is deflected.
  • a traditional circuit is a point-to-point connection between a sender and a receiver.
  • UniNet uses a shared medium which uses a structured network topology to simplify routing.
  • a Manhattan Street Network is based on a fully connected two-dimensional grid.
  • the routing algorithm does not use any routing tables, since the route can be determined from the address coordinates. In case a link is blocked, the packet is deflected. Nodes may then have a cache of paths to different receivers. If a connection request arrives for an unknown receiver, a request is sent to the address consultant that returns a path to use.
  • a multicast channel can easily be extended to span over several hops, since the switch operation is actually a multicast operation, in the sense that it duplicates data onto another bus. Broadcast in the network, i.e. for distribution of TV, is an important feature. The problem with broadcast is to reach all nodes in the network and still avoid flooding the network with messages. A node should get one and only one copy of each message.
  • Each application such as in Video (Video Conference - TCP/IP) or Data (Email - UDP/IP ) or Voice (Tele- Conference RTP/UDP/IP) has the dedicated network connection such as IP addresses for different host nodes (Casel) or/and at different TCP ports addresses for the same host node that is hosting all of the 3 related applications (Case2).
  • IP addresses for different host nodes (Casel) or/and at different TCP ports addresses for the same host node that is hosting all of the 3 related applications (Case2).
  • DOCCIS 1.1 for cable modem of most home with digital cable internet access will be installed with this single IP address scenario (Case2).
  • xDSL for Telephone Digital Services allow more than one IP address for each of the access node (Casel).
  • Case 2 Techniques The synchronous environment between the sender and receiver allow new IP Time Slice related scheduling technique that improves the capacity at the upper layer along with the QoS that is needed to deliver a multimedia over the same best effort channel.
  • the IP TDM technique allows the application time share (TDM) the IP address in the most optimal manners. This can be interpreted as a IP virtual channels , as shown in figure 67c, for each of the applications. This will differentiate the real-time and non-real-time time sensitive data messages.
  • the sending and receiving applications will call new TCP/UDP/IP driver software or services with the IP TDM technique built in to deliver TDM multiplexing and demultiplexing in an optimal way.
  • Case 1 Techniques The synchronous environment between the sender and receiver allow new TCP Time Slice, as shown in figure 67b, related scheduling technique that improves the capacity at the upper layer along with the QoS that is needed to deliver a multimedia over the same best effort channel.
  • the TCP&UDP TDM technique allows the application time share (TDM) the TCP port address in the most optimal manners without hitting the TCP time out window. This can be interpreted as a TCP&UDP virtual channel for each of the applications. This will differentiate the real-time and non-real-time time sensitive data messages.
  • the sending and receiving applications will call new TCP/UDP/IP driver software or services with the IP TDM technique built in to deliver TDM multiplexing and demultiplexing in an optimal way, as shown in figure 67d.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Cette invention concerne un procédé permettant d'augmenter la largeur de bande des signaux entre des noeuds d'émission et de réception. Sur réception d'un signal de synchronisation, une logique de réglage fin d'horloge (161) synchronise les noeuds d'émission et de réception au moyen dudit signal. Une logique de mesure de canal (164) mesure la capacité du canal de communication. Une logique d'étalonnage (163) étalonne le canal de communication sur la base de relevés de capacité. Une logique d'échantillonnage de précision (165) échantillonne le signal d'horloge des noeuds. Un ajustement de phase est transmis aux noeuds lorsque un signal d'horloge échantillonné dépasse l'intervalle phase.
PCT/US2000/010101 1999-04-14 2000-04-14 Systeme de reseau synchrone universel pour processeur internet et environnement de fonctionnement internet WO2000062470A1 (fr)

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CA002370634A CA2370634A1 (fr) 1999-04-14 2000-04-14 Systeme de reseau synchrone universel pour processeur internet et environnement de fonctionnement internet
AU47990/00A AU4799000A (en) 1999-04-14 2000-04-14 Universal synchronous network system for internet processor and web operating environment
EP00930112A EP1173949A1 (fr) 1999-04-14 2000-04-14 Systeme de reseau synchrone universel pour processeur internet et environnement de fonctionnement internet

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US12931499P 1999-04-14 1999-04-14
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US09/417,528 US6553085B1 (en) 1997-07-31 1999-10-13 Means and method for increasing performance of interference-suppression based receivers
US09/417,528 1999-10-13
US44400799A 1999-11-19 1999-11-19
US09/444,007 1999-11-19
US17045599P 1999-12-13 1999-12-13
US60/170,455 1999-12-13
USPCT/US00/06842 2000-03-15
PCT/US2000/006842 WO2000062415A1 (fr) 1999-04-14 2000-03-15 Moyens et procede permettant d'ameliorer la performance des recepteurs a antiparasitage

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003009556A1 (fr) * 2001-07-18 2003-01-30 Massana Research Limited Egalisateur pour transmission de donnees multi-canaux
US7099385B2 (en) 2001-07-18 2006-08-29 Massana Research Limited Compensation for interference in data receivers
US7542485B2 (en) 2003-11-19 2009-06-02 Avaya, Inc. Time and data synchronization between network devices
EP2683163A1 (fr) * 2011-03-04 2014-01-08 Dentsu Inc. Système de distribution de radiodiffusion de contenu synchronisé
CN107947848A (zh) * 2017-11-16 2018-04-20 北京卫星信息工程研究所 基于IEEE 1588v2的卫星通信地面同步仿真系统及应用方法
KR20190052472A (ko) * 2017-11-08 2019-05-16 전자부품연구원 심볼간 간섭이 최소화된 pam-4 수신기
CN113126130A (zh) * 2021-03-25 2021-07-16 中国电子科技集团公司第五十四研究所 一种多层次深耦合的导航信号异常高精度监测方法
EP4016852A1 (fr) * 2020-12-17 2022-06-22 INTEL Corporation Réglage de la porteuse de débit en bauds en boucle fermée et de la fréquence de la porteuse pour une interface sans fil de type puce à puce
WO2023075061A3 (fr) * 2021-10-27 2023-06-22 전북대학교산학협력단 Système à antennes multiples en boucle fermée et procédé de sécurité de communication à antennes multiples en boucle fermée

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105991720B (zh) * 2015-02-13 2019-06-18 阿里巴巴集团控股有限公司 配置变更方法、设备及系统
CN111641470B (zh) * 2020-05-08 2022-08-02 哈尔滨工程大学 一种分布式仿真的时间一致性同步方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930267A (en) * 1996-05-17 1999-07-27 Lucent Technologies Inc. Frame synchronization for asynchronous transmission

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930267A (en) * 1996-05-17 1999-07-27 Lucent Technologies Inc. Frame synchronization for asynchronous transmission

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003009556A1 (fr) * 2001-07-18 2003-01-30 Massana Research Limited Egalisateur pour transmission de donnees multi-canaux
US7099385B2 (en) 2001-07-18 2006-08-29 Massana Research Limited Compensation for interference in data receivers
US7542485B2 (en) 2003-11-19 2009-06-02 Avaya, Inc. Time and data synchronization between network devices
EP2683163A1 (fr) * 2011-03-04 2014-01-08 Dentsu Inc. Système de distribution de radiodiffusion de contenu synchronisé
EP2683163A4 (fr) * 2011-03-04 2014-08-27 Dentsu Inc Système de distribution de radiodiffusion de contenu synchronisé
KR20190052472A (ko) * 2017-11-08 2019-05-16 전자부품연구원 심볼간 간섭이 최소화된 pam-4 수신기
KR102204355B1 (ko) * 2017-11-08 2021-01-18 한국전자기술연구원 심볼간 간섭이 최소화된 pam-4 수신기
CN107947848A (zh) * 2017-11-16 2018-04-20 北京卫星信息工程研究所 基于IEEE 1588v2的卫星通信地面同步仿真系统及应用方法
CN107947848B (zh) * 2017-11-16 2020-10-23 北京卫星信息工程研究所 基于IEEE 1588v2的卫星通信地面同步仿真系统及应用方法
EP4016852A1 (fr) * 2020-12-17 2022-06-22 INTEL Corporation Réglage de la porteuse de débit en bauds en boucle fermée et de la fréquence de la porteuse pour une interface sans fil de type puce à puce
CN113126130A (zh) * 2021-03-25 2021-07-16 中国电子科技集团公司第五十四研究所 一种多层次深耦合的导航信号异常高精度监测方法
WO2023075061A3 (fr) * 2021-10-27 2023-06-22 전북대학교산학협력단 Système à antennes multiples en boucle fermée et procédé de sécurité de communication à antennes multiples en boucle fermée

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