WO2000057404A1

WO2000057404A1 - Magnetic disk memory

Info

Publication number: WO2000057404A1
Application number: PCT/JP1999/001395
Authority: WO
Inventors: Takashi Hashimoto; Masaki Yoshinaga
Original assignee: Hitachi, Ltd.
Priority date: 1999-03-19
Filing date: 1999-03-19
Publication date: 2000-09-28

Abstract

A magnetic disk memory mounted thereon with a semiconductor integrated circuit device operated under a second voltage for applying a ground potential of a circuit to a disc-shaped magnetic storage medium and being kept at a positive potential at the free end of an arm to which an MR head is attached and centering around a first potential of the above circuit and under a third voltage kept at a negative potential, wherein the semiconductor integrated circuit device has built-in therein a bias circuit for biasing the above MR head to the vicinity of a voltage centering around the first voltage, and a lead amplifier which feedbacks a current slightly smaller than emitter currents of first and second amplifier transistors and kept in an opposite phase by using a current feedback circuit for supplying a read signal by the above MR head to the bases of the above first and second amplifier transistors and providing a capacitor between the emitters of the first and second amplifier transistors to receive their collector output signals, which reduces signal current components flowing into the above capacitor, and which receives output signals from the first and second amplifier transistors.

Description

Description Magnetic disk memory device Technical field

The present invention relates to a magnetic disk memory device. In particular, the present invention relates to a technology effective when an MR (magnetoresistive effect) element is used as a read head and the head circuit is provided on a suspension. Further, the present invention relates to a technology which is effective when used for a compound head using an inductive head as an MR head for reading and a writing head.

Background art

As a magnetic head device provided with a head circuit for controlling writing and reproduction on a suspension, there is Japanese Patent Application Laid-Open No. 3-257177. A head suspension of a hard disk device and a wiring integrated type are disclosed. For technology and COS (chip-on-suspension) technology, see Nikkei Business Publications, Nikkei Electronics, April 6, 1989, “Nikkei Electronics”, pp. 167-177. In the above-mentioned COS technology, it is indispensable to reduce the size and weight of electronic circuits including chips mounted for high-speed movement of the head. In other words, if the weight of the electronic circuit including the chip is large, the inertia moment of the arm on which the head is mounted becomes large, which acts to prevent the arm from moving at high speed.

Therefore, the present inventors have developed a magnetic disk memory device suitable for miniaturization and high-speed operation by devising a circuit for reducing the size and weight of an IC chip such as a read amplifier.

Therefore, the present invention provides a magnetic disk drive that realizes a compact and high-speed drive. It is intended to provide a memory device. Another object of the present invention is to provide a magnetic disk memory device that realizes operation up to high frequency with high sensitivity. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The outline of a typical invention disclosed in the present application is briefly described as follows. In other words, corresponding to the disk-shaped magnetic storage medium to which the first potential of the circuit is applied, the first potential of the circuit is centered on the end of the arm (the so-called suspension) attached to the MR head. A semiconductor integrated circuit device that operates at a second potential set to a positive potential and a third potential set at a negative potential. The semiconductor integrated circuit device is provided with the MR head with the first potential as a center voltage. A bias circuit that supplies a predetermined bias voltage to both ends of the MR head; first and second amplifying transistors whose signals read from both ends of the MR head are respectively supplied to a base; A capacitor provided between the emitters of the first and second width transistors to hold a DC bias supplied to both ends of the MR head and to flow a signal current;增 width transistor collection Receiving the output signal, the current having a phase opposite to that of the emitter current of the first and second amplifying transistors is returned by / j, and the signal current component flowing into the capacitor is fed back. A lead amplifier for obtaining an output signal from the collectors of the first and second wide transistors is built in. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a lead used in a magnetic disk memory device according to the present invention. FIG. 2 is a circuit diagram showing one embodiment,

FIG. 2 is a circuit diagram showing another embodiment of the lead amplifier used in the magnetic disk memory device according to the present invention,

FIG. 3 is a circuit diagram showing another embodiment of the lead amplifier used in the magnetic disk memory device according to the present invention.

FIG. 4 is a circuit diagram showing still another embodiment of the read amplifier used in the magnetic disk memory device according to the present invention.

FIG. 5 is a layout diagram of an embodiment of the resistance element used in the read amplifier according to the present invention,

FIG. 6 is a block diagram showing one embodiment of a hard disk drive according to the present invention.

FIG. 7 is a schematic configuration diagram showing one embodiment of a hard disk drive according to the present invention.

FIG. 8 is a schematic structural diagram of a main part showing one embodiment of a hard disk drive according to the present invention.

FIG. 9 is a schematic cross-sectional view showing one embodiment of a disk rotating mechanism in the magnetic disk memory device according to the present invention;

FIG. 10 is a partially sectional external view showing an embodiment of an M-inductive composite head used in the magnetic disk memory device according to the present invention. FIG. 11 is a magnetic disk memory according to the present invention. FIG. 2 is a plan view showing an example of a flexible wiring board used in the device,

FIG. 12 is a plan view showing an embodiment of an arm and a suspension section used in the magnetic disk memory device according to the present invention.

FIG. 13 is an external view showing an embodiment of the arm and suspension unit in the magnetic disk memory device according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 shows a configuration of a main part of a reading system of a magnetic disk memory device according to an embodiment of the present invention, together with a read amplifier. Each circuit element constituting the read amplifier is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The device power supply forms a positive power supply SEV CC supplied to the semiconductor integrated circuit device on which the read amplifier is mounted, a negative power supply mEV EE, and ¹ SEVMO supplied to the motor drive device.

A magnetic disk (hard disk) as a magnetic storage medium is rotated by a motor as a drive mechanism. The ground potential of the circuit (first potential of the circuit) GND is applied to the surface magnetic material of the magnetic disk via the rotating shaft of this motor. The application of the ground potential GND in this manner is performed by a color that is convenient for removing undesired charges accumulated on the rotating magnetic disk.

The MR head for reading (or the magnetoresistive effect head, the same applies hereinafter) is connected at one end to the ground potential GND of the circuit to prevent discharge from the disk, and has substantially the same potential. To be. When the ground potential GND of the circuit is applied to one end of the MR head in this way, the voltage at the other end is usually about 20 Ω in resistance of the MR head, and the bias current flowing through it is 1 O mA It is only about 0.2 V, which is very small.

In order to read signals up to a high frequency corresponding to the high storage density of the magnetic disk, it is necessary to extract the signals as voltage signals. The reason is to extract the current signal corresponding to the change in magnetoresistance from the MR head. In this case, the inductance ^ of the wire connecting the MR head and the read amplifier directly acts as described above to limit the extraction of the high-frequency signal. As described above, the following bias circuit is used to extract from the other end of the MR head as a ΔE signal corresponding to the magnetic storage information of the magnetic disk.

To both ends of the MR head, one end of a resistor R having a resistance value sufficiently higher than the above-described resistance value of the MR head is connected, and the other end is commonly connected and a circuit is provided. The ground potential GND (0 V) is applied. Thereby, ΔE at both ends of the MR head is set to a minute positive voltage centered on the ground potential and a negative value.

A constant current source for supplying a bias current Ib1 is provided between one end of the MR head corresponding to the positive SE and the positive power supply voltage V CC set to ΔE. Similarly, a constant current source that flows the bias current Ib2 with the same current value as described above between the other end of the MR head corresponding to the negative voltage and the negative supply voltage VEE. Is provided.

The read signal obtained at one end of the MR head is supplied to the base of an npn type wide transistor QN1. The read signal obtained at the other end of the MR head is similarly supplied to the base of an npn-type wide transistor QN2. The capacity transistor C 1 is provided between the emitters of the wide transistors Q N 1 and Q N 2. This capacitor C1 holds a DC bias applied to both ends of the MR head, and allows a power and a signal current to flow. Then, a differential amplification operation is performed.

The ¾J £ VX and Vy generated at both ends of the MR head due to the flow of a constant current differ in DC level by ¾ϊdrop in the MR head. Then, the wide transistors QN 1 and QN 2 are connected like a differential wide circuit. With emitter coupling, an offset occurs between the output RDX and RDY in a steady state with no signal. In order to prevent this, a capacitor C1 is provided as a high-pass filter, and the emitter is coupled AC. By the way, if this capacitor C1 has a very small capacitance value, the impedance will look large and the low-frequency cutoff frequency will be high (the bandwidth GB product will be small).

The capacitance value of the capacitor C1 is set to a value such as 330 pF to l. To realize such a capacity value, an external capacity is used. However, considering the speeding up and miniaturization of the magnetic disk memory device as described above, the external capacity of a relatively large capacity value as described above is considered. There is no room for mounting components. If the above capacity is mounted, the size and speed of the magnetic disk memory device are correspondingly impaired.

According to the present invention, while using the capacitor C1 having a relatively small capacitance value incorporated in the semiconductor integrated circuit device formed with the lead amplifier, a circuit contrivance that acts equivalently to the above-mentioned external capacitance is used. Is what you do. In other words, the capacity C1 built into the semiconductor integrated circuit device together with the other circuit elements constituting the read amplifier has a relatively small capacitance value. While using 1, the DC bias voltage applied to both ends of the MR head is held, and a current corresponding to the signal component is passed to perform differential operation on the AC width in the alternating current. Therefore, the following current feedback circuit is provided.

The collectors of the transistors QN1 and QN2 are connected in series with npn-type transistors QN3 and QN4 each having a base applied with a predetermined bias ベース EVa, and are connected via the transistors QN3 and QN4. Load resistor Each is connected to one end of the anti-RL. The other end of the load resistor RL is supplied with the power supply voltage VCC.

The signal voltage generated by the load resistance RL is supplied to the bases of the pnp type differential transistors QP1 and QP2. One end of an emitter resistor Ra is connected to each of the emitters of the differential transistors QP1 and QP2. Between the other end of the emitter resistor Ra and the power supply voltage VCC, a constant current source Ia for forming the operating current of the differential transistors QP1 and QP2 is provided. The collector currents of these transistors QP 1 and QP 2 are made to flow to the emitters of the other wide transistors QN 2 and QN 1, respectively.

In the present invention, in a current feedback pump composed of a P np type differential transistor QP 1 and QP 2, in a no-signal state, a bias current I a is applied to the differential transistors QP 1 and QP 2 by I a / 2. Flow by each. The X-side terminal of the MR head (the base of the amplification transistor QN1) rises AVx in response to the magnetic recording information recorded on the magnetic disk surface, and the width of the transistor changes accordingly. Assume that a signal current such as ΔI 1 flows in 1. In order to cope with this increase in ¾ϊΔVX, △ I1 originally corresponding to the signal current flows through the capacitor C1.

However, in the present invention, only a minute current such as ΔIc flows through the capacitor C 1 due to the operation of the current feedback circuit. That is, due to the current △ I1 flowing through the width transistor QN1, the voltage drop generated by the load resistance RL increases, and the base potential of the ρηρ transistor QP1 decreases. As a result, the base force of the transistor QP1 falls, and the collector current force increases.

Although not shown in the figure, the Y-side terminal of the MR head (corresponding to the amplification transistor QN2) corresponds to the magnetic recording information stored on the magnetic disk surface. ス AV AV 、 AV AV AV AV AV AV AV AV 信号 AV, 、信号 2 、信号信号信号信号信号信号信号信号信号信号信号信号信号信号信号信号信号信号信号. ing. That is, the collector current of the differential transistor QP1 increases by ΔIa as Ia / 2 + ΔIa, and the collector current of the transistor QP2 increases by ΔIa as Ia / 2—ΔIa. decreases by a.

Focusing on the emitter of the amplifying transistor QN1 whose signal current has increased, the pnp differential transistor QP provided corresponding to the amplifying transistor QN2, while increasing the signal current ΔI1 The current of the collector of power 2 is reduced by Δ I a. As a result, the signal current ΔIc flowing into the capacitor C1 is reduced as the above-mentioned difference current ΔI1− △ Ia. If the change thus reduced is ΔΙ &, the current ΔIc charged to C1 is actually designed by appropriately setting the resistance Ra and setting the gain to 0.9, and ΔIa = When 0.9 I1 is set, the following equation (1) is obtained.

Δ I c = Δ I 1 (1-0.9) = 0.1 Δ I 1 (1) This is the original signal current ΔI 1 that is charged to the capacitor C 1, By providing such a current feedback circuit, it is possible to make the current value of 1/10 and not to flow, and it is possible to make the capacitance value of the capacitor C 1 appear 10 times higher.

This means that the apparent capacitance C 力 can be expressed as in equation (2).

C 1 '= C 1 ΧΔ I 1 / (Δ I 1 -Δ I a) (2) If the capacitance value is increased by a factor of 10 as described above, the capacitance of the capacitor C 1 built in the semiconductor integrated circuit device This is a force to form the value as large as 330 pF to 0.1 F, and even if it is built-in, there is a problem that a large occupied area is required. Therefore, semiconductor integrated circuits Using the capacity C1 built into the device, in order to equivalently display a large capacitance value such as 3300 pF to 1F as described above, the current gain in the current feedback circuit must be adjusted. The design should be about 0.95 (20 times capacity) and 0.97 times (33 times capacity).

The width output obtained from the collectors of the width transistors QN 1 and QN 2 is transmitted to the input of the next-stage amplifier (2 nd AMP), where it is amplified and transmitted to a signal processing circuit described later.

Although not particularly limited, in the figure, capacitors (so-called decaps) C2 and C3 for stabilizing the voltage are provided between the power supplies EVEVC C and VEE and the ground potential GND of the circuit, respectively. Such a bus capacitor is required to have a large capacitance value for stabilizing the power supply, and is constituted by an external capacitor of the semiconductor integrated circuit device. If there is room in the power supplies EVC C and V E, a semiconductor integrated circuit device may have a built-in power supply stabilizing circuit and the above-mentioned bus capacitor may be omitted.

FIG. 2 shows a circuit diagram of another embodiment of the lead amplifier. In this embodiment, a level shift diode is provided on the power supply voltage side of the load resistance RL provided to the collectors of the wide transistors QN1 and QN2. As this diode, a pnp type transistor in which a base and an emitter are connected can be used.

When a diode for level shift as in this embodiment is provided, the bases of the differential transistors QP 1 and QP 2 constituting the current feedback circuit, and the emission time «if force cancel with the forward direction« ΙΪ of the diode. Thus, the current gain can be set in accordance with the resistance ratio of the load resistance R and the resistance R a.

FIG. 3 shows a configuration of a main part of a reading system together with a read amplifier in another embodiment of the magnetic disk memory device according to the present invention. Read Door The amplifier is the same as that of the embodiment shown in FIG. 1, and a feedback amplifier FBA is used for the bias circuit of the MR head. In other words, one constant current source Ib for forming a bias current is provided at one end Vx of the MR head, and an N channel as a variable current source is provided between the other end Vy and the power supply voltage VEE. Flannel type MOSFET MN 1

The output signal of the feedback amplifier FBA is supplied to the gate of the MOSFETMN1. One input of the feedback amplifier FBA, the inverting input terminal (-), is the ground potential of the circuit, and the other input is the non-inverting input terminal (10). Connected to connection point.

When the potential at the interconnection point of the resistor Rg becomes higher than the ground potential GND, the feedback amplifier FBA raises the gate voltage of the N-channel MOS FETMN1 to increase its drain current. As a result, the potential at the interconnection point of the resistor Rg is kept low. Conversely, when the potential at the interconnection point of the resistor Rg becomes lower than the ground potential GND, the feedback amplifier FBA reduces the gate voltage of the N-channel MOSFET MN1 and reduces its drain current. . Thereby, the potential of the interconnection point of the resistor Rg is corrected to be high. By such a feedback operation, the potential of the interconnection point of the resistor Rg is controlled to be equal to the ground potential GND.

The capacitor C4 provided at the gate of the MOSFET MN1 has a stabilizing capacitance, and can be realized by a relatively small capacitance formed in the semiconductor integrated circuit device.

FIG. 4 is a circuit diagram showing another embodiment of the lead amplifier provided in the magnetic disk memory device according to the present invention. When the ground potential GND of the circuit is applied to one end of the MR head, the other end is forced to zero as described above. Only a small ¾E of about 2 V. Therefore, a bias current is supplied from the constant current source Ib1 to the other end of the MR head via a diode for level shift (or a diode-connected transistor forcibly connected to the base and the collector). Supplied.

The voltage at the other end via the above-mentioned MR head diode is supplied to the base of an npn-type wide transistor QN1. The emitter of the transistor QN1 is provided with a resistor R1 for setting a DC bias current and a capacitor C1 for alternatingly grounding its emitter to provide high sensitivity. As a result, the signal gain of the amplifying transistor QN1 can realize a large voltage gain determined by the resistance ratio between the load resistance R provided in the collector and the emitter resistor having a small resistance value in the transistor. .

The collector of the wide transistor QN1 is provided with a load resistance RL through an npn-type transistor QN3 having a constant applied to its base, and an output signal is obtained from the resistance RL.

In this case, similarly to the above, the calibrator C1 is built in the semiconductor integrated circuit device, and as a result, a capacitor having a relatively small capacitance value is used. When the capacitor C1 having such a small capacitance value is used, the impedance connected to the emitter of the wide transistor QN1 is increased, so that the large signal gain cannot be obtained.

Therefore, a current feedback circuit is provided in order to use a capacitor having a small capacitance value as formed in a semiconductor integrated circuit device, but to make the capacitance value equivalently large as described above. In this embodiment, to form a current feedback circuit, two dummy wide transistors QN are provided. The base of the wide transistor QN2 is supplied with a DC bias voltage equivalent to the DC bias voltage supplied to the base of the transistor QN1. Similarly, the collector is provided with a dummy load resistor RL through a transistor QN4 similar to the above, and the voltage signal formed by the load resistor RL is connected to a P np type differential transistor QP1. It is supplied to the base of QP2, and its collector current is fed back to the emitter side of the other wide transistors QN2 and QN1.

As a result, as in the case of the lead amplifier shown in FIG. 1, the signal current flowing through the emitter of the amplification transistor QN1 corresponds to the signal current formed by the wide transistor QN1 corresponding to the input signal. Only a small current corresponding to the difference between the current supplied from the collector of the differential transistor QP2 and the phase-shifted current flows through the capacitor C1. As a result, an operation equivalent to that obtained by increasing the capacitance value of the capacitor C1 formed in the semiconductor integrated circuit device in accordance with the current gain of the differential transistor can be performed.

In order to stabilize the circuit, it is desirable to provide the dummy wide transistor QN2 as described above. The base of the differential transistor QP1 when there is no signal is added to the base of the differential transistor QP2. It may be one that directly supplies a bias ¾ϊ equivalent to the DC voltage applied to the power supply.

FIG. 5 shows a layout diagram of an embodiment of the load resistance provided in the amplification transistor and the resistance provided in the emitter of the differential transistor constituting the current feedback circuit.

In this embodiment, the current feedback circuit has a large current gain setting capability and plays an important role in stabilizing the circuit operation. Therefore, if there is a large manufacturing variation in the resistance ratio between the load resistance RL and the emission resistance Ra, stable circuit operation cannot be expected. Conversely, in the case of a read amplifier in which a required capacitance value cannot be equivalently secured, a desired amplified signal cannot be obtained, resulting in a defective chip and a poor product quality. Therefore, the unit resistor R having the same size is used, and the load resistor RL is such that a plurality of unit resistors R are connected in series to obtain a desired relatively large resistance value. On the other hand, the resistor Ra provided at the emitter of the differential transistors QP1 and QP2 connects the unit resistor R in a parallel configuration to obtain a desired small resistance value.

As is well known, the relative ratio of the same element formed in the same semiconductor integrated circuit device can be formed with high accuracy with respect to the above-mentioned manufacturing variation. As a result, the current gain of the current feedback circuit can be set stably with high accuracy while using a resistor having a relatively large manufacturing variation formed in the semiconductor integrated circuit device, thereby realizing stable circuit operation. The product quality can be increased.

FIG. 6 is a block diagram of one embodiment of the magnetic disk memory device according to the present invention. The magnetic disk memory device of this embodiment is directed to a hard disk device, a plurality of disk disks as storage media, a motor for driving the disk disks, and both surfaces of the disk disks. To multiple MR heads, each of which reads the magnetic storage information stored in the memory, and to multiple read amplifiers, post-amplifiers, and write magnetism (inductive) provided for the MR head A plurality of read / write chips each having a write driver for moving the read / write chip, a control chip and a signal processing LSI for transmitting / receiving signals to / from the read / write chip, and a host device. Interface. The discs are mounted on a common rotating shaft whose center is rotated by a motor, and a ground potential is applied to the rotating shaft, whereby the potential of the storage surfaces of the plurality of discs is reduced to the ground potential. It is made.

As described above, a plurality of discs are provided corresponding to both surfaces of the discs. The configuration in which one read amplifier, one post-amplifier circuit corresponding to it, and a write driver are provided for each of the read-write chips can take the following chip mounting forms. In other words, the read / write chip is placed adjacent to the composite head consisting of the MR head MR and the magnetic head IND, and the small read signal from the M head is relatively long L. It is intended to minimize signal loss when transmitted using a signal transmission path and realize high-sensitivity and high-band amplification operation.

FIG. 7 shows a schematic configuration diagram of an embodiment of the hard disk device according to the present invention.

The plurality of disk disks are concentrically connected at a certain interval by a shaft. In this embodiment, one arm extends on two disk surfaces facing each other, is branched by a suspension arm, and is mounted such that the composite head comes into contact with both surfaces. When the disk is stopped, the head is in contact with the disk surface. When the disk is rotating at high speed, it floats with a small gap due to the airflow generated by the force. The read / write operation is performed with the head flying above the disk surface.

In this embodiment, the lead tip is mounted on the tip side of the arm, that is, on the mounting portion with the suspension arm. As a result, the signal wiring between the read-write chip and the head, in other words, the MR head and the lead amplifier, and the signal wiring between the magnetic head and the write driver, have the length of the suspension arm. Accordingly, the above-described high sensitivity and high band operation are realized by setting the factors that attenuate the signal such as the parasitic resistance and the parasitic inductance component in the signal wiring to the minimum. Is what you do.

A controller that performs operations such as selecting one of the multiple heads Chip and signal processing LSI should be attached to the other end of the arm.

_! The force between the control chip and the read / write chip is relatively long according to the length of the arm. Signal ports can be ignored.

FIG. 8 is a schematic structural view of a main part of an embodiment of the hard disk device according to the present invention. The read light chip is attached to the base of the suspension arm as described above. A composite head consisting of the MR head and the magnetic head is attached to the tip of the suspension arm.

The plurality of arms and the suspension arm are connected in a state of being overlapped with each other in correspondence with a plurality of disk disks, and the control chip is mounted thereon using a side surface formed by the plurality of arms. By adopting such a mounting form of the read / write chip and the control chip, the loss in the signal transmission path is minimized as described above, and a high-sensitivity, wide-band read operation and a compact hard disk drive are realized. Can be done.

FIG. 9 is a schematic sectional view of one embodiment of the disk-circular rotary drive system mechanism. The shaft of the spindle motor is made of a conductive metal, and a brush-like conductor is provided to apply a ground potential to the shaft. This conductor provides the ground potential of the circuit by making contact with the surface of the shaft. A plurality of disk disks as described above are attached to the shaft, and a ground potential is applied to the magnetic material formed on the front and back surfaces thereof. By supplying such a ground potential, the electric charge accumulated on the disc can be extracted, and by setting one end of the MR head to the ground potential as described above, discharge between the two can be prevented. FIG. 10 shows a partially cutaway external view of the embodiment of the MR ♦ inductive composite head. FIG. (A) shows an overall view of the above two elements, and (B) shows an enlarged view of the MR element. In FIG. 3A, the inductive element is used for writing, and is composed of an upper magnetic film, a lower magnetic film and an upper shield film, and a conductor configured to be sandwiched between the two magnetic films. Is done. The MR element is fabricated on the top and bottom using the same microfabrication technology as the semiconductor element, and the MR film is formed on the lower shield film sandwiched between two electrodes. As shown in the enlarged view (B), a magnetic domain control film is provided between the MR film and the electrode. In the figure, a force film is omitted. A shunt film シ a SAL (Soft Adjacent Layer) film is provided below the MR film.

The composite head floats at a minute distance (for example, several nm to several tens nm) from the disk. At such a distance that can be regarded as almost touching, the disk disk is rotating at a high speed, and the MR head also moves to change the position corresponding to the track address. For this reason, the disk and the MR head are actually in contact many times during operation. If the potential of the MR head and the potential of the disk disk differ during such contact, a short-circuit current will flow at the time of contact, and the MR head may be destroyed. The disadvantage is that the characteristics of the head are degraded or the discharge current at the time of reading is read as noise.

In this embodiment, in order to prevent a discharge caused by the disk disk and the MR head having different potentials, both are set to the same ground potential. Theoretically, if the two potentials are the same, the above-described discharge does not occur, but a bias voltage for that purpose is provided by a low-impedance power supply, which is not practical. By using the ground potential of the most stable and simple circuit among the power supplies of magnetic disk memory devices, However, the burden on the power supply can be reduced. In order to configure a read amplifier with high sensitivity while using the ground potential of such a circuit, two power supplies (VCC and VEE) as in the embodiment of FIGS. 1 to 3 are used. In the vicinity of the midpoint voltage (GND), the width transistor of the lead amplifier is bypassed. Alternatively, as shown in the embodiment of FIG. 4, in the lead amplifier operating with one power supply (VCC), a diode for level shift is used. What you buy. FIG. 11 is a plan view of one embodiment of a wire substrate used in the magnetic disk memory device according to the present invention. The wiring board of this embodiment is

The connection between the head shown in FIG. 7 and the like, the read / write chip, and the control chip is made by the flexible wiring substrate. This flexible wiring board is formed by the well-known EI spring substrate technology, and is provided with test pads for testing the electrical characteristics of the formed wiring. In other words, an electrode is applied to the test pad, and a test is performed to determine whether or not the wiring has desired transmission characteristics. This transfer characteristic also includes DC tests such as short circuits between wires, disconnection of signal lines, and so on. The flexible wiring board has an electrode connected to the composite head at one end, a lead / write IC mounting part at the middle, and an electrode to connect to the control chip at the other end. . The test pad is provided on the electrode part connected to the composite head and the electrode part connected to the control chip. When the above test is completed, the test pad is cut off at the dotted line.

FIG. 12 is a plan view showing an embodiment of the arm and suspension unit in the magnetic disk memory device according to the present invention. In the figure, (A) shows the mounting surface of the read / write IC, and (B) shows the back surface thereof.

The composite head is connected to the flexible wiring board on the back side, and A read drive IC is mounted in the opening at the tip of the room. As a result, the mounting space in the height direction of the IC can be secured by the thickness of the arm. That is, the overall thickness when the read / write IC is mounted on the arm can be reduced, and the overall height when a plurality of arms are stacked as shown in FIG. 8 can be reduced. This makes it possible to reduce the thickness of the hard disk memory device.

Although not particularly limited, two chip capacitors are provided at the tip of the arm in addition to the read light IC as described above. If this chip capacitor is operated with dual power supplies VCC and VEE as shown in the embodiment of FIGS. It is a bus capacitor that stabilizes the power supply voltages VCC and VEE. In this embodiment, since the necessary capacity is built in the read amplifier as described above, the number of chip capacitors provided together with the read-drive IC is increased by two. It can be reduced to individual. As a result, the moment of inertia when the arm seeks at high speed can be reduced, and the head can be moved quickly and smoothly.

FIG. 13 is an external view of an embodiment of the arm and suspension unit in the magnetic disk memory device according to the present invention.

As shown in FIG. 8, a plurality of arms are superposed to correspond to a plurality of magnetic disks, and FIG. 8 shows one arm, suspension and flexible wiring. ing. An open force is provided at the selected side of the arm, in other words, at the connection with the suspension, and the element mounting surface is formed so that it faces from the bottom to the upper surface. Flexible | Provided. On the element mounting surface of the flexible wiring in the arm opening, a front chip that constitutes the above-described read-out IC is provided. Chip capacitors (pass capacitors) provided for capacitors and power supplies. The front end of the flexible wiring is connected to the composite head as described above, and the other end is connected to an electrode of a mounting board mounted on a carriage and mounted with a control chip.

The operational effects obtained from the above embodiment are as follows.

(1) Corresponding to a disk-shaped magnetic recording body to which the first potential of the circuit is applied, a positive voltage centering on the first potential of the circuit is placed on the tip of the arm (so-called suspension) to which the MR head is attached. A semiconductor integrated circuit device that operates at the second potential at the potential and the third voltage at the negative potential, and in the semiconductor integrated circuit device, the first potential is the center voltage of the MR head; A bias circuit for supplying a predetermined bias to both ends; a first and a second amplifying transistor to which the signals read from both ends of the MR head are respectively supplied to the base; A capacitor provided between the first and second amplifying transistors for holding a DC bias voltage supplied to both ends of the MR head and flowing a signal current; Collector output of amplification transistor Current feedback circuit that receives a signal and is slightly smaller than the emission currents of the first and second width transistors and that feeds back a current that is out of phase to reduce the signal current component flowing into the capacitor. By incorporating a read amplifier that obtains an output signal from the collector of the first and second amplification transistors, the moment of inertia of the arm is reduced to speed up its movement, and the size of the entire device is reduced. Can be realized.

(2) First and second resistive elements having a sufficiently larger resistance value at both ends of the MR head and having the first potential provided at the interconnection point thereof are provided. By providing a current source that supplies a bias current to the other end of the MR head, the first and second resistance elements, Even if the head does not break down or break due to short-circuit current at the time of contact due to the difference between the potential of the disc and the potential of the disc, the characteristics of the MR head deteriorate or the discharge current at reading causes noise. The readout signal is output as a voltage signal, and the inductance component of the wire connecting the MR head and the read amplifier is directly affected. This has the effect that the readout power up to high frequencies becomes possible without limiting the extraction of high-frequency signals.

(3) A first current source is provided between one end of the MR head and the second ¾ ±, and a transistor is provided between the other end of the MR head and the third ¾EE. The interconnection point of the first and second resistance elements is supplied to a first input terminal, and the transistor is controlled by a feed-in pump in which the first potential is applied to a second input terminal. By making the potential at the interconnection point between the first and second resistance elements equal to the first potential, it is possible to supply the required bias current and bias voltage to the MR head with high accuracy. Effect is obtained.

(4) A load resistance element is provided between the collectors of the first and second amplifying transistors and the second ¾ff, and the voltage signal formed by the load resistance element is set in a differential form. An emitter resistor is provided at the emitter of the third and fourth transistors, and a constant current source is provided between the interconnection point of the emitter resistor and the second ΔS. By returning the collector currents of the third and fourth transistors to the emitters of the other second and first wide transistors, the emitter currents of the first and second wide transistors are changed. An effect is obtained that the signal current component flowing into the capacitor can be reduced by feeding back a current that is slightly smaller than the above and that has an opposite phase. (5) The first and second wide transistors are npn transistors, the third and fourth transistors of the current feedback circuit are pnp transistors, and the collectors of the first and second amplification transistors are An npn-type transistor with a predetermined constant voltage applied to the base is further provided between the load resistance element and the parasitic resistance on the collector side of the first and second wide transistors. This has the effect of making it equivalently smaller and allowing amplification operations up to high frequencies to be performed.

(6) The other end of the load resistance element is commonly connected, and a diode that performs a level shift operation is connected between the other end of the load resistance element and the current gain of the differential transistor circuit that constitutes the current feedback circuit. Since it can be set by the resistance ratio between the load resistance and the emitter resistance, the current feedback amount can be set with high accuracy and accuracy, and the desired amplification operation can be performed stably using the built-in capacity. Is obtained.

(7) The load resistance element and the emitter resistor are constituted by a plurality of unit resistances formed to have the same resistance value, and the load resistance element includes a plurality of the unit resistances connected in series. By connecting a plurality of the above-mentioned unit resistors in parallel, the desired resistance value can be achieved and the resistance ratio can be made almost constant irrespective of the manufacturing variation of the element. Therefore, the desired amplification operation can be performed more stably while using the built-in capacitor.

(8) A composite head consisting of an MR head, a magnetic head, and a force is attached to the top end of the suspension, and the magnetic head is driven by the semiconductor integrated circuit device equipped with the read amplifier power. Built-in write driver that minimizes the loss in the signal transmission path between the head and the signal processing circuit, achieves high-sensitivity, wideband read-write operation, and reduces the size of the hard disk drive. The effect of realizing patterning is obtained.

(9) By providing a control chip corresponding to a plurality of the read amplifiers at the base of the arm attached with the suspension force, the mouth of the signal transmission path between the head and the signal processing circuit can be controlled. By minimizing the size of the hard disk drive, it is possible to obtain a high sensitivity and wide band read / write operation.

(10) As a self-lead amplifier, one end of the MR head is connected to the first potential, and the other end is supplied with a bias current from the second potential via the level shift means to the MR. A signal read from the other end of the pad through the level shift means is supplied to the base of the first amplifying transistor, and an emitter resistor is provided between the emitter and the first potential. A capacitor is built in the semiconductor integrated circuit device in parallel with the resistor, holds the DC bias voltage applied to the MR head, and connects a capacitor through which power and signal current flow. Receiving the output signal, the current that is slightly smaller than the emitter current of the first amplification transistor and the current whose phase is reversed is fed back to reduce the signal current component flowing into the capacitor, thereby simplifying the power supply device. In addition, it is possible to reduce the moment of inertia of the arm to increase the speed of its movement and to achieve the effect of downsizing the entire device.

(11) A second amplification transistor, which is provided corresponding to the first amplification transistor, is supplied with a bias voltage corresponding to the base DC voltage of the first width transistor to the base, and operates as a dummy element, Load resistance elements are provided between the collectors of the first and second wide transistors and the second voltage, respectively, and the third and third voltage signals formed by the load resistance elements are made differential. The emitter resistor is provided at the third and fourth emitters, and the interconnection point between the emitter resistor and the second emitter is provided. A constant current source is provided between the first and second transistors, and the collector currents of the third and fourth transistors are returned to the emitters of the other second and first wide transistors. The current that is slightly smaller than the emitter current of the transistor can be fed back stably, and the current that is in phase opposite to that of the transistor can be stably fed back, and the signal current ^ flowing into the capacitor can be reduced. Can be

(12) The first and second wide transistors are npn transistors, the third and fourth transistors of the self-current feedback circuit are pnp transistors, and the first and second transistors are Between the collector of the amplifying transistor and the load resistance element, an npn-type transistor having a predetermined constant E applied to the base is further provided, so that the first and second wide-band transistors are connected. The effect is that the parasitic resistance on the side can be reduced equivalently, and the amplification operation up to a high frequency can be performed.

(13) A disk-shaped magnetic storage medium that is driven to rotate via the rotary shaft of the drive mechanism and to which the first potential of the circuit is applied, and is attached to the distal end side with a MR head through a suspension On the connection side between the arm connected to the suspension and the suspension in the arm, receiving the second voltage made positive at the first potential of the circuit above and the third m ± made negative at the negative potential In a magnetic disk memory device comprising a semiconductor integrated circuit device having a read amplifier output from the MR head and a read amplifier for controlling the read signal output from the MR head, the first read amplifier is used as the read amplifier. A bias circuit for supplying a predetermined bias voltage to both ends of the MR head with the electric potential as a center, and first and second signals supplied to the base from the signals read from both ends of the MR head, respectively. With the second amplification transistor Provided between the first and the second amplifier transient scan evening emitter, a capacitor supplying a signal current holds the DC bias «1I supplied to both ends of the head to the MR, the first A signal current that receives the collector output signals of the first and second amplifying transistors, is slightly smaller than the emitter current of the first and second wide transistors, and returns a current that is in opposite phase to flow into the capacitor. It consists of a current feedback circuit that reduces the component, and obtains an output signal from the collector of the first and second amplifying transistors to reduce the inertial moment of the arm and speed up its movement, The effect is obtained that the size of the entire apparatus can be reduced.

(14) By applying the disk-shaped magnetic storage medium to a hard disk, it is possible to obtain an effect that a hard disk memory device which is small and realizes high-speed operation can be obtained.

(15) As the driving mechanism, a brush-like conductor as means for rotating the conductive shaft to which the plurality of storage media are attached by a spindle motor and setting the shaft to the same potential as the ground potential of the circuit. With the use of the above, the ground potential can be applied to the disk disk with a simple configuration, and the MR head has a short-circuit current at the time of contact due to the potential difference between the MR head and the potential of the disk disk. Degradation of the MR head even if it does not lead to destruction or destruction of the MR head has the effect that the discharge current at the time of reading prevents noise and realizes a highly sensitive and stable reading operation.

(16) The drive mechanism rotates a plurality of storage media, and a plurality of the suspensions, MR heads and read amplifiers are provided for each of the plurality of storage media, thereby realizing miniaturization and high reliability. An effect is obtained that a hard disk memory device realizing the H characteristic can be obtained. Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, to MR The circuit for supplying the DC bias EE to the head can take various embodiments. The MOSFET MN 1 in FIG. 4 can be replaced with a η ρ η type bipolar transistor. Conversely, bipolar transistors such as the amplification transistors QN1 and QN2 and the differential transistors QP1 and QP2 may be replaced with MOSFETs.

In order to form the self-read amplifier, the capacitors C1 and C4, etc. built into the semiconductor integrated circuit device having such a read-amplifier function use a MOS capacitor and a nitride as a dielectric. Various embodiments can be adopted, such as one using a metal film. The configuration of the MR head can employ various embodiments other than the above-described embodiment. Industrial applicability

The present invention uses an MR (magnetoresistive) head as a read head, and furthermore uses an inductive head as a read MR (magnetoresistive) head and a write head. It can be widely used for magnetic disk memory devices such as hard disk memory devices using composite heads that use the same.

Claims

The scope of the claims

1. a disk-shaped magnetic storage medium to which the first potential of the circuit is applied;

An arm with an MR head attached to the tip side via a suspension,

A semiconductor integrated circuit device, which operates on the connection side of the arm with the suspension, receiving a second voltage made positive about the first potential of the circuit and a third Δffi made negative, around the first potential of the circuit. A magnetic disk memory device equipped with a read amplifier for amplifying a read signal output from the MR head,

The above read amplifier,

A bias circuit for supplying a predetermined bias to both ends of the MR head with the first potential as a center voltage,

A first amplification transistor to which a signal read from one end of the MR head is supplied to a base;

A second amplification transistor to which a signal read from the other end of the MR head is supplied to a base;

It is provided between the emitters of the first and second amplifying transistors, is built in the semiconductor integrated circuit device, holds the noise supplied to both ends of the MR head, and generates a signal current. With a capayu evening flowing ingredients,

A signal which receives the collector output signals of the first and second amplifying transistors, feeds back a current that is slightly smaller than the emitter currents of the first and second amplifying transistors, and has an opposite phase, and flows into the capacitor. And a current feedback circuit for reducing

A magnetic disk memory device wherein an output signal is obtained from the collectors of the first and second amplification transistors.

2. In claim 1, the bias circuit is First and second resistors that are connected in series to both ends of the MR head, have a resistance value sufficiently larger than that of the MR head, and have the first potential applied to their interconnection points. Element and

A magnetic disk memory device comprising: the first and second resistance elements; and a current source that supplies a bias current supplied to the other end of the MR head.

3. The bias circuit in claim 1,

The first and second resistance elements are connected in series to both ends of the MR head, and have a sufficiently larger resistance value than the MR head.

A first current source provided between one end of the MR head and the second «Ε,

A transistor provided between the other end of the MR head and the third «Ε,

The interconnection point between the first and second resistance elements is supplied to a first input terminal, the first potential is applied to a second input terminal, and the output signal is supplied to the input terminal of the transistor to provide A magnetic disk memory device comprising: a feedback amplifier for making a potential at an interconnection point between first and second resistance elements equal to the first potential.

4. In Claim 3,

Load resistance elements are provided between the collectors of the first and second amplification transistors and the second SE, respectively.

The current feedback circuit,

A third transistor and a fourth transistor in a differential form for receiving a voltage signal formed by the load resistance element;

The emitter resistors provided in the third and fourth emitters, respectively; A constant current source provided between the interconnection point of the emitter resistor and the second «,

A magnetic disk memory device characterized in that the collector currents of the third and fourth transistors are supplied to the emitters of the other second and first wide transistors, respectively.

5. In Claim 4,

The first and second amplifying transistors are npn-type transistors,

The third and fourth transistors of the self-current feedback circuit are pnp-type transistors,

A magnetic disk memory device, further comprising an npn-type transistor having a base applied with a predetermined constant voltage, between the collectors of the first and second amplifying transistors and the load resistance element. .

6. In Claim 5,

The other end of the load resistance element is commonly connected, and a diode for performing a level shift operation with the second voltage is connected to the load resistance element.

7. In Claim 4,

The self-load resistance element and the above-mentioned resistance are composed of a plurality of unit resistors formed to have the same resistance value.

The load resistance element is configured by connecting a plurality of the unit resistors in series.

The magnetic disk memory device according to claim 1, wherein the emitter resistor is configured by connecting a plurality of the unit resistors in parallel.

8. In Claim 1,

The MR head, the magnetic head, the force, and the Composite head is attached,

A magnetic disk memory device characterized in that a semiconductor integrated circuit device on which the above-mentioned lead amplifier is mounted also incorporates a write driver for circulating the magnetic head.

9. In Claim 8,

A magnetic disk memory device, characterized in that a control chip corresponding to a plurality of the lead amplifiers is provided at the base of the arm attached with the suspension force.

10. A disk-shaped magnetic storage medium to which the first potential of the circuit is applied;

A arm attached to the MR head via a suspension at the distal end,

A semiconductor integrated circuit device that operates on the connection side with the suspension in the above-mentioned arm, receiving the first potential and the second line of the above-mentioned circuit, and amplifies a read signal output from the above-mentioned MR head. A magnetic disk memory device equipped with a read amplifier,

The above read amplifier,

An MR head having one end connected to the first potential and the other end supplied with a bias current from the second potential via a level shift means;

A first amplifying transistor to which a signal read from the other end of the MR head via the level shift means is supplied to a base;

An emitter resistance provided between the emitter of the first amplification transistor and the first potential;

A capacity provided in parallel with the emitter resistor, built in the semiconductor integrated circuit device, holding a DC bias voltage applied to the MR head, and flowing a signal current; A current that receives the collector output signal of the first amplification transistor, is slightly smaller than the emitter current of the first width transistor, and feeds back an inverted current to reduce the signal current flowing into the capacitor. Including a feedback circuit,

A magnetic disk memory device wherein an output signal is obtained from a collector of the first amplification transistor.

11. In claim 10,

A second amplification transistor that is provided corresponding to the first amplification transistor, is supplied with a bias voltage corresponding to the base DC voltage of the first width transistor, and operates as a dummy element;

A load resistance element is provided between each of the collectors of the first and second wide transistors and the second «ΙΪ,

The current feedback circuit,

The emitter resistors provided in the third and fourth emitters, respectively;

A constant current source provided between the interconnection point of the emitter resistor and the second,

A magnetic disk memory device, wherein the collector currents of the third and fourth transistors are supplied to the emitters of the other second and first amplification transistors.

12. In Claim 11,

The first and second wide transistors are η ρ η type transistors,

The third and fourth transistors of the current feedback circuit are ρηρ type transistors. It consists of

A magnetic disk memory device characterized by further comprising an npn transistor having a base applied with a predetermined constant voltage between the collectors of the first and second amplifying transistors and the load resistance element. .

13. drive mechanism;

A disk-shaped magnetic storage medium that is rotationally driven through a rotary shaft of the drive mechanism and is supplied with a first potential of a circuit;

MR head via suspension on the tip side 《Attached arm and

A semiconductor integrated circuit device, which operates on the connection side of the arm with the suspension, receiving a second voltage made positive about the first potential of the circuit and a third ¾ϊ made negative, around the first potential of the circuit. A magnetic disk memory device including a read amplifier for amplifying a read signal output from the MR head,

The above read amplifier,

A capacitor is provided between the emitters of the first and second amplifying transistors, is built in the semiconductor integrated circuit device, holds a bias supplied to both ends of the MR head, and flows a cap signal current. Evening and

Receiving the collector output signals of the first and second amplifying transistors, and slightly smaller than the emitter current of the first and second amplifying transistors; And a current feedback circuit that feeds back the inverted current to reduce the signal current component flowing into the capacitor,

14. In claim 13,

A magnetic disk memory device, wherein the disk-shaped magnetic storage medium is a hard disk.

15 In section 14 of the blueprint,

The drive mechanism is

A spindle motor,

A conductive shaft attached to the plurality of storage media and rotated by the spindle motor;

A magnetic disk memory device comprising: a brush-like conductor as means for setting the shaft to the same potential as the ground potential of a circuit. 16. In claim 15,

The drive mechanism is for rotating a plurality of storage media, and is provided with the suspension, a plurality of MR heads, and a plurality of lead amplifiers corresponding to each of the plurality of media. A magnetic disk memory device characterized in that: