WO2000054409A1

WO2000054409A1 - Circuit having output buffer with dynamic impedance

Info

Publication number: WO2000054409A1
Application number: PCT/EP2000/001337
Authority: WO
Inventors: Marinus A. W. Van Den Broek; Johannes M. Peters
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 1999-03-10
Filing date: 2000-02-18
Publication date: 2000-09-14

Abstract

A circuit has an output buffer that is switchable between at least a lower and a higher output impedance mode. The lower impedance mode is selected after logic transitions on the input and the higher impedance mode when a signal at the output enters a predetermined range around a nominal level required by the input. The circuit comprises a memory circuit (160) for blocking switch-back to the lower output impedance mode after the signal at the output has been in the predetermined range as long the output signal at the input does not change.

Description

Circuit having output buffer with dynamic impedance.

The invention relates to a circuit with an output buffer.

US patent No. 5241221 (EP 466238; PHA 1203) discloses an output buffer with two driver circuits in parallel. The output buffer operates in two modes: a lower output impedance mode in which both drivers are active in parallel and a higher output impedance mode in which one of the drivers is disabled.

The output buffer operates in the lower output impedance mode when the output buffer drives its output from one logic level to another. This ensures high speed switching. The output buffer is switched to the higher impedance mode when the switch from one logic level to the other is underway. In the higher output impedance mode the output impedance of the output buffer is increased to an output impedance value that substantially matches the transmission line impedance of the conductor that is connected to the output. Thus, by using two output impedance modes, the known circuit combines the advantages of matching to the transmission line impedance and increased initial speed during transitions. It should be noted that the output is driven in both modes and not left floating. In addition to the higher and lower output impedance modes, the output buffer may have a floating output mode, in which the transmission line connected to the output buffer is left free to be driven by other output buffers.

The voltage at the output of the output of the output buffer is used to control switching between the output impedance modes. The distance between the voltage at the output and the desired output voltage determines the mode: when the distance is sufficiently small, the output buffer is in the higher output impedance mode, otherwise it is in the lower output impedance mode.

As a result, the known output buffer will return to the lower output impedance mode if the voltage deviates again from the desired level, due to reflections on the conductor that is connected to the output. Return to the lower output impedance mode will cause new reflections. This is undesirable because it increases the undesired signals on the conductor.

Amongst others, it is an object to provide for reduction of the amount of undesired signals on the conductor connected to the output of the output buffer. The circuit according to the invention is set forth in Claim 1. By using a memory circuit to control the impedance of the output buffer, it is ensured that the output buffer cannot be switched back to the low impedance mode after the output buffer has brought the signal at the output to the desired level in response to a transition at the input. Thus, noise due to reflections cannot cause the output buffer to return to the low impedance mode. The lower impedance is realized for example by switching on an additional driver in parallel with the driver that drives the output buffer in the higher impedance mode, or by switching on a lower impedance driver instead of a higher impedance driver. Claim 3 describes an embodiment of the circuit according to the invention. In this embodiment the circuit is realized with level sensitive circuits only, i.e. without edge triggered circuits, which complicate its design and makes it dependent on the environment of the circuit. If the circuit has to adapt the impedance both on rising and falling edges, preferably a complementary version of the structure of Claim 2 is added, so that a respective structure is present for each edge. Of course, if only one of the rising and falling edges needs adaptation, only one memory circuit is used.

Claim 4 describes another embodiment of the circuit according to the invention. The most significant reflection problems occur with reflections that arrive back at the output buffer in response to the transition generated by the output buffer. These reflections arrive soon after the transition, usually when the transition is little more than halfway. By switching to the higher impedance mode before that, the initial speed of the transition is increased and reflections on the remainder of the transition are prevented.

Claim 5 describes a further embodiment of the circuit according to the invention. By delaying the process of switching on the static driver, the output impedance of the static driver will be higher at the time the dynamic driver is switched off. Thus it is possible to provide a substantially adapted early output impedance to the transmission line at the time that the dynamic driver is switched off and a lower impedance later on. As a result, reflections are prevented when the dynamic driver is switched off and additional level holding strength is available later on.

These and other advantageous aspects of the invention will be illustrated using examples shown in the accompanying drawing, which shows

Figure 1 a first embodiment of a circuit with an output buffer. Figure 2 an embodiment of an output buffer.

Figure 1 shows a circuit with an output buffer. This circuit contains a signal sending circuit 10 and a signal receiving circuit 18, connected via an output buffer 1 1 and a conductor 17 that forms a transmission line. The output buffer 11 has an input and an output and contains a static driver 12a,b and a dynamic driver 14, 16. The input of the output buffer 11 is connected to an output of the signal sending circuit 10. The output of the output buffer 1 1 is connected to the signal receiving circuit 18 via the conductor 17.

The static driver 12a.b contains an NMOS transistor 12a and a PMOS transistor 12b with channels coupled from the output to a first and second power supply connection Nss, Ndd respectively. The gates of the ΝMOS transistor 12a and the PMOS transistor 12b are coupled to the input of the output buffer 1 1.

The dynamic driver 14. 16 contains an impedance control circuit 16 and a dynamic ΝMOS driver transistor 14. The impedance control circuit contains an enabling/disabling circuit 162 coupled between the input of the output buffer 1 1 and a gate of the dynamic ΝMOS driver transistor 14. The channel of the ΝMOS driver transistor 14 is coupled between the output of the output buffer 11 and the first power supply connection Nss. The impedance control circuit 16 contains a memory element 160, which has inputs coupled to the input and output of the output buffer 11 respectively, and an output coupled to the enabling/disabling circuit 162.

In operation, the signal sending circuit 10 generates logic level transitions on the input of the output buffer 1 1. In response, the output buffer 11 generates opposite logic level transitions on the output of the output buffer 1 1. The circuit shown in figure 1 illustrates a special treatment of transitions from logic input low to high on the input of the output buffer 1 1.

Before the input low to high transition, the logic level at the input and output of the output buffer 1 1 are logic low and high respectively. PMOS transistor 12b conducts and ΝMOS transistor 12a is non-conductive. The memory element 160 is kept in a set state by the input of the output buffer 11 when this input is low. In this state, enabling/disabling circuit 162 passes the low input signal to the gate of dynamic ΝMOS transistor 14, which is therefore non-conductive.

Immediately after the input low to high transition, the memory element 160 remains in the set state and therefore the input signal pulls dynamic ΝMOS transistor into a conducting state. ΝMOS transistor 12a also conducts and PMOS transistor 12b is non- conductive. As a result the voltage on the conductor is pulled towards Nss by both the dynamic MOS driver transistor 14 and the ΝMOS transistor 12a.

Once the voltage at the output of output buffer 1 1 has fallen beyond a threshold level of memory element 160, which is approximately midway logic high and low or higher, the output resets the memory element 162 to a logic reset state. In the reset state the memory element 162 causes the enabling/disabling circuit 162 to pull the gate of dynamic ΝMOS transistor 14 to NSS. making the dynamic ΝMOS transistor 14 non-conductive. Until the memory element 162 is brought back to the set state by a logic low on the input of output buffer 1 1. memory element 160 will continue to force enabling/disabling circuit 162 to make dynamic ΝMOS transistor 14 non-conductive.

As a result, dynamic ΝMOS transistor 14 will help ΝMOS transistor 12a to pull the voltage of the conductor 17 low immediately after a low to high transistor on the input of the output buffer 1 1. until that voltage is approximately halfway logic low and high. After that, ΝMOS transistor 12a drives the output of the output buffer 1 1 on its own. no matter what happens to the voltage on the output of output buffer 1 1 , until the input of output buffer 1 1 switches to logic low and back again to logic high.

The impedance of the ΝMOS transistor 12a substantially matches the transmission line impedance of conductor 17, at least when the voltage at the output of the output buffer is nearly halfway between logic low and high. This transmission impedance is for example between 75 and 80 Ohm for typical applications in PC's (Personal Computers). This means that any transmission line reflections that arrive back at the output buffer 1 1 from the receiving circuit 18 via transmission line 17 will be substantially absorbed by output buffer 1 1.

Of course, the circuit of figure 1 can be varied without deviating from the invention. For example, only one dynamic driver 14, 16 is shown, which handles one direction of input signal transition. A second, similar dynamic driver circuit may be provided connected to Vdd for handling input signal transitions in the opposite direction. Furthermore, also by way of example, instead of bringing the memory element 160 into its reset state dependent on the voltage level on the output of output buffer 17. it may be reset a fixed delay time after it is set. Similarly, the memory element may be set by the transition of the input signal rather than its level.

Figure 2 shows part of a further output buffer. This output buffer contains a static pull-down circuit 20 and a dynamic driver 22. The static pull-down circuit 20 contains cascade of a first inverter 200 a NAND gate 202, a second inverter 204, 206, 208 and an NMOS transistor 12a, which corresponds to the NMOS transistor 12a of figure 1. An input of the first inverter 200 is coupled to an input of the output buffer. Inputs of the NAND gate 202 are coupled to the output of the first inverter 200 and an "output enable" input. The second inverter contains a series connection of a channel of a PMOS transistor 208, a resistor 206 and an NMOS transistor 204 successively, between the second power supply connection Vdd and the first power supply connection Nss. An output of the ΝAΝD gate 202 is coupled to the gates of the PMOS transistor 208 and the ΝMOS transistor 204. A node between the resistor 206 and the channel of the ΝMOS transistor 205 is coupled to the gate of ΝMOS transistor 12a. The channel of ΝMOS transistor 12a is connected between the output of the output buffer and the first power supply connection Vss.

The dynamic driver circuit 22 contains a memory element 220, a NOR gate 222 and dynamic NMOS driver transistor 14, which corresponds to the dynamic NMOS driver transistor 14 of figure 1. The output of NAND gate 202 is coupled to a set input of the memory element 220. The input of the output buffer is coupled to a first input of NOR gate 222. An output of memory element 220 is coupled to a second input of NOR gate 222. The inverse of the output enable input is coupled to a third input of the NOR gate 222. The output of NOR gate 222 is coupled to the gate of dynamic NMOS driver transistor 14. The channel of dynamic NMOS driver transistor 14 is connected between the output of the output buffer and the first power supply connection Nss. The output of the output buffer is connected to an inverting reset input of memory element 220.

Memory element 220 is realized for example as a pair of cross-coupled ΝAΝD gates (not shown), one ΝAΝD gate having an input coupled to the output of the output buffer and the other ΝAΝD gate having an input coupled to the output of ΝAΝD gate 202 via an inverter (not shown). Of course other settable and resettable memories can be used without deviating from the invention.

Preferably, complementary counterparts (not shown) of driver circuits 20, 22 are included in the output buffer for driving the output to a logic high voltage. In the complementary counterparts the role of logic high and low, low power supply and high power supply, Pomes and ΝMOS are exchanged in comparison with the driver circuits 20, 22.

In operation dynamic driver circuit 22 works similar to dynamic driver circuit 14, 16 of figure 1. Memory element 220 is set when the input of the output buffer is logic high and reset when the output of the output buffer is below a threshold. The threshold is for example approximately halfway between logic high and low, or at a third from logic low to logic high or higher. Thus, dynamic NMOS driver transistor 14 is active only briefly after a high to low transition on the input.

Static pull-down circuit 20 works with a delay with respect to dynamic driver circuit 22. After the input goes from logic high to low, static pull-down circuit 20 will start pulling the voltage at the output of the output buffer to logic low. In response to the high to low transition, the voltage at the gate of NMOS transistor 12a will be pulled to Ndd via resistor 206 and PMOS transistor 208. Mainly because the resistor 206 slows down charging of the gate of ΝMOS transistor 12a, the ΝMOS transistor 12a will become conductive more gradually than dynamic ΝMOS driver transistor 14.

The resistor 206 is chosen so that ΝMOS transistor 12a will not yet have reached its maximum conductivity at the dynamic switch-off time when dynamic ΝMOS driver transistor 14 is switched off due to the reset of memory element 220. At this dynamic switch-off time the voltage at the output of the output buffer is at the threshold of memory element 220. (The threshold is for example approximately halfway between logic high and low, or at a third from logic low to logic high or higher). The combination of the circuit parameters of the second inverter 204, 206 and 208 is selected so that at this dynamic switch- off time the impedance of the ΝMOS transistor 12a will substantially match the transmission line impedance of conductor 17. Thus, around the dynamic switch-off time ΝMOS transistor 12a will substantially absorb any reflections that arrive back from conductor 17 in response to the high to low transition that is started by dynamic ΝMOS driver transistor 14 and ΝMOS transistor 12a. After the dynamic switch-off time the impedance presented by ΝMOS transistor 12a will continue to fall, so that this impedance will eventually be well below the transmission line impedance. This ensures that the conductor 17 is kept solidly at logic low level. By switching ΝMOS transistor 12a on gradually, ΝMOS transistor 12a combines the two functions of solidly holding the logic low level and absorbing reflections at the critical time, when most reflections arrive, i.e. shortly after the dynamic switch-off time.

Of course, these functions could also be separated, including more pull-down transistors like ΝMOS transistor 12a in parallel, one that is made conductive quickly and provides the proper impedance and another that is made conductive only later and serves mainly to keep the logic low level on the conductor 17. However, using one transistor has the advantage of avoiding unnecessary additional switching. The output enable input serves to enable or disable the circuit. When output enable is logic low and inverse output enable is logic high, NMOS transistors 12a, 14 are kept non-conductive irrespective of the input and output signals.

Of course in an output buffer the circuit of figure 2 may be combined with another, complementary circuit for handling low to high transitions.

Claims

CLAIMS:

1. A circuit with an output buffer that is switchable between at least a lower and a higher output impedance mode, the output buffer having an input, an output and a mode select circuit, the output buffer driving the output with a relatively higher and lower impedance in the higher and lower output impedance mode respectively, the mode select circuit selecting the lower impedance mode after logic transitions on the input and the higher impedance mode when a signal at the output enters a predetermined range around a nominal level required by the input, characterized in that the mode select circuit comprises a memory circuit for blocking switch-back to the lower output impedance mode after the signal at the output has been in the predetermined range, said blocking lasting at least as long the output buffer is active and a signal at the input does not change.

2. A circuit according to Claim 1, wherein the output buffer comprises a first and a second driver circuit coupled to the output in parallel, at least the first driver circuit driving the output in the lower output impedance mode, the second driver circuit but not the first driver circuit driving the output in the higher output impedance mode.

3. A circuit according to Claim 1, wherein the memory circuit comprises a memory element for selecting the mode during transitions from a first output signal level to a second output signal level, the memory element having a set input and a reset input, coupled to the input and the output of the output buffer respectively, so that the memory element is set when the signal at the input is at a first logic level and reset when the signal at the output is within the predetermined range around the nominal level required in response to the logic inverse of the first logic level at the input.

4. A circuit according to Claim 1 , wherein the predetermined range comprises at least half the signal range between the nominal level and level corresponding to the logical opposite of the nominal level.

5. A circuit according to Claim 2, comprising a delay circuit between the input of the output buffer and an input of the second driver circuit, the delay circuit switching on the second driver circuit with a delay relative to the first driver circuit, so that the input of the second driver circuit is not yet fully driven when the first driver circuit is switched off.