WO2000050991A3 - Method and apparatus for scheduling program code in a computer system - Google Patents

Method and apparatus for scheduling program code in a computer system Download PDF

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Publication number
WO2000050991A3
WO2000050991A3 PCT/IB2000/000081 IB0000081W WO0050991A3 WO 2000050991 A3 WO2000050991 A3 WO 2000050991A3 IB 0000081 W IB0000081 W IB 0000081W WO 0050991 A3 WO0050991 A3 WO 0050991A3
Authority
WO
WIPO (PCT)
Prior art keywords
schedule
execution
performer
during
basic period
Prior art date
Application number
PCT/IB2000/000081
Other languages
French (fr)
Other versions
WO2000050991A2 (en
Inventor
Robert Kroeger
William Cowan
Original Assignee
Liquimedia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Liquimedia Inc filed Critical Liquimedia Inc
Priority to AU30703/00A priority Critical patent/AU3070300A/en
Publication of WO2000050991A2 publication Critical patent/WO2000050991A2/en
Publication of WO2000050991A3 publication Critical patent/WO2000050991A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic

Abstract

Embodiments of the invention comprise a mechanism configured to schedule program code for execution and provide feedback regarding the schedule. Program code, or other unit of execution, is referred to herein as a performer. Each performer has associated information that includes historical information regarding its execution behavior which is used to predict the future behavior of the performer (e.g., mean and variance of the execution time, etc.). In one or more embodiments of the invention, one or more performers are scheduled for execution during an execution interval that is referred to as a basic execution period or basic period. A scheduler insures that the performers that are scheduled to execute during the basic period have at least a threshold probability (referred to as a safety factor (or Sf) of executing to completion during the basic period. If a schedule satisfies the safety factor it is considered to be correct. Where the schedule is not considered to be correct, one or more incorrect performers may be removed from the schedule and the schedule is re-verified. A conductor iterates through a verified schedule to invoke each performer if it believes that the performer can execute to completion during the basic period. During each basic period, the conductor gathers information associated with a performer's behavior that can be used to re-evaluate the correctness of a schedule. Through a continual process of regular re-verifications, the invention can provide probabilistic realtime execution of independently authored code fragments.
PCT/IB2000/000081 1999-02-26 2000-01-10 Method and apparatus for scheduling program code in a computer system WO2000050991A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU30703/00A AU3070300A (en) 1999-02-26 2000-01-10 Method and apparatus for scheduling program code in a computer system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25917899A 1999-02-26 1999-02-26
US09/259,178 1999-02-26

Publications (2)

Publication Number Publication Date
WO2000050991A2 WO2000050991A2 (en) 2000-08-31
WO2000050991A3 true WO2000050991A3 (en) 2000-11-30

Family

ID=22983852

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2000/000081 WO2000050991A2 (en) 1999-02-26 2000-01-10 Method and apparatus for scheduling program code in a computer system

Country Status (2)

Country Link
AU (1) AU3070300A (en)
WO (1) WO2000050991A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003067331A (en) * 2001-08-28 2003-03-07 Matsushita Electric Ind Co Ltd Schedule preparing method, schedule preparing device and schedule preparing program
GB0212176D0 (en) * 2002-05-27 2002-07-03 Radioscape Ltd Stochasitc scheduling in CVM
US7639671B2 (en) 2006-03-07 2009-12-29 Freescale Semiconductor, Inc. Allocating processing resources for multiple instances of a software component
US8856791B2 (en) 2009-01-23 2014-10-07 Imec Method and system for operating in hard real time
CN106095115B (en) * 2016-06-30 2019-05-17 北京智能管家科技有限公司 A kind of application program scheduling processing method and processing device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ALIA ATLAS ET AL.: "Statistical Rate Monotonic Scheduling", PROCEEDINGS OF THE 19TH IEEE REAL-TIME SYSTEMS SYMPOSIUM, 2 December 1998 (1998-12-02) - 4 December 1998 (1998-12-04), pages 123 - 132, XP002144868, ISBN: 0-8186-9212-X, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/iel4/5963/15954/00739737.pdf> [retrieved on 20000809] *
IVERSON M A ET AL.: "Run-time statistical estimation of task execution times for heterogeneous distributed computing", PROCEEDINGS OF THE FIFTH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE DISTRIBUTED COMPUTING (CAT. NO.TB100069), SYRACUSE, NY, USA, 6 August 1996 (1996-08-06) - 8 August 1996 (1996-08-08), Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, pages 263 - 270, XP002144869, ISBN: 0-8186-7582-9, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/iel3/3985/11475/00546196.pdf> [retrieved on 20000809] *
YINGGANG XIE ET AL.: "Efficient admission control for EDF scheduler with statistical QoS guarantee", PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (CAT. NO.97TB100187), LAS VEGAS, NV, USA, 22 September 1997 (1997-09-22) - 25 September 1997 (1997-09-25), Los Alamitos, CA, USA, IEEE Comput. Soc, USA, pages 242 - 247, XP002144870, ISBN: 0-8186-8186-1, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/iel3/4912/13564/00623319.pdf> [retrieved on 20000809] *

Also Published As

Publication number Publication date
AU3070300A (en) 2000-09-14
WO2000050991A2 (en) 2000-08-31

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