WO2000049711A1

WO2000049711A1 - Distortion control

Info

Publication number: WO2000049711A1
Application number: PCT/GB2000/000417
Authority: WO
Inventors: Peter Kenington; Anthony Michael New
Original assignee: Wireless Systems International Limited
Priority date: 1999-02-19
Filing date: 2000-02-10
Publication date: 2000-08-24
Also published as: GB2347033A; AU2449800A; GB9903922D0; GB2347033B

Abstract

The predistorter control circuitry described herein provides amplitude and/or phase control signals for controlling a predistorter used, for example, to linearise a non-linear RF amplifier. When used with such a non-linear RF amplifier, these predistortion control circuits operate by sampling both the pure input to the non-linear RF amplifier (710) and its distorted output (724). These two sampled signals are then squared using detectors (716, 730) having a squaring function. The square of the signal representing the pure input to the RF amplifier to be linearised is then squared again (722) to obtain a signal having fourth order reference terms and the resulting signal is correlated (746, 752) with the square of the signal representing the distorted output of the amplifier to be linearised in order to generate the amplitude and/or phase control signals. The predistorter control circuits may use main tone cancellation processes (344, 352, Figure 3) and may be adapted to cope with low input frequencies (Figure 4).

Description

DISTORTION CONTROL

The present invention relates to controlling predistortion applied to an input to a signal processing means in order to reduce distortion appearing at the output of the signal processing means. More particularly, the present invention relates to controlling predistortion applied to the input of a non-linear amplifier.

A typical format for a generic predistorter is shown in Figure 1. The predistorter in the circuit shown is being used to predistort the RF input to a non-linear power amplifier. A portion of the RF input destined for the amplifier is removed at coupler 110 and supplied to non-linearity generator 112. The non-linearity generator 112 may be of any suitable form. For example, it may be diode based (either attenuator or hybrid configurations), dual-gate Mosfet based, BJT based (either diode connected or conventional), amplifier (either MMIC or discrete) based, or FET devices operating close to pinch-off, or mixer or multiplier based polynomial systems. Non-linearity generators of the latter kind are disclosed in our pending patent applications GB9804745.9 and GB9804835.8. The non-linearity produced is then adjusted by means of phase adjuster 114 and amplitude adjuster 116. The resulting adjusted non-linearity is then amplified by RF amplifier 118, and at combiner 120, is reintroduced to the main portion of the RF input which reaches the combiner by way of time delay 122. The purpose of time delay 122 is to delay the main portion of the RF input by a period equal to the time taken for the portion removed at coupler 110 to negotiate the non-linearity generator 112 and return to combiner 120. For most common forms of amplifier, the non-linearity generator produces a compressive non-linearity to counter the distortion produced by the non-linear power amplifier and the output from RF amplifier 118 must then be arranged to subtract from the output of time delay 122 at combiner 120. On the other hand, if the non-linearity required to compensate for the non-linear power amplifier is expansive, then the output from RF amplifier 118 must be summed with the output from the time delay 122 at the combiner 120.

Figure 1 also shows the three potential control points 1,2 and 3 at which predistorter control can be effected. The control circuitry needed to provide the control inputs for the predistorter is usual complex and often involves narrowband down conversion of the RF signal to be predistorted using local oscillator signals.

The object of the invention is to provide predistortion control which is simpler and which can operate on a wider range of RF input signals.

According to one aspect, the invention consists in a method for reducing distortion of an output signal of signal processing means, by predistorting the input signal to the signal processing means so as to counter the distortion present in the output signal of the signal processing means, and controlling the predistortion of the input signal by squaring the input signal before predistortion to generate a first squared signal, squaring the output of the signal processing means to generate a second squared signal, and processing the first and second squared signals to produce signals for controlling said predistortion.

According to another aspect, the invention comprises apparatus for reducing distortion of an output signal of signal processing means, the apparatus comprising predistortion means for predistorting an input signal to the signal processing means so as to counter the distortion present in the output signal of the signal processing means, first squaring means for forming the square of the input signal before predistortion to generate a first squared signal, second squaring means for forming the square of the output signal of the signal processing means to generate a second squared signal, and control means using the first and second squared signal to produce control signals for controlling the predistortion applied to the input signal by the predistortion means.

In a preferred embodiment, the first and second squaring means are square-law detector circuits.

Preferably, a control signal for the predistorter is produced by squaring the first squared signal and correlating it with the second squared signal. This control signal can be used to control an amplitude adjuster of the predistorting means. Advantageously, the squared first squared signal can be squared and correlated with the square of the second squared signal in order to produce a different control signal. This second control signal can be used to control a phase adjuster of the predistorting means. Certain embodiments of the invention will now be described, by way of example only, with reference to Figures 1 to 7, in which:

Figure 1 is a schematic block diagram of a generic predistorter;

Figure 2 is a schematic block diagram of a broadband predistorter control system;

Figure 3 is a detailed schematic block diagram of an analogue control scheme for a single predistorter variable;

Figure 4 is a schematic block diagram of a modified baseband converter for low and high frequency operation;

Figure 5 is a schematic block diagram of a portion of a hybrid DSP/analogue implementation of a single predistorter variable control scheme;

Figure 6 is a schematic block diagram of an analogue implementation of a control scheme for two predistorter variables; and

Figure 7 is a schematic block diagram of a further analogue implementation of a control scheme for two predistorter variables.

Figure 2 shows a predistorter 200 used to linearise an RF power amplifier 210. The predistorter 200 corresponds to, for example, components 110 to 122 of Figure 1. Control circuitry 212 provides control signals to the predistorter 200 for controlling one or more predistorter variables. A portion of the RF signal to be amplified is removed at coupler 214 and is supplied to square-law detector 216 which feeds a signal to control circuitry 212. Similarly, coupler 218 removes a portion of the RF output from amplifier 210 and feeds it to square-law detector 220 which provides an output to control circuitry 212. The control circuitry 212 uses the signals from the square-law detectors 216 and 220 to produce one or more control signals for the predistorter 200.

In many cases, with a simple predistortion lineariser providing perhaps 10-12dB of distortion reduction, it is not necessary to control both the phase and amplitude of the predistortion precisely. An initial set-up of, say, the phase of the predistortion signal is sufficient when coupled with accurate control of the amplitude signal.

The square-law detectors 216 and 220 can be fabricated by a range of techniques, and can be based on, for example, diode circuits, mixer circuits and analogue multiplier circuits.

The input and output RF signals are sampled by low distortion square-law detectors 216 and 220 to provide baseband signals. The detected RF input signal provides a reference for the control processing and the detected RF output signal provides a measure of the amount of distortion remaining after predistortion linearisation has taken place.

Figure 3 shows a detailed view of the control circuitry 212 and square-law detectors 216,220 of Figure 2. The pure RF input sampled from the main amplifier input by coupler 214 (Figure 2) is supplied to input 300 of the control circuitry, and the distorted RF output sampled from the main amplifier output at coupler 218 (Figure 2) is supplied to input 310. The pure RF input is compensated at delay line 312 and its amplitude is detected at 314. The distorted RF output is attenuated by pin-diode attenuator 316 and is supplied to amplitude detector 318. The outputs from amplitude detectors 314 and 318 are furnished to a differential amplifier or subtractor 320 which provides an output to integrator 322 which, in turn, provides a control signal for the pin-diode attenuator 316. The amplitude detector 318, the subtractor 320, the integrator 322 and the pin-diode attenuator 316 comprise an amplitude correction loop. The delayed pure RF input from delay line 312 is combined at 324 with the distorted RF output as attenuated by pin-diode attenuator 316. Combiner 324 performs a controlled subtraction of the RF input from the attenuated distorted RF output. This reduces the level of the unwanted second order component appearing in the distortion sample. The subtraction performed by the combiner 324, and the action of a main tone cancellation loop (described below) substantially reduce the dynamic range required from the following correlation process (described below) and the level of unwanted correlation.

The pure RF input from 300 is also sampled at square-law detector 326 (equivalent to detector 216 in Figure 2) which outputs second order signals at baseband frequencies which are passed by baseband filter 328 and subsequently amplified at 330. Similarly, the result of the RF carrier cancellation at 324 is, after amplification at 332, detected by square-law detector 334. The square-law detector 334 outputs a second order component (from the amplified main signals of the distorted RF output sample from the main amplifier output) and also a fourth order component (from the detected third order intermodulation distortion appearing in the distorted RF output sampled from the main amplifier output). The output from square-law detector 334 is then filtered by baseband filter 336 and is ultimately supplied to one input of mixer 338, which together with integrator 340 comprises the intermodulation distortion (MD) correlator. The second order signals passed by baseband filter 328 are supplied to each of two inputs of mixer 342 which performs a squaring function to produce a fourth order output to the other input of the mixer 338 of the IMD correlator. The fourth order reference signal produced by the squaring mixer 342 from the output of square-law detector 326 is then correlated with the fourth order component of the output from square-law detector 334 by the IMD correlator to produce a control output for the amplitude adjuster of the predistorter. The amplitude adjuster varies the amount of complementary distortion introduced by the predistorter, and hence controls the degree of correction produced. In this way, the level of correction may be maintained at an optimum setting irrespective of temperature changes, amplifier loading variations or component ageing variations within the amplifier or the predistorter.

A main tone cancellation loop acts on the output of square-law detector 334 prior to its supply to the IMD correlator. The loop is formed by mixer 344 which correlates the outputs of the two square-law detectors 326 and 334 and provides an output signal to integrator 346. The output from this integrator is supplied to a control input of a variable gain amplifier 348. The output of the square-law detector 326 is supplied to the main input of the variable gain amplifier 348 and its output is combined with the output of square-law detector 334 at 350 in order to complete the main tone cancellation loop. The purpose of the main tone cancellation loop, like the RF carrier cancellation discussed above, is to reduce the level of unwanted second order components appearing in the distorted RF output samples from the main amplifier output as provided to input 310 of the control circuitry. These two processes substantially reduce the dynamic range required for the correlation process and the level of unwanted correlation.

Final cancellation is also performed on the residual second order component appearing at the output of the squaring mixer 342. This uses another main tone cancellation loop comprising a mixer 352 which receives inputs from the output of the squaring mixer 342 and the square-law detector 326. The output of mixer 352 is integrated by integrator 354 to provide a DC signal for injection to mixer 342 to achieve main tone cancellation. Squaring mixer 342 therefore yields a signal very heavily dominated by fourth order products, such that unwanted correlation between second order components in the signals supplied to the IMD correlator is virtually eliminated. It is possible to remove the RF cancellation process or either of the main tone cancellation loops, or indeed all three processes, without effecting the intrinsic operation of the circuit, however, its dynamic range may then be compromised.

The degree of cancellation achieved by these various processes will determine the minimum distortion level which can be achieved by the system. If a lower IMD specification is required, one or more of these processes may be eliminated to create an even simpler system.

Figure 4 shows a modification to the system of Figure 3 which enables it to cope with low carrier frequencies. A problem occurs when attempting to use a square-law detector designed for wide instantaneous channel bandwidths at low frequencies. The problem is that the detector begins to detect the carriers themselves rather than the overall modulation contained on the carriers or within the band of interest (if multiple carriers are used). Consider, for example, a square-law detector designed for a channel/multi-carrier bandwidth of 30MHz. Once the RF frequency of the carrier(s) falls close to or within this bandwidth (e.g. one or more carriers around 20MHz) then the carriers themselves will be detected. This will result in control system malfunction as it is not receiving the correct information.

In Figure 4, circuit components carried over from the embodiment of Figure 3 have been given the same reference numerals. It will be appreciated that circuit path 300, 326, 328, 330, now includes a high pass filter 400. The circuit path just described is used for high frequency inputs but when low frequency inputs are present, a switch 418 operates via amplifiers 410, 414, to power down one and power up the other so as to switch from this circuit path to a parallel circuit path comprising a baseband filter 412, thus bypassing the square-law detector 326 altogether. This allows the signal processing to operate on the RF signals directly and restores operation to the system. It will be appreciated that a bypass path can similarly be provided for the square-law detector 334 which handles the distorted RF output sampled from the main amplifier output (provided to input 310 in Figure 3).

It is possible to use a digital signal processor (DSP) to perform some or all of the processing outlined above with further advantage over a purely analogue implementation. For narrow linearisation bandwidths, it is possible to feed the outputs from the broadband detectors (the square-law detectors) directly into the analogue to digital converters of the DSP, with all of the subsequent processing (i.e. squaring, correlation, integration, etc.) taking place numerically within the DSP. This has the significant advantage that DC offsets and the drift of component values, amplifier gains, etc., are eliminated. This results in improved long-term performance. This form of DSP implementation is ideally suited to handset applications, where space is at a premium, and, in may cases, only a single narrowband channel needs to be linearised at any given point in time. However, for large linearisation bandwidths, a fast DSP would be required.

Figure 5 shows a portion of a hybrid DSP/analogue implementation of the wide band predistorter control system, which allows a slow DSP to be used with large bandwith signals. This implementation combines some of the benefits of digital signal processing (no DC offsets, flexibility of processing, etc.) with the wide linearisation bandwidth capability of the analogue implementation. The DSP takes over the integration function of the control system at each stage. The DSP is incorporated into the circuitry of Figure 3 so that integrators 510, 512 and 514 perform the functions of integrators 346, 354 and 340, respectively, as shown in the circuitry of Figure 3.

Using a DSP to perform the integration processes allows for calibration and offset removal to be undertaken periodically as necessary. This has two advantages. Firstly, it allows gross offsets, caused by component manufacturing imperfections (for example, in the correlation multipliers/mixers) to be eliminated in a one-off calibration, for example, on manufacture. Secondly, it allows long-term offset drifts (e.g. for example, resulting from temperature changes or component ageing) to be eliminated periodically. This latter procedure operates as follows. An initialisation pulse 516 emanating from the DSP disables both the square-law detectors sampling the RF input and output (e.g. by removing their power supply). The same pulse also enables latches 518, 520, 522, at each of the DSP inputs such that the latches sample and store the DSP inputs when the square-law detectors are deactivated. The values stored by the latches represent the correlator offsets and, when the correlators are re-enabled upon cessation of the initialisation pulse, the correlator offsets stored in the latches may be subtracted from the normal correlator outputs, within the DSP. The initialisation process can be repeated at appropriate intervals, in order to compensate for continual drift over time and with temperature.

The circuit shown in Figure 6 is a version of the broadband predistorter control circuitry shown in Figure 3 modified to provide a phase control signal for the predistorter. The phase control is based on detecting the phase quadrature component of the signal from square-law detector 334 (Figure 3). This is achieved by squaring, at mixers 610 and 612 respectively, the outputs of square-law detector 614 and squaring mixer 616, and correlating the resulting outputs using mixer 618 and integrator 620 to produce the phase control output for the predistorter. The squaring processes performed by mixers 610 and 612 converts the phase quadrature signal from square-law detector 614 into a phase inversion of its double frequency component which is detected by the correlating mixer 618 and the integrator 620, avoiding the need for a broadband 90 degree phase shift of one of the square-law detector outputs which would be difficult to realise in analogue hardware. The function of integrator 620 could be incorporated in a DSP in the case of a hybrid DSP/analogue control circuit like Figure 5.

Figure 7 shows an alternative version of a predistorter control circuit for controlling two predistorter variables (amplitude and phase in this instance). The circuitry shown in this figure eliminates the RF main-tone cancellation processes used in the circuitry of Figures 4 and 6 and hence is more suitable for low dynamic range applications, although a combination of the concepts shown in Figures 6 & 7 with yield a high dynamic range system if required. As in previous embodiments of the predistorter control circuitry, the arrangement of Figure 7 samples the pure RF input supplied to the RF amplifier to be linearised, and also the distorted RF output from this amplifier undergoing linearisation. These signals are then squared using baseband detectors, e.g. square-law detectors, and the squared pure RF input is squared a further time and the resulting signal, containing fourth order reference components, is quadrature-correlated with the squared distorted RF amplifier output containing fourth order distortion components, in order to generate the amplitude and phase control signals.

In more detail, the pure RF input to the amplifier to be linearised is sampled at 710, amplified at 712, attenuated by controlled variable attenuator 714 and supplied to baseband detector 716, which forms the square of its input. Optionally, a delay line can be provided between the sampling point 710 and the detector 716. The output from baseband detector 716 is sampled by level detector 718 (which is a precision rectifier), and the output of the level detector is supplied to integrator 720 which provides a control input to the variable attenuator 714, thus completing a level control loop for controlling the output of the baseband detector 716. The output of the baseband detector 716 is then squared using mixer 722 and the resulting signal is used to generate the amplitude and phase control signals as will be described later.

The distorted RF output of the amplifier to be linearised is sampled by the predistorter control circuitry at 724 and, like the signal supplied to 710, this signal is amplified, at 726, attenuated by variable attenuator 728 and supplied to baseband detector 730, which, like baseband detector 716, has a squaring characteristic. To cancel the presence of the main tone from the output of baseband detector 730, the levelled output of baseband detector 716 is combined at 732. The variable attenuator 728 is controlled by the output of integrator 738, which operates on the output of mixer 740, to which are input the outputs of baseband detector 716 and amplifier 736. The signal resulting from amplifier 736, containing terms representative of third order distortion in the output of the RF amplifier to be linearised, is then used to produce the amplitude and phase control signals as described below.

The outputs of squarer 722 and amplifier 736, the results of the reference and distortion branches respectively, are low-pass filtered at 742 and 744 and supplied as inputs to mixer 746. The output of mixer 746 is supplied to integrator 748 which produces the amplitude control signal as its output.

The same two signals, the outputs of amplifier 736 and squaring mixer 722 are then manipulated to achieve a 90° phase shift between them. In this embodiment, this is achieved using 90° phase difference filter 750 (an all-pass filter). The outputs of filter 750 are supplied to mixer 752, the output of which is integrated by integrator 754 to generate the phase control signal.

The 90° phase shift in the phase control path ensures that the phase control signal is orthogonal to the amplitude control signal, and this allows the two control signals to be operated independently. This 90° phase shift could be provided in other ways. For example, it is possible to substitute the all-pass filter 750 with a matched bandpass filter arrangement, but although this will provide a degree of orthogonality between the amplitude and phase control signals, it will not approach the broadband performance provided by all-pass filter 750. Use of non-ideal phase shift networks such as a matched bandpass filter arrangement result in a greater degree of interaction between the amplitude and phase control signals which in turn leads to a longer lead-in time for the control circuit and a restricted range of tone spacing for which control may be achieved. However, this latter restriction may not be important in many systems, since modulated signals will generate a range of baseband signals on which acceptable control may be based. A subset of these may be sufficient to provide the required control.

The principal advantage of the predistorter control circuitry of Figure 7 over that shown in Figure 6 is the improvement of the signal to noise ratio for the signals on which control is based. The additional squaring processes required in Figure 6 can lead to a lower signal to noise ratio for the phase control signal and hence to lower overall control precision.

Claims

1. Apparatus for reducing distortion of an output signal of signal processing means, the apparatus comprising predistortion means for predistorting an input signal to the signal processing means so as to counter the distortion present in the output signal of the signal processing means, first squaring means for forming the square of the input signal before predistortion to generate a first squared signal, second squaring means for forming the square of the output of the signal processing means to generate a second squared signal, and control means using the first and second squared signals to produce control signals for controlling the predistortion applied to the input signal by the predistortion means.

2. Apparatus according to claim 1, further comprising third squaring means for squaring the first squared signal to generate a quartic signal.

3. Apparatus according to claim 1 or claim 2, further comprising a first correlating means for correlating the quartic signal with the second squared signal to produce a first predistorter control signal.

4. Apparatus according to claim 3, wherein the first correlating means comprises first mixing means for mixing the quartic signal and the second squared signal, and integrating means for integrating the output of the first mixing means to produce the first predistorter control signal.

5. Apparatus according to any preceding claim, further comprising control signal generating means which uses the quartic and second squared signals to generate a second predistorter control signal.

6. Apparatus according to any preceding claim, further comprising delay means for delaying the input signal prior to its supply to the first squaring means.

7. Apparatus according to any preceding claim, wherein the first and second squaring means are square-law detector circuits.

8. Apparatus according to any one of claims 3 to 7, wherein the first predistorter control signal is a predistorter amplitude control signal.

9. Apparatus according to any one of claims 5 to 8, wherein the second predistorter control signal is a predistorter phase control signal.

10. Apparatus according to any preceding claim, further comprising a first cancellation means for removing the main tone from the quartic signal.

11. Apparatus according to claim 10, wherein the first cancellation means comprises second mixing means for mixing the first squared signal and the quartic signal and integrating means for integrating the output of the second mixing means and injecting a dc signal into the third squaring means.

12. Apparatus according to any preceding claim, further comprising second cancellation means for cancelling a carrier component in the output signal sampled from the output of the signal processing means.

13. Apparatus according to claim 12, wherein the second cancellation means comprises first attenuating means for attenuating the output signal and combining means for combining the attenuated output signal with the input signal.

14. Apparatus according to claim 13, wherein the second cancellation means further comprises attenuation control means for controlling the degree of attenuation applied by the first attenuating means to the output signal on the basis of the detected amplitudes of the input signal and the attenuated output signal.

15. Apparatus according to any preceding claim, further comprising third cancellation means for removing the main tone from the second squared signal.

16. Apparatus according to claim 15, wherein the third cancellation means comprises variable amplifying means.

17. Apparatus according to any preceding claim, further comprising fourth and fifth squaring means for forming the squares of the quartic and second squared signals respectively.

18. Apparatus according to claim 17, further comprising second correlating means for generating a second predistorter control signal, the second correlating means comprising second mixing means for mixing the outputs of the fourth and fifth squaring means and integrating means for integrating the output of the second mixing means to produce the second predistorter control signal.

19. Apparatus according to any preceding claim, further comprising bypassing means for selectively bypassing the first and/or second squaring means.

20. Apparatus according to any one of claims 1 to 9, comprising second attenuating means for attenuating the input signal prior to the first squaring means.

21. Apparatus according to claim 20, further comprising first level control means for controlling the degree of attenuation applied by the second attenuating means to the input signal by using the output of the first squaring means.

22. Apparatus according to any one of claims 1 to 9, 20 or 21, further comprising third attenuating means for attenuating the output signal prior to the second squaring means.

23. Apparatus according to claim 22, further comprising second level control means for controlling the degree of attenuation applied by the third attenuating means to the output signal by using the output of the second squaring means.

24. Apparatus according to claim 23, wherein the second level control means further comprises mixing means for mixing the first squared signal into the second squared signal prior to the use of the latter for controlling the third attenuating means.

25. Apparatus according to any one of claims 1 to 9, 20 to 23 or 24, further comprising first cancellation means for cancelling the main tones present in the second squared signal.

26. Apparatus according to claim 25, wherein the first cancellation means comprises means for combining the first squared signal into the second squared signal.

27. Apparatus according to claim 3, or any one of claims 4 to 9, 20 to 25, or 26, when dependent on claim 3, further comprising low pass filtering means for low pass filtering the quartic and second squared signals prior to the use in the first correlating means.

28. Apparatus according to any one of claims 1 to 9, 20 to 26 or 27, further comprising phase shifting means for generating a 90° phase difference between the quartic and second squared signals.

29. Apparatus according to claim 28, wherein the phase shifting means comprises a 90° phase difference filter.

30. Apparatus according to claim 29, wherein the 90° difference filter comprises an all-pass filter.

31. Apparatus according to any one of claims 28 to 30, further comprising second correlating means for correlating the phase-differenced quartic and second squared signals to produce a second predistorter control signal.

32. Apparatus according to claim 31, wherein the second correlator means comprises mixing means for mixing together the phase-differenced quartic and second squared signals and integrating means which integrates the output of the mixer means to produce the second predistorter control signal.

33. Apparatus according to any preceding claim, wherein a digital signal processor is used to perform any integration process.

34. Apparatus according to claim 33, wherein the digital signal processor has offset removal means for removing an offset associated with an integration process.

35. A method for reducing distortion of an output signal of signal processing means, by predistorting the input signal to the signal processing means so as to counter the distortion present in the output signal of the signal processing means, and controlling the predistortion of the input signal by squaring the input signal before predistortion to generate a first squared signal, squaring the output of the signal processing means to generate a second squared signal, and processing the first and second squared signals to produce signals for controlling said predistortion.

36. A method according to claim 35, further comprising the step of squaring the first squared signal to generate a quartic signal.

37. A method according to claim 35 or claim 36, further comprising the step of correlating the quartic signal with the second squared signal to produce a first predistorter control signal.

38. A method according to any one of claims 35 to 37, further comprising a first cancellation step for removing the main tone from the quartic signal.

39. A method according to any one of claims 35 to 38, further comprising a second cancellation step for cancelling a carrier component in the output signal sampled from the output of the signal processing means.

44. A method according to any one of claims 35 to 39, further comprising a third cancellation step for removing the main tone from the second squared signal.

41. A method according to any one of claims 35 to 40, further comprising the step of squaring the quartic and second squared signals.

42. A method according to claim 41, further comprising a second correlating step for generating a second predistorter control signal by mixing the squared quartic and squared second squared signal.

43. A method according to any one of claims 35 to 42, further comprising the step of selectively bypassing the step of squaring the input signal and/or the output signal.

44. A method according to any one of claims 35 to 37, further comprising the step of applying controlled attenuation to the input and output signals before they are squared.

45. A method according to any one of claims 35 to 37 or 44, further comprising a first cancellation step for cancelling main tones present in the second squared signal.

46. A method according to any one of claims 35 to 37, 44, 45 or 46, further comprising the step of generating a 90° phase-difference between the quartic and squared signals.

47. A method according to claim 46, further comprising the step of correlating the phase-differenced quartic and second squared signals to produce a second predistorter control signal.

48. A method according to any one of claims 35 to 47, comprising the step of using a digital signal processor to perform any integration process.

49. A method according to claim 48, wherein the step of using a digital signal processor to perform any integration process further comprises the step of removing an offset associated with an integration process.