WO2000038385A1 - Quadrature receiver, communication system, signal processor, method of calculating direct current offset, and method of operating a quadrature receiver - Google Patents

Quadrature receiver, communication system, signal processor, method of calculating direct current offset, and method of operating a quadrature receiver Download PDF

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Publication number
WO2000038385A1
WO2000038385A1 PCT/US1999/030803 US9930803W WO0038385A1 WO 2000038385 A1 WO2000038385 A1 WO 2000038385A1 US 9930803 W US9930803 W US 9930803W WO 0038385 A1 WO0038385 A1 WO 0038385A1
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WO
WIPO (PCT)
Prior art keywords
signal
vector
quadrature
direct current
offset
Prior art date
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PCT/US1999/030803
Other languages
French (fr)
Inventor
Steffen J. Beyme
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Koninklijke Philips Electronics N.V.
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Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP99968953A priority Critical patent/EP1062781A1/en
Priority to JP2000590352A priority patent/JP2002533999A/en
Publication of WO2000038385A1 publication Critical patent/WO2000038385A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/063—Setting decision thresholds using feedback techniques only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
    • H03D3/008—Compensating DC offsets

Definitions

  • QUADRATURE RECEIVER COMMUNICATION SYSTEM, SIGNAL PROCESSOR, METHOD OF CALCULATING DIRECT CURRENT OFFSET, AND METHOD OF OPERATING A QUADRATURE RECEIVER
  • the present invention relates to a quadrature receiver, communication system, signal processor, method of calculating direct current offset, and method of operating a quadrature receiver.
  • Radio frequency (RF) receivers which utilize quadrature demodulation techniques are known in the art.
  • Some conventional digital quadrature receiver designs include a variable amplification stage followed by a downconversion stage.
  • a received radio frequency (RF) signal is typically applied to a variable gain amplifier to selectively adjust the gain of the received signal depending upon the strength of the signal received at the antenna.
  • An automatic gain control (AGC) component can be utilized to control the variable gain amplifier to account for varied signal strengths at the antenna of the receiver.
  • the output of the variable gain amplifier is thereafter provided to a downconverter in such prior art designs.
  • Downconversion includes analog processing, such as mixing, to downconvert the received radio frequency signal from an intermediate frequency (IF) to baseband. Following the downconversion operations, the received signal is low-pass filtered and conditioned for subsequent analog-to-digital conversion.
  • IF intermediate frequency
  • D.C. direct current offset
  • I in-phase
  • Q quadrature
  • the direct current offset within the in-phase and quadrature channels can cause signal distortion in the demodulator of the receiver. Additionally, direct current offset often results in misoperation of the automatic gain control portion of the quadrature receiver.
  • Direct current portions of the in-phase and quadrature channels or the complex direct current respectively contain carrier information in some modulation schemes (e.g., constant envelope modulation schemes such as frequency modulation/frequency-shift keying (FM/FSK) in a dual-mode code division multiple access/advanced mobile phone system (CDMA/ AMPS) architecture).
  • modulation schemes e.g., constant envelope modulation schemes such as frequency modulation/frequency-shift keying (FM/FSK) in a dual-mode code division multiple access/advanced mobile phone system (CDMA/ AMPS) architecture.
  • Averaging over the in-phase and quadrature channels does not reliably yield the direct current offset or feedthrough value in such modulation schemes, but rather provides the sum of the actual direct current of the complex envelope content and the unwanted direct current feedthrough yielding an ambiguous result.
  • Exemplary prior art methods for minimizing effects of direct current feedthrough include offsetting or modulating the local oscillator of the downconverter. These conventional techniques are successful to some degree in minimizing
  • Fig. 1 is a functional block diagram of a communication system.
  • Fig. 2 is a functional block diagram of an exemplary quadrature receiver according to the present invention.
  • Fig. 3 is an illustrative representation of a complex envelope of a received wireless communication signal with constant envelope modulation.
  • Fig. 4 is a functional block diagram of a feedback structure for reducing direct current offset within in-phase and quadrature signals.
  • Fig. 5 is a functional block diagram of a feedforward structure for reducing direct current offset within in-phase and quadrature signals.
  • Fig. 6 is a flow chart illustrating an exemplary methodology for determining direct current offset. Best Modes for Carrying Out the Invention and Disclosure of Invention
  • the present invention provides a quadrature receiver comprising: a downconverter configured to convert a wireless communication signal into a baseband signal; and an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
  • the present invention provides a quadrature receiver comprising: a downconverter configured to convert a wireless communication signal into a baseband signal; an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled values, and to provide a direct current offset signal from the plural sampled values; and a summer coupled with the downconverter and the I/Q offset processor and configured to combine the baseband signal and the direct current offset signal.
  • Another aspect of the present invention provides a signal processor of a quadrature receiver configured to calculate direct current offset, the signal processor comprising circuitry configured to sample a baseband signal to provide plural sampled vectors, to calculate a difference vector from the sampled vectors, to calculate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
  • a communication system comprising: a transmitter configured to output a wireless communication signal; and a quadrature receiver configured to receive the wireless communication signal and including: a downconverter configured to convert the wireless communication signal into a baseband signal; an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled values, and to provide a direct current offset signal from the plural sampled values; and a summer coupled with the downconverter and the I/Q offset processor and configured to combine the baseband signal and the direct current offset signal.
  • the invention provides a quadrature receiver comprising: an antenna configured to receive a constant envelope modulated wireless communication signal; a variable gain amplifier coupled with the antenna and configured to adjust the gain of the wireless communication signal; a downconverter coupled with the variable gain amplifier and configured to convert the wireless communication signal into in-phase and quadrature analog baseband signals; plural low-pass filters coupled with the downconverter and configured to filter frequency components above a predetermined cut-off frequency from the in-phase and quadrature analog baseband signals; plural analog-to-digital converters coupled with the low-pass filters and configured to convert the in-phase and quadrature analog baseband signals to in-phase and quadrature digital baseband signals; an I/Q offset processor coupled with the analog-to-digital converters and configured to sample the in-phase and quadrature digital baseband signals to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate an orthogonal vector from the difference vector, to generate a scaled vector from the orthogonal vector, and to sum
  • Another aspect provides a method of calculating direct current offset comprising: receiving a wireless communication signal; downconverting the wireless communication signal following the receiving; sampling the wireless communication signal providing plural sampled vectors; calculating a difference vector from the sampled vectors; calculating a scaled vector from the difference vector; and summing the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
  • Another aspect of the present invention provides a method of operating a quadrature receiver comprising: receiving a wireless communication signal within a quadrature receiver; downconverting the wireless communication signal following the receiving providing in-phase and quadrature baseband signals; sampling the in-phase and quadrature baseband signals providing plural sampled values; calculating direct current offset signals from the plural sampled values; and subtracting the direct current offset signals from the in-phase and quadrature baseband signals.
  • a communication system 1 including a transmitter 8 and a quadrature receiver 10 is depicted.
  • Transmitter 8 and quadrature receiver 10 can be -3 configured for digital communications utilizing at least one wireless communication signal 1 1.
  • communication system 1 utilizes a frequency modulation/frequency-shift keying (FM/FSK) modulation scheme in a dual- mode code division multiple access/advanced mobile phone system (CDMA/AMPS) architecture.
  • FM/FSK frequency modulation/frequency-shift keying
  • CDMA/AMPS dual- mode code division multiple access/advanced mobile phone system
  • Other configurations of communication system 1 are possible.
  • the illustrated quadrature receiver 10 comprises a radio receive path 12 coupled with a baseband processor 14.
  • Radio receive path 12 is additionally coupled with an antenna 16 configured to receive wireless communication signals.
  • Exemplary wireless communication signals comprise frequency modulated (FM) radio frequency (RF) signals.
  • Radio receive path 12 is also coupled with external circuitry 18 which can comprise processing circuitry, handset circuitry including a speaker, and/or any other desired circuitry.
  • Signals received by antenna 16 are applied to radio receive path 12. Initially, such received signals can be processed prior to application to receive path 12. For example, the received signals may be applied to a low noise amplifier (LNA), intermediate frequency (IF) converter, and band-pass filter prior to application to receive path 12.
  • LNA low noise amplifier
  • IF intermediate frequency
  • band-pass filter prior to application to receive path 12.
  • Radio receive path 12 includes a variable gain amplifier 20, downconverter 22, local oscillator 24, low-pass filters 26, 27, analog-to-digital converters (ADCs) 28, 29, digital-to-analog converters (DACs) 30, 31 , and summers 32, 33.
  • the illustrated downconverter 22 comprises plural mixers 34, 35 and a phase shifter 36.
  • the depicted baseband signal processor 14 includes an I/Q offset processor 40, automatic gain control (AGC) circuitry 42 and a downstream processor 44.
  • I/Q offset processor 40, automatic gain control circuitry 42 and downstream processor 44 are individually coupled with radio receive path 12.
  • VGA Variable gain amplifier 20 receives wireless communication signals from antenna 16 during normal operations of quadrature receiver 10.
  • Variable gain amplifier 20 is configured to selectively adjust the gain of the wireless communication signals.
  • Variable gain amplifier 20 is operable to output intermediate frequency (IF) communication signals to downconverter 22.
  • IF intermediate frequency
  • Downconverter 22 provides downconversion operations which convert the wireless communication signals into in-phase (I) and quadrature (Q) analog baseband signals.
  • local oscillator 24 outputs a periodic waveform to phase shifter 36 for application to respective mixers 34, 35.
  • Received wireless communications signals are also applied to both mixers 34, 35.
  • Mixers 34, 35 operate to utilize the received periodic waveform to downconvert the intermediate frequency wireless communication signal into respective in-phase and quadrature analog baseband signals.
  • the in-phase and quadrature baseband signals are applied to respective low-pass filters 26, 27.
  • Low-pass filters 26, 27 are individually configured to filter frequency components above a predetermined cut-off frequency from the in-phase and quadrature analog baseband signals.
  • low pass filters 26, 27 are configured to filter frequencies above 15 kHz in AMPS mode.
  • the filtered in-phase and quadrature baseband signals are applied to respective summers 32, 33.
  • the in-phase and quadrature analog baseband signals are converted to digital signals within respective analog-to-digital converters 28, 29.
  • the in-phase and quadrature digital baseband signals are outputted from radio receive path 12 to baseband processor 14.
  • I/Q offset processor 40 is operable to calculate in-phase (I o fset ) and quadrature
  • Q offset digital direct current offset signals as described in detail below.
  • the calculated in-phase and quadrature direct current offset signals can be utilized to minimize direct current offset or feedthrough resulting from the downconversion operations.
  • the calculated in-phase and quadrature direct current offset signals are outputted from I/Q offset processor 40 to radio receive path 12. More specifically, the in-phase and quadrature direct current offset signals are applied to respective digital-to-analog converters 30, 31 of radio receive path 12. Digital-to-analog converters 30, 31 individually operate to convert the in-phase and quadrature digital direct current offset signals into in-phase and quadrature analog direct current offset signals.
  • Quadrature receiver 10 includes a feedback configuration for reducing the direct current offset within the in-phase and quadrature baseband signals. As illustrated, the in-phase and quadrature analog direct current offset signals are applied to respective summers 32, 33.
  • Summers 32, 33 are configured to combine the in-phase and quadrature analog baseband signals and the respective in-phase and quadrature analog direct current offset signals.
  • summers 32, 33 individually operate to subtract the in-phase and quadrature analog direct current offset signals from the respective in-phase and quadrature baseband analog signals outputted from low pass filters 26, 27.
  • the in-phase and quadrature analog signals outputted from summers 32, 33 are applied to respective analog and digital converters 28, 29 for application to I/Q offset 3 processor 40, automatic gain control circuitry 42 and downstream processor 44.
  • the in- phase and quadrature signals outputted from summers 32, 33 preferably include minimal direct current offset.
  • Automatic gain control circuitry 42 receives the digital in-phase and quadrature signals outputted from respective summers 32, 33 and analog- to-digital converters 28, 29. Automatic gain control circuitry 42 is configured to control variable gain amplifier 20 responsive to the received digital in-phase and quadrature signals.
  • Downstream processor 44 receives the digital in-phase and quadrature signals from analog-to-digital converters 28, 29. Downstream processor 44 can be configured to provide further signal processing including I and Q combination operations, demodulation operations, decoding operations and/or detection operations in an exemplary embodiment. The output of downstream processor 44 is applied to external circuitry 18.
  • I/Q offset processor 40 for calculating direct current offset or feedthrough utilizes a-priori knowledge about the geometrical shape of the envelope as described below with reference to Fig. 3. Initially, I/Q offset processor 40 is configured to sample the in-phase and quadrature baseband signals to provide plural sample values. Exemplary sample values are vectors which individually include an in-phase value and a quadrature value. I/Q offset processor 40 is configured to calculate direct current offset or feedthrough from the sampled values utilizing a-priori knowledge.
  • I/Q offset processor 40 calculates a difference vector from the sampled values and an orthogonal vector from the difference vector. I/Q offset processor 40 scales the orthogonal vector providing a scaled vector utilizing a-priori knowledge. Thereafter, I/Q offset processor 40 sums at least one of the sampled values, the difference vector and the scaled vector to calculate the in-phase and quadrature direct current offset values or signals.
  • the in-phase and quadrature direct current offset are subtracted from, or otherwise combined with, the in-phase and quadrature baseband signals to remove or minimize the direct current offset or feedthrough within the in- phase and quadrature baseband signals applied to baseband processor 14 and external circuitry 18.
  • a complex envelope of the received wireless communication signal is a baseband signal represented by separate in-phase and quadrature channels.
  • the in-phase channel comprises the real portion of the signal and the quadrature channel comprises the imaginary portion of the signal.
  • the in-phase and quadrature signals are constant envelope modulated signals inasmuch as frequency modulation techniques only adjust the instantaneous frequency deviation of the communicated signal. Other modulation schemes which provide constant envelope modulated signals can be utilized.
  • the complex envelope has a nominal gain R as a result of the constant envelope modulated signals (deviations from gain R may occur prior to setting of the automatic gain control circuitry).
  • the complex envelope of the baseband signals may be represented by a circle 50 with a radius R which corresponds to the gain.
  • An unknown offset r 0 of circle 50 corresponds to the direct current offset or feedthrough.
  • the center of circle 50 representing the direct current offset can be determined.
  • I/Q offset processor 40 is configured to sample the in-phase and quadrature baseband signals to provide I, Q sample pair values r resort r, which are represented as the following vectors in the described embodiment:
  • I/Q offset processor 40 is configured to generate a difference vector u from the sampled vectors r consult r r
  • an orthogonal vector o having the magnitude of vector u can be computed by rotating vector u using a matrix M wherein
  • orthogonal vector o Mu
  • a scaled vector v is determined by scaling the orthogonal vector o by a factor K wherein
  • the scaled vector v is perpendicular to the difference vector u.
  • the direct current offset r 0 can be calculated by summing the difference vector u, the scaled vector v and one of the sampled values to provide the direct current offset. Such may be represented by
  • a feedback control loop typically utilizes one pole which is realized by an integrator with the transfer function (az/z-1) whereby a is the loop gain.
  • exemplary feedback and feedforward structures 58, 70 for reducing direct current offset within in-phase and quadrature baseband signals are illustrated.
  • the depicted structures 58, 70 are individually utilized in the in-phase signal path and the quadrature signal path in the described embodiment.
  • the input baseband signal includes desired information r k plus direct current offset r 0 .
  • the baseband signal is initially applied to a summer 60 (summer 60 can comprise one of summers 32, 33 depicted in Fig. 2) of feedback structure 50.
  • I/Q offset processor 40 is utilized to estimate the direct current offset
  • I/Q offset processor 40 calculates the direct current offset as a function of r cake r f and R. Thereafter, the determined direct current offset is integrated within an integration function block 64. I/Q offset processor 40 can also be configured to perform the integration functions of block 64.
  • the output of integrator 64 comprises direct current offset r 0 which is applied to summer 60 and subtracted from the incoming baseband signal comprising desired information r k plus the direct current offset r 0 .
  • the depicted feedback structure 58 effectively cancels the direct current offset or feedthrough by driving error signal ⁇ to 0.
  • the alternative feedforward structure 70 for reducing direct current offset within the baseband in-phase and quadrature signals is illustrated.
  • the baseband signal including the desired information r k and the direct current offset r 0 is applied to a summer 72 and function block 74.
  • I/Q offset processor 40 is utilized to estimate the direct current offset in function block 74 using the previously described process.
  • I/Q offset processor 40 calculates the direct current offset as a function of ⁇ , and R.
  • the estimated direct current offset is applied to low-pass filter 76 and a time-average value r 0 of the direct current offset is outputted from low-pass filter 76.
  • the calculated direct current offset r 0 is subtracted from the baseband signal within summer 72.
  • the quadrature receiver 10 depicted in Fig. 2 is configured as a feedback structure, in an alternative embodiment it is configured as a feedforward structure to implement direct current offset reduction operations.
  • Both the feedback and feedforward methods of reducing direct current offset from the baseband signal are numerically robust over a reasonable range of input values and is preferably utilized with fixed-point digital signal processing (DSP) inasmuch as the involved operations may be implemented within I/Q offset processor 40.
  • DSP fixed-point digital signal processing
  • I/Q offset processor 40 can be configured to execute operational code to provide the illustrated steps.
  • I/Q offset processor 40 performs step S10 wherein the downconverted baseband signal is sampled to provide I, Q sample pair vectors as previously described. Thereafter, I/Q offset processor 40 calculates a difference vector from the sampled values or vectors at step S12. At step S14, I/Q offset processor 40 calculates an orthogonal vector by rotating the difference vector and calculates a scaled vector from the orthogonal vector. At step SI 6, I/Q offset processor 40 determines the direct current offset using the difference vector, the scaled vector and one of the sampled vectors. I/Q offset processor 40 can thereafter perform additional signal processing such as integration operations or low-pass filtering operations if desired.

Abstract

A quadrature receiver (10) including a downconverter (22) configured to convert a wireless communication signal into a baseband signal; and an I/Q offset processor (40) coupled with the downconverter (22) and configured to sample the baseband signal to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal. A method of calculating direct current offset including receiving a wireless communication signal; downconverting the wireless communication signal following the receiving; sampling the wireless communication signal providing plural sampled vectors; calculating a difference vector from the sampled vectors; calculating a scaled vector from the difference vector; and summing the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.

Description

3 DESCRIPTION
QUADRATURE RECEIVER, COMMUNICATION SYSTEM, SIGNAL PROCESSOR, METHOD OF CALCULATING DIRECT CURRENT OFFSET, AND METHOD OF OPERATING A QUADRATURE RECEIVER
Technical Field
The present invention relates to a quadrature receiver, communication system, signal processor, method of calculating direct current offset, and method of operating a quadrature receiver.
Disclosure of the Invention
Radio frequency (RF) receivers which utilize quadrature demodulation techniques are known in the art. Some conventional digital quadrature receiver designs include a variable amplification stage followed by a downconversion stage. A received radio frequency (RF) signal is typically applied to a variable gain amplifier to selectively adjust the gain of the received signal depending upon the strength of the signal received at the antenna. An automatic gain control (AGC) component can be utilized to control the variable gain amplifier to account for varied signal strengths at the antenna of the receiver. The output of the variable gain amplifier is thereafter provided to a downconverter in such prior art designs. Downconversion includes analog processing, such as mixing, to downconvert the received radio frequency signal from an intermediate frequency (IF) to baseband. Following the downconversion operations, the received signal is low-pass filtered and conditioned for subsequent analog-to-digital conversion.
A common problem occurring in typical conventional digital quadrature receivers is the introduction of unwanted direct current (D.C.) offset (also known as direct current feedthrough). The direct current offset occurs on both in-phase (I) and quadrature (Q) channels as a consequence of the downconversion, low-pass filtering, and analog processing and conditioning steps. The direct current offset within the in-phase and quadrature channels can cause signal distortion in the demodulator of the receiver. Additionally, direct current offset often results in misoperation of the automatic gain control portion of the quadrature receiver. Direct current portions of the in-phase and quadrature channels or the complex direct current respectively, contain carrier information in some modulation schemes (e.g., constant envelope modulation schemes such as frequency modulation/frequency-shift keying (FM/FSK) in a dual-mode code division multiple access/advanced mobile phone system (CDMA/ AMPS) architecture). Averaging over the in-phase and quadrature channels does not reliably yield the direct current offset or feedthrough value in such modulation schemes, but rather provides the sum of the actual direct current of the complex envelope content and the unwanted direct current feedthrough yielding an ambiguous result. Exemplary prior art methods for minimizing effects of direct current feedthrough include offsetting or modulating the local oscillator of the downconverter. These conventional techniques are successful to some degree in minimizing the effects of direct current feedthrough. However, these techniques adversely affect the complex envelope spectrum which can limit the usefulness of such prior art methods in a number of applications.
Therefore, there exists a need to provide improved devices and methodologies for reducing direct current offset within quadrature receivers.
Brief Description of the Drawings Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
Fig. 1 is a functional block diagram of a communication system. Fig. 2 is a functional block diagram of an exemplary quadrature receiver according to the present invention. Fig. 3 is an illustrative representation of a complex envelope of a received wireless communication signal with constant envelope modulation.
Fig. 4 is a functional block diagram of a feedback structure for reducing direct current offset within in-phase and quadrature signals.
Fig. 5 is a functional block diagram of a feedforward structure for reducing direct current offset within in-phase and quadrature signals.
Fig. 6 is a flow chart illustrating an exemplary methodology for determining direct current offset. Best Modes for Carrying Out the Invention and Disclosure of Invention
According to one aspect, the present invention provides a quadrature receiver comprising: a downconverter configured to convert a wireless communication signal into a baseband signal; and an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
According to a second aspect, the present invention provides a quadrature receiver comprising: a downconverter configured to convert a wireless communication signal into a baseband signal; an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled values, and to provide a direct current offset signal from the plural sampled values; and a summer coupled with the downconverter and the I/Q offset processor and configured to combine the baseband signal and the direct current offset signal.
Another aspect of the present invention provides a signal processor of a quadrature receiver configured to calculate direct current offset, the signal processor comprising circuitry configured to sample a baseband signal to provide plural sampled vectors, to calculate a difference vector from the sampled vectors, to calculate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
Another aspect of the present invention provides a communication system comprising: a transmitter configured to output a wireless communication signal; and a quadrature receiver configured to receive the wireless communication signal and including: a downconverter configured to convert the wireless communication signal into a baseband signal; an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled values, and to provide a direct current offset signal from the plural sampled values; and a summer coupled with the downconverter and the I/Q offset processor and configured to combine the baseband signal and the direct current offset signal.
According to another aspect, the invention provides a quadrature receiver comprising: an antenna configured to receive a constant envelope modulated wireless communication signal; a variable gain amplifier coupled with the antenna and configured to adjust the gain of the wireless communication signal; a downconverter coupled with the variable gain amplifier and configured to convert the wireless communication signal into in-phase and quadrature analog baseband signals; plural low-pass filters coupled with the downconverter and configured to filter frequency components above a predetermined cut-off frequency from the in-phase and quadrature analog baseband signals; plural analog-to-digital converters coupled with the low-pass filters and configured to convert the in-phase and quadrature analog baseband signals to in-phase and quadrature digital baseband signals; an I/Q offset processor coupled with the analog-to-digital converters and configured to sample the in-phase and quadrature digital baseband signals to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate an orthogonal vector from the difference vector, to generate a scaled vector from the orthogonal vector, and to sum the difference vector, the scaled vector, and one of the sampled vectors to provide in-phase and quadrature digital direct current offset signals; plural digital-to-analog converters coupled with the I/Q offset processor and configured to convert the in-phase and quadrature digital direct current offset signals to in-phase and quadrature analog direct current offset signals; plural summers coupled with the downconverter and the digital-to-analog converters and configured to individually subtract one of the in-phase and quadrature analog direct current offset signals and one of the respective in-phase and quadrature analog baseband signals; and an automatic gain control circuit configured to control the variable gain amplifier responsive to the in-phase and quadrature digital baseband signals. Another aspect provides a method of calculating direct current offset comprising: receiving a wireless communication signal; downconverting the wireless communication signal following the receiving; sampling the wireless communication signal providing plural sampled vectors; calculating a difference vector from the sampled vectors; calculating a scaled vector from the difference vector; and summing the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
Another aspect of the present invention provides a method of operating a quadrature receiver comprising: receiving a wireless communication signal within a quadrature receiver; downconverting the wireless communication signal following the receiving providing in-phase and quadrature baseband signals; sampling the in-phase and quadrature baseband signals providing plural sampled values; calculating direct current offset signals from the plural sampled values; and subtracting the direct current offset signals from the in-phase and quadrature baseband signals.
Referring to Fig. 1, a communication system 1 including a transmitter 8 and a quadrature receiver 10 is depicted. Transmitter 8 and quadrature receiver 10 can be -3 configured for digital communications utilizing at least one wireless communication signal 1 1. In but one exemplary embodiment, communication system 1 utilizes a frequency modulation/frequency-shift keying (FM/FSK) modulation scheme in a dual- mode code division multiple access/advanced mobile phone system (CDMA/AMPS) architecture. Other configurations of communication system 1 are possible.
Referring to Fig. 2, the illustrated quadrature receiver 10 comprises a radio receive path 12 coupled with a baseband processor 14. Radio receive path 12 is additionally coupled with an antenna 16 configured to receive wireless communication signals. Exemplary wireless communication signals comprise frequency modulated (FM) radio frequency (RF) signals. Radio receive path 12 is also coupled with external circuitry 18 which can comprise processing circuitry, handset circuitry including a speaker, and/or any other desired circuitry.
Signals received by antenna 16 are applied to radio receive path 12. Initially, such received signals can be processed prior to application to receive path 12. For example, the received signals may be applied to a low noise amplifier (LNA), intermediate frequency (IF) converter, and band-pass filter prior to application to receive path 12.
Radio receive path 12 includes a variable gain amplifier 20, downconverter 22, local oscillator 24, low-pass filters 26, 27, analog-to-digital converters (ADCs) 28, 29, digital-to-analog converters (DACs) 30, 31 , and summers 32, 33. The illustrated downconverter 22 comprises plural mixers 34, 35 and a phase shifter 36.
The depicted baseband signal processor 14 includes an I/Q offset processor 40, automatic gain control (AGC) circuitry 42 and a downstream processor 44. Exemplary implementations of baseband processor 14 include digital signal processor (DSP) firmware or an application specific integrated circuit (ASIC). I/Q offset processor 40, automatic gain control circuitry 42 and downstream processor 44 are individually coupled with radio receive path 12.
Variable gain amplifier (VGA) 20 receives wireless communication signals from antenna 16 during normal operations of quadrature receiver 10. Variable gain amplifier 20 is configured to selectively adjust the gain of the wireless communication signals.
Variable gain amplifier 20 is operable to output intermediate frequency (IF) communication signals to downconverter 22.
Downconverter 22 provides downconversion operations which convert the wireless communication signals into in-phase (I) and quadrature (Q) analog baseband signals. In particular, local oscillator 24 outputs a periodic waveform to phase shifter 36 for application to respective mixers 34, 35. Received wireless communications signals are also applied to both mixers 34, 35. Mixers 34, 35 operate to utilize the received periodic waveform to downconvert the intermediate frequency wireless communication signal into respective in-phase and quadrature analog baseband signals. The in-phase and quadrature baseband signals are applied to respective low-pass filters 26, 27. Low-pass filters 26, 27 are individually configured to filter frequency components above a predetermined cut-off frequency from the in-phase and quadrature analog baseband signals. For example, in one embodiment, low pass filters 26, 27 are configured to filter frequencies above 15 kHz in AMPS mode. The filtered in-phase and quadrature baseband signals are applied to respective summers 32, 33. Following application to summers 32, 33, the in-phase and quadrature analog baseband signals are converted to digital signals within respective analog-to-digital converters 28, 29. The in-phase and quadrature digital baseband signals are outputted from radio receive path 12 to baseband processor 14. I/Q offset processor 40 is operable to calculate in-phase (Io fset) and quadrature
(Qoffset) digital direct current offset signals as described in detail below. The calculated in-phase and quadrature direct current offset signals can be utilized to minimize direct current offset or feedthrough resulting from the downconversion operations.
The calculated in-phase and quadrature direct current offset signals are outputted from I/Q offset processor 40 to radio receive path 12. More specifically, the in-phase and quadrature direct current offset signals are applied to respective digital-to-analog converters 30, 31 of radio receive path 12. Digital-to-analog converters 30, 31 individually operate to convert the in-phase and quadrature digital direct current offset signals into in-phase and quadrature analog direct current offset signals. Quadrature receiver 10 includes a feedback configuration for reducing the direct current offset within the in-phase and quadrature baseband signals. As illustrated, the in-phase and quadrature analog direct current offset signals are applied to respective summers 32, 33. Summers 32, 33 are configured to combine the in-phase and quadrature analog baseband signals and the respective in-phase and quadrature analog direct current offset signals. In particular, summers 32, 33 individually operate to subtract the in-phase and quadrature analog direct current offset signals from the respective in-phase and quadrature baseband analog signals outputted from low pass filters 26, 27.
The in-phase and quadrature analog signals outputted from summers 32, 33 are applied to respective analog and digital converters 28, 29 for application to I/Q offset 3 processor 40, automatic gain control circuitry 42 and downstream processor 44. The in- phase and quadrature signals outputted from summers 32, 33 preferably include minimal direct current offset.
Automatic gain control circuitry 42 receives the digital in-phase and quadrature signals outputted from respective summers 32, 33 and analog- to-digital converters 28, 29. Automatic gain control circuitry 42 is configured to control variable gain amplifier 20 responsive to the received digital in-phase and quadrature signals.
Downstream processor 44 receives the digital in-phase and quadrature signals from analog-to-digital converters 28, 29. Downstream processor 44 can be configured to provide further signal processing including I and Q combination operations, demodulation operations, decoding operations and/or detection operations in an exemplary embodiment. The output of downstream processor 44 is applied to external circuitry 18.
One methodology implemented by I/Q offset processor 40 for calculating direct current offset or feedthrough utilizes a-priori knowledge about the geometrical shape of the envelope as described below with reference to Fig. 3. Initially, I/Q offset processor 40 is configured to sample the in-phase and quadrature baseband signals to provide plural sample values. Exemplary sample values are vectors which individually include an in-phase value and a quadrature value. I/Q offset processor 40 is configured to calculate direct current offset or feedthrough from the sampled values utilizing a-priori knowledge.
In general, following sampling of the in-phase and quadrature baseband signals, I/Q offset processor 40 calculates a difference vector from the sampled values and an orthogonal vector from the difference vector. I/Q offset processor 40 scales the orthogonal vector providing a scaled vector utilizing a-priori knowledge. Thereafter, I/Q offset processor 40 sums at least one of the sampled values, the difference vector and the scaled vector to calculate the in-phase and quadrature direct current offset values or signals. The in-phase and quadrature direct current offset are subtracted from, or otherwise combined with, the in-phase and quadrature baseband signals to remove or minimize the direct current offset or feedthrough within the in- phase and quadrature baseband signals applied to baseband processor 14 and external circuitry 18.
Referring to Fig. 3, a complex envelope of the received wireless communication signal is a baseband signal represented by separate in-phase and quadrature channels. The in-phase channel comprises the real portion of the signal and the quadrature channel comprises the imaginary portion of the signal. The in-phase and quadrature signals are constant envelope modulated signals inasmuch as frequency modulation techniques only adjust the instantaneous frequency deviation of the communicated signal. Other modulation schemes which provide constant envelope modulated signals can be utilized. The complex envelope has a nominal gain R as a result of the constant envelope modulated signals (deviations from gain R may occur prior to setting of the automatic gain control circuitry). Utilizing this a-priori knowledge regarding the shape of the envelope with the gain R, it is possible to calculate the direct current offset or feedthrough resulting from downconversion of the received wireless communication signal in accordance with the present invention. The complex envelope of the baseband signals may be represented by a circle 50 with a radius R which corresponds to the gain. An unknown offset r0 of circle 50 corresponds to the direct current offset or feedthrough. Utilizing the a-priori knowledge, the center of circle 50 representing the direct current offset can be determined.
I/Q offset processor 40 is configured to sample the in-phase and quadrature baseband signals to provide I, Q sample pair values r„ r, which are represented as the following vectors in the described embodiment:
Figure imgf000010_0001
Utilizing the a-priori knowledge, it is determined that the two sample vector pairs r, , τ} are located upon circle 50. Using the two sample vector pairs r, , r an unknown offset vector
Figure imgf000010_0002
can be calculated. Initially, I/Q offset processor 40 is configured to generate a difference vector u from the sampled vectors r„ rr In particular, I/Q offset processor 40 calculates the difference vector u from the following formula → 1 → → → → u = — ( ij - ri ) where rj - r, ≠ 0
Thereafter, an orthogonal vector o having the magnitude of vector u can be computed by rotating vector u using a matrix M wherein
Figure imgf000011_0001
Thus, orthogonal vector o can be calculated by o = Mu
A scaled vector v is determined by scaling the orthogonal vector o by a factor K wherein
K = K(R, R2 = K2 u + u ;0< u <R2
Figure imgf000011_0002
Put another away, the scaled vector v is calculated by
KMu
The scaled vector v is perpendicular to the difference vector u.
Thereafter, the direct current offset r0 can be calculated by summing the difference vector u, the scaled vector v and one of the sampled values to provide the direct current offset. Such may be represented by
τ n = r ; + u + v I/Q offset processor 40 is configured in one embodiment to integrate the determined direct current offset. Thereafter, the integrated direct current offset is outputted to radio receive path 12 and summers 32, 33. A feedback control loop typically utilizes one pole which is realized by an integrator with the transfer function (az/z-1) whereby a is the loop gain.
Referring to Fig. 4 and Fig. 5, exemplary feedback and feedforward structures 58, 70 for reducing direct current offset within in-phase and quadrature baseband signals are illustrated. The depicted structures 58, 70 are individually utilized in the in-phase signal path and the quadrature signal path in the described embodiment.
Referring specifically to Fig. 4, the input baseband signal includes desired information rk plus direct current offset r0. The baseband signal is initially applied to a summer 60 (summer 60 can comprise one of summers 32, 33 depicted in Fig. 2) of feedback structure 50. I/Q offset processor 40 is utilized to estimate the direct current offset
(represented as error value ε) in function block 62 using the previously described process. I/Q offset processor 40 calculates the direct current offset as a function of r„ rf and R. Thereafter, the determined direct current offset is integrated within an integration function block 64. I/Q offset processor 40 can also be configured to perform the integration functions of block 64.
The output of integrator 64 comprises direct current offset r0 which is applied to summer 60 and subtracted from the incoming baseband signal comprising desired information rk plus the direct current offset r0. The depicted feedback structure 58 effectively cancels the direct current offset or feedthrough by driving error signal ε to 0.
Referring specifically to Fig. 5, the alternative feedforward structure 70 for reducing direct current offset within the baseband in-phase and quadrature signals is illustrated. In the depicted feedforward structure 70, the baseband signal including the desired information rk and the direct current offset r0 is applied to a summer 72 and function block 74. I/Q offset processor 40 is utilized to estimate the direct current offset in function block 74 using the previously described process. I/Q offset processor 40 calculates the direct current offset as a function of η, and R. The estimated direct current offset is applied to low-pass filter 76 and a time-average value r0 of the direct current offset is outputted from low-pass filter 76. The calculated direct current offset r0 is subtracted from the baseband signal within summer 72.
Although the quadrature receiver 10 depicted in Fig. 2 is configured as a feedback structure, in an alternative embodiment it is configured as a feedforward structure to implement direct current offset reduction operations. Both the feedback and feedforward methods of reducing direct current offset from the baseband signal are numerically robust over a reasonable range of input values and is preferably utilized with fixed-point digital signal processing (DSP) inasmuch as the involved operations may be implemented within I/Q offset processor 40. Referring to Fig. 6, a flow chart illustrating an exemplary method for determining direct current offset following downconversion operations is illustrated. I/Q offset processor 40 can be configured to execute operational code to provide the illustrated steps.
Initially, I/Q offset processor 40 performs step S10 wherein the downconverted baseband signal is sampled to provide I, Q sample pair vectors as previously described. Thereafter, I/Q offset processor 40 calculates a difference vector from the sampled values or vectors at step S12. At step S14, I/Q offset processor 40 calculates an orthogonal vector by rotating the difference vector and calculates a scaled vector from the orthogonal vector. At step SI 6, I/Q offset processor 40 determines the direct current offset using the difference vector, the scaled vector and one of the sampled vectors. I/Q offset processor 40 can thereafter perform additional signal processing such as integration operations or low-pass filtering operations if desired.

Claims

1. A quadrature receiver comprising: a downconverter configured to convert a wireless communication signal into a baseband signal; and 5 an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal. w
2. The quadrature receiver according to claim 1 further comprising a summer coupled with the downconverter and the I/Q offset processor and configured to combine the baseband signal and the direct current offset signal.
15 3. The quadrature receiver according to claim 2 further comprising: a variable gain amplifier configured to selectively adjust the gain of the wireless communication signal; and automatic gain control circuitry coupled with the summer and configured to control the variable gain amplifier responsive to the output of the summer. 0
4. The quadrature receiver according to claim 2 further comprising: an analog-to-digital converter coupled intermediate the downconverter and the I/Q offset processor and configured to convert the baseband signal into a digital signal; and 5 a digital-to-analog converter coupled intermediate the I/Q offset processor and the summer and configured to convert the direct current offset signal into an analog signal.
5. The quadrature receiver according to claim 1 wherein the 0 downconverter is configured to convert the wireless communication signal into in- phase and quadrature baseband signals.
6. The quadrature receiver according to claim 1 wherein the I/Q offset processor is configured to calculate an orthogonal vector from the difference vector.
7. The quadrature receiver according to claim 6 wherein the I/Q offset processor is configured to scale the orthogonal vector to calculate the scaled vector.
8. The quadrature receiver according to claim 1 wherein the I/Q offset processor is configured to integrate the direct current offset signal.
9. The quadrature receiver according to claim 1 wherein the wireless communication signal comprises a constant envelope modulated wireless communication signal.
10. A quadrature receiver comprising: a downconverter configured to convert a wireless communication signal into a baseband signal; an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled values, and to provide a direct current offset signal from the plural sampled values; and a summer coupled with the downconverter and the I/Q offset processor and configured to combine the baseband signal and the direct current offset signal.
11. The quadrature receiver according to claim 10 further comprising: a variable gain amplifier configured to selectively adjust the gain of the wireless communication signal; and automatic gain control circuitry coupled with the summer and configured to control the variable gain amplifier responsive to the output of the summer.
12. The quadrature receiver according to claim 10 further comprising: an analog-to-digital converter coupled intermediate the downconverter and the I/Q offset processor and configured to convert the baseband signal into a digital signal; and a digital-to-analog converter coupled intermediate the I/Q offset processor and the summer and configured to convert the direct current offset signal into an analog signal.
3 13. The quadrature receiver according to claim 10 wherein the downconverter is configured to convert the wireless communication signal into in- phase and quadrature baseband signals.
14. The quadrature receiver according to claim 10 wherein the I/Q offset processor is configured to sample the baseband signal to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide the direct current offset signal.
15. The quadrature receiver according to claim 14 wherein the I/Q offset processor is configured to calculate an orthogonal vector from the difference vector.
16. The quadrature receiver according to claim 15 wherein the I/Q offset processor is configured to scale the orthogonal vector to calculate the scaled vector.
17. The quadrature receiver according to claim 10 wherein the I/Q offset processor is configured to integrate the direct current offset signal.
18. The quadrature receiver according to claim 10 wherein the wireless communication signal comprises a constant envelope modulated wireless communications signal.
19. A signal processor of a quadrature receiver configured to calculate direct current offset, the signal processor comprising circuitry configured to sample a baseband signal to provide plural sampled vectors, to calculate a difference vector from the sampled vectors, to calculate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
20. The signal processor according to claim 19 wherein the signal processor is configured to calculate an orthogonal vector from the difference vector.
21. The signal processor according to claim 20 wherein the signal processor is configured to scale the orthogonal vector to calculate the scaled vector.
22. The signal processor according to claim 19 wherein the signal processor is configured to sample the baseband signal to provide plural sample vectors individually comprising an in-phase value and a quadrature value.
23. The signal processor according to claim 19 wherein the signal processor is configured to integrate the direct current offset signal.
24. The signal processor according to claim 19 wherein the baseband signal comprises a constant envelope modulated wireless communication signal.
25. A communication system comprising: a transmitter configured to output a wireless communication signal; and a quadrature receiver configured to receive the wireless communication signal and the quadrature receiver including: a downconverter configured to convert the wireless communication signal into a baseband signal; an I/Q offset processor coupled with the downconverter and configured to sample the baseband signal to provide plural sampled values, and to provide a direct current offset signal from the plural sampled values; and a summer coupled with the downconverter and the I/Q offset processor and configured to combine the baseband signal and the direct current offset signal.
26. The communication system according to claim 25 further comprising: a variable gain amplifier configured to selectively adjust the gain of the wireless communication signal; and automatic gain control circuitry coupled with the summer and configured to control the variable gain amplifier responsive to the output of the summer.
27. The communication system according to claim 25 wherein the downconverter is configured to convert the wireless communication signal into in- phase and quadrature baseband signals.
28. The communication system according to claim 25 wherein the I/Q offset processor is configured to sample the baseband signal to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate a scaled vector from the difference vector, and to sum the difference vector, the scaled vector and one of the sampled vectors to provide the direct current offset signal.
29. The communication system according to claim 28 wherein the I/Q offset processor is configured to calculate an orthogonal vector from the difference vector.
30. The communication system according to claim 29 wherein the I/Q offset processor is configured to scale the orthogonal vector to calculate the scaled vector.
31. The communication system according to claim 25 wherein the I/Q offset processor is configured to integrate the direct current offset signal.
32. The communication system according to claim 25 wherein the wireless communication signal comprises a constant envelope modulated wireless communications signal.
3
33. A quadrature receiver comprising: an antenna configured to receive a constant envelope modulated wireless communication signal; a variable gain amplifier coupled with the antenna and configured to adjust the gain of the wireless communication signal; a downconverter coupled with the variable gain amplifier and configured to convert the wireless communication signal into in-phase and quadrature analog baseband signals; plural low-pass filters coupled with the downconverter and configured to filter frequency components above a predetermined cut-off frequency from the in-phase and quadrature analog baseband signals; plural analog-to-digital converters coupled with the low-pass filters and configured to convert the in-phase and quadrature analog baseband signals to in- phase and quadrature digital baseband signals; an I/Q offset processor coupled with the analog-to-digital converters and configured to sample the in-phase and quadrature digital baseband signals to provide plural sampled vectors, to generate a difference vector from the sampled vectors, to generate an orthogonal vector from the difference vector, to generate a scaled vector from the orthogonal vector, and to sum the difference vector, the scaled vector, and one of the sampled vectors to provide in-phase and quadrature digital direct current offset signals; plural digital-to-analog converters coupled with the I/Q offset processor and configured to convert the in-phase and quadrature digital direct current offset signals to in-phase and quadrature analog direct current offset signals; plural summers coupled with the downconverter and the digital-to-analog converters and configured to individually subtract one of the in-phase and quadrature analog direct current offset signals and one of the respective in-phase and quadrature analog baseband signals; and an automatic gain control circuit configured to control the variable gain amplifier responsive to the in-phase and quadrature digital baseband signals.
34. A method of calculating direct current offset comprising: receiving a wireless communication signal; downconverting the wireless communication signal following the receiving; sampling the wireless communication signal providing plural sampled vectors; calculating a difference vector from the sampled vectors; calculating a scaled vector from the difference vector; and summing the difference vector, the scaled vector and one of the sampled vectors to provide a direct current offset signal.
35. The method according to claim 34 further comprising calculating an orthogonal vector from the difference vector.
36. The method according to claim 35 wherein calculating the orthogonal vector comprises rotating the difference vector.
37. The method according to claim 35 wherein calculating the scaled vector comprises scaling the orthogonal vector.
38. The method according to claim 34 wherein the sampling follows the downconverting.
39. The method according to claim 34 wherein the downconverting generates an in-phase signal and a quadrature signal.
40. The method according to claim 34 further comprising integrating the direct current offset signal.
41. The method according to claim 34 further comprising subtracting the direct current offset signal from the wireless communication signal.
42. The method according to claim 34 wherein the receiving comprises receiving a constant envelope modulated wireless communication signal. 3
43. A method of operating a quadrature receiver comprising: receiving a wireless communication signal within a quadrature receiver; downconverting the wireless communication signal following the receiving providing in-phase and quadrature baseband signals; J sampling the in-phase and quadrature baseband signals providing plural sampled values; calculating direct current offset signals from the plural sampled values; and subtracting the direct current offset signals from the in-phase and quadrature baseband signals. 0
44. The method according to claim 43 wherein calculating comprises: determining a difference vector from the sampled values; determining a scaled vector from the difference vector; and summing the difference vector, the scaled vector and one of the sampled 5 values.
45. The method according to claim 44 further comprising calculating an orthogonal vector from the difference vector.
0 46. The method according to claim 45 wherein calculating the orthogonal vector comprises rotating the difference vector.
47. The method according to claim 45 wherein calculating the scaled vector comprises scaling the orthogonal vector. 5
48. The method according to claim 43 further comprising integrating the direct current offset signals.
49. The method according to claim 43 further comprising adjusting the 0 gain of the wireless communication signal following the subtracting and responsive to the in-phase and quadrature signals.
50. The method according to claim 43 wherein the receiving comprises receiving a constant envelope modulated wireless communication signal.
PCT/US1999/030803 1998-12-22 1999-12-22 Quadrature receiver, communication system, signal processor, method of calculating direct current offset, and method of operating a quadrature receiver WO2000038385A1 (en)

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