WO2000028666A1

WO2000028666A1 - Frequency synthesizer, method for operating a frequency synthesizer and integrated circuit comprising a frequency synthesizer

Info

Publication number: WO2000028666A1
Application number: PCT/DE1999/003580
Authority: WO
Inventors: Torsten Hinz; Armin Pitzer
Original assignee: Infineon Technologies Ag
Priority date: 1998-11-10
Filing date: 1999-11-10
Publication date: 2000-05-18

Abstract

The invention relates to a frequency synthesizer circuit (1) comprising a phase-locking loop (2) which provides for a higher-frequency pulse at its output, whereby said higher-frequency pulse has one or more phases. To this end, a reference pulse of any frequency which is coupled in the input end is used. Said frequency synthesizer circuit also comprises a frequency divider (3, 4) which is provided downstream in relation to the phase-locking loop and which by means of said higher-frequency pulse having one or more phases and by means of division provides for an output pulse which can be any output pulse with regard to its frequency. The invention also relates to a sigma-delta-modulator (9) which controls the frequency divider. The frequency of the reference pulse and of the output pulse become arbitrary in a certain range when the configuration of the divider factors (m, n) in the phase-locking loop, of the divider factor of the frequency divider (q, p) and of the input signal of the sigma-delta-modulator are chosen freely. A second control input at the sigma-delta-modulator enables the utilisation of the frequency synthesizer as an oscillator in a purely digital PLL.

Description

description

Frequency synthesizer, method for operating a frequency synthesizer and integrated circuit with a frequency synthesizer

The invention relates to a frequency synthesizer circuit, in particular a frequency synthesizer with an interconnection of a phase-locked loop, a frequency divider and a sigma-delta modulator which drives this. Furthermore, the invention relates to a method for operating a frequency synthesizer and an integrated circuit with such a frequency synthesizer.

In modern transmitter and receiver arrangements in mobile radio technology, frequency synthesizers are predominantly used to generate the mixed signals necessary for the respective frequency conversions. In particular, frequency synthesizers are also used in microcontrollers to generate the various clocks.

A generic phase locked loop (PLL) for frequency synthesizers is described in US 4,965,531. There, a phase locked loop with a digitally implemented phase detector, an analog loop filter, an analog oscillator and a digital divider is specified in the feedback path. The divider in the feedback path is designed as a fractional divider. This fractional divider is controlled by a sigma-delta modulator in such a way that non-integer ratios of input and synthesized output frequency are achieved. The arrangement of the sigma-delta modulator together with the fractional dividers in the feedback path of the phase-locked loop reduces the quantization noise caused by the fractional divider. However, when using the phase-locked loops mentioned, a problem arises in particular when a large number of such phase-locked loops are required on a single chip. The loop filter often requires external circuit components. In addition, the analog circuit parts, the loop filter and the oscillator require a lot of chip area and therefore have a comparatively high power consumption. Finally, a purely analog phase locked loop is rigid with regard to its input and output frequency and is therefore inflexible for changing requirements.

In purely digital phase locked loops, a digital divider is used instead of the analog oscillator. This divider, which is designed as a fractional divider, forms the output clock of the phase locked loop from a high-frequency basic clock, which is then fed back into the phase comparator. The choice of the divider factor is suitably set by the digital loop filter, so that the output clock can be varied compared to the basic oscillator clock.

The disadvantage of such a digital PLL oscillator is its high intrinsic jitter, which is identical to the period of the high-frequency basic clock. However, increasing this basic clock to improve the self-jitter is only possible to a limited extent, since the technology used limits the increase in the basic clock frequency. However, this digital phase locked loop is still rigid and therefore inflexible.

One possibility of reducing the self-jitter in a phase locked loop is described in US Pat. No. 5,493,243. In the purely digital phase-locked loop specified there, the divider used as the oscillator is not supplied with a high-frequency basic clock, but with six phases of the basic clock. Instead of changing the divider factor, the clock source of the divider is switched between these six phases in a commutator for frequency synthesis. As a result, the self-jitter is only 1/6 of the period of the basic oscillator clock. The commutator is controlled by a 7 bit

Counter; the six basic clock phases are generated from a master reference clock using a classic analog phase locked loop. However, this improved digital phase locked loop, in which the self-jitter is reduced, is rigid and inflexible with respect to different master reference clock frequencies and output clock frequencies.

The required frequency synthesizer as an oscillator in a purely digital phase-locked loop should be versatile and should have as little redundancy as possible in order to achieve a high level of economy. Space and power requirements should be reduced to a minimum. A high degree of flexibility is required with regard to the master reference frequency and output frequency. The intrinsic jitter and the frequency accuracy should be able to be reduced to the required level regardless of the technology.

Starting from the prior art mentioned at the outset, the present invention is therefore based on the object of specifying a frequency synthesizer which fulfills the requirements mentioned above.

According to the invention this object is achieved by a frequency synthesizer with the features of claim 1, i. H. a frequency synthesizer with the following features:

a phase-locked loop that provides a high-frequency, single-phase or multi-phase clock at its output from a reference clock coupled in on the input side with any frequency, a frequency divider connected downstream of the phase-locked loop, which provides an output clock of any frequency with respect to its output from the high-frequency, single-phase or multi-phase clock by division, a sigma-delta modulator which drives the frequency divider.

Furthermore, the object is achieved by a method for operating a frequency synthesizer with the features of patent claim 11 and by an integrated circuit with at least one frequency synthesizer monolithically integrated in a semiconductor chip according to patent claim 12.

The multi-phase basic clock is generated in a classic analog phase locked loop from a "clean" master reference clock. The flexible configuration of the feedback divider and the prescaler of the analog phase locked loop results in a very large permissible range for the frequency of the "clean" master reference clock. The frequency of the multi-phase basic clock, which is generated in the analog phase-locked loop for the frequency dividers, only has to be in a range to be configured beforehand. The basic multi-phase clock can thus be generated from almost any master reference frequency.

Any desired output frequency can be generated by means of completely flexibly configurable rational division factors of the frequency divider used as the clock generator. The frequency error resulting from the rational division factor and the permissible range of the multi-phase basic clock frequency is reduced as desired by the choice of the accumulator word width of the sigma delta modulator. The frequency error is compensated for by applying a constant to the accumulator. A second input on the accumulator represents the position input of the oscillator, which is connected to the output of a digital tal loop filter can be connected to a purely digital phase locked loop. If the frequency synthesizer is not used as an oscillator in a purely digital PLL, this input is permanently set to 0.

The maximum self-jitter of the frequency synthesizer is determined by the number of phases and the smallest permissible frequency of the multi-phase basic clock and is therefore a design parameter. The accuracy of the output frequency is given by the word width of the accumulator and thus also a design parameter. If the divider factors of the upstream analog phase-locked loop for generating the multi-phase basic clock, the divider factor of the frequency divider used as the clock generator and the constant applied to the Sigmadelta modulator can be set, for example, by software, the result is a wide frequency spectrum for the master reference frequency and the output frequency.

In an application in which only one phase-locked loop or only one frequency synthesizer is required, the use of the frequency synthesizer according to the invention is not absolutely sensible. The modular circuit concept offers advantages in the application in which many frequency synthesizers and / or purely digital PLLs are required with a flexible master reference frequency. It enables frequency synthesis with regard to frequency and phase of independent clocks with only one analog phase locked loop. This multiple use of a single analog phase-locked loop to generate multiple output clocks with free configuration of the master reference clock frequency also enables area optimization in the design of the frequency synthesizers. This advantageously also significantly reduces the power consumption of the entire circuit. Advantageous refinements and developments of the invention can be found in the following description, the figures in the drawing and the respective subclaims.

The invention is explained in more detail below on the basis of the exemplary embodiments indicated in the figures of the drawing. It shows:

1 shows the block diagram of the frequency synthesizer according to the invention;

FIG. 2 shows an advantageous embodiment for the analog phase locked loop for generating the multi-phase basic clock of the frequency synthesizer according to the invention;

FIG. 3 shows the block diagram of the frequency divider, embodied as a clock generator, of the frequency synthesizer according to the invention;

Figure 4 shows the block diagram of the sigma-delta modulator of the frequency synthesizer according to the invention.

In all figures of the drawing, the same or functionally identical elements are provided with the same reference numerals, unless stated otherwise.

FIG. 1 shows the block diagram of the frequency synthesizer according to the invention. In Figure 1, 1 denotes the frequency synthesizer according to the invention. The frequency synthesizer consists of a series-connected analog phase locked loop (PLL) 2, which in the present exemplary embodiment is designed as a multiphase clock generator, multiplexer 3 and frequency divider 4. Furthermore, a control path is provided in which a sigma-delta modulator 5, which drives the frequency divider 4, is connected.

First, the general mode of operation of a frequency synthesizer according to the invention is described with reference to FIG. 1. A detailed description of the structure and the mode of operation of the individual components of the frequency synthesizer 1 according to the invention is then given with reference to FIGS. 2 to 4.

The external master reference clock with the frequency fIN is applied to an analog PLL via a prescaler with the divider factor 1 / m. The PLL uses this to generate a multiphase clock signal of n times the frequency with p phases. The PLL output clock thus has the frequency fl = fIN * n / m. That

"Clock bundle" is given to any number of dividers, one divider being provided for each output frequency required. The division factors of these dividers can be freely programmed; discrete division factors q / p are possible. Because of the discrete values, the output frequency typically does not match the desired frequency. A constant phase error results with each cycle. This phase error is accumulated in a sigma delta modulator.

If this accumulator overflows or underflows, the divider factor is modified by + l / p or by -1 / p for the next cycle, so that the division is not made with the factor q / p, but with the factor (q + l) / p or (ql) / p. Due to the overflow of the sigma delta modulator, the phase correction in the phase error memory is automatically taken into account. With the freely programmable value, which is applied to the Sigma Delta modulator as a phase error, any output frequency can be formed. The accuracy of this frequency only depends on the battery word width. The Eigenjitter this The clock rate is nominally 1 / (fIN * n / m * p), the resolution steps are 1 / (fIN * n / m * p * 2 ^Λ Akuu word width). Both are only limited by the maximum possible frequency of the semiconductor technology used. A precondition for using this circuit is, however, that the frequency fl must be designed to be correspondingly higher in frequency than the desired output clock fout.

FIG. 2 shows the block diagram of an advantageous exemplary embodiment for the analog phase-locked loop for generating the multi-phase basic clock.

The analog PLL 2 in FIG. 2 has a phase detector 21, a loop filter 22 and an oscillator 23, which are connected in series. In addition, a feedback path 24 is provided, which feeds back the output signal fl of the oscillator 23 into the phase detector 21. A first divider 25 with a first divider ratio 1 / n is connected in the feedback path 24. In addition, a second divider 26 is provided, which is connected upstream of the phase detector 21 of the analog PLL 2 as a prescaler. The second divider 26 has a second divider ratio 1 / m. A control device 27 is also provided. The control device 27 controls the dividers 25, 26 and the loop filter 22. The control device 27 can in particular be used as a microprocessor or

Microcomputer be trained. The various divider ratios 1 / m, 1 / n and the various parameters of the analog PLL 2, such as the filter constant and the amplification factor of the oscillator 23, can be suitably set. A software-controlled setting of these factors by the program of the control device 27 is thus possible, which alone guarantees a very high flexibility of the analog PLL 2 at this point. The loop filter 22 is typically designed as a low-pass filter. It is also particularly advantageous if the oscillator is designed as a voltage-controlled oscillator. It is also particularly advantageous if the oscillator 23 is implemented as a ring oscillator with several clock taps. An analog PLL 2 designed as a so-called multi-phase clock generator can thus be implemented.

A further, very advantageous embodiment of the analog PLL 2 is described in EP 0 821 487 AI. The analog PLL described there has a coarse control device in addition to the phase / frequency control. This coarse control device is activated, in particular, in the immediate starting phase of the analog PLL, in which the latter has not yet settled in and the frequency differences or the phase position of the input signal and output signal of the analog PLL have not yet stabilized to a constant value.

With regard to further details, features, their advantages and mode of operation of phase-locked loops, reference is expressly made to EP 0 821 487 AI and full reference ("Incorporated by Reference").

FIG. 3 shows the block diagram of the divider of the frequency synthesizer according to the invention. As already mentioned, the divider consists of two sub-blocks: a multiplexer 3 and a frequency divider 4. The multiplexer 3 selects one from the p phases of the output signal fl provided on the output side by the analog PLL 2 and supplies the downstream frequency divider 4 with it this phase of the multi-phase clock. This clock represents the working clock. The frequency divider 4 in turn determines which phase the multiplexer 3 selects. The frequency divider 4 can also change the selected phase during the division process. his. Not only are integer divisors possible, but also rational divisors with a third divider ratio q / p. The third divider ratio q / p can be set in a software-controlled manner by the control device 27, like the first two divider ratios 1 / m, 1 / n.

In addition to the p phases, p selection lines go to the multiplexer 3, only one of the selection lines being activated in each case. If the selection line changes now, the multiplexer 3 is constructed in such a way that it is ensured that the output clock cannot "spike". Rather, the working cycle decoupled from the multiplexer 3 will be shortened or lengthened by the distance between two phases. It is only ever switched between two neighboring phases within one work cycle.

The frequency divider 4 consists of a plurality of shift registers 41 ... 44 of the width k which can be loaded in parallel, a counter 45 and a decoder unit 46. The first shift register 41 is the cycle generator, with a logic "1" at the input. The output of this shift register is a load signal with which this shift register 41 and all other shift registers 42 ... 44 are loaded. The load value of the shift register 41 can now be used to determine the number of work cycles after which the cycle generator 41 generates the load signal again and thus starts a new cycle. This loading value corresponds to the basic division factor. The fact that a logic "1" is present at the data input of the cycle generator 41 ensures that the shift registers 41 ... 44 are also loaded. This means that the circuit starts up stably from any state.

The second shift register 42 is the output signal generator. In it the course of the output clock during a Cycle filed. In the third and fourth shift register 43,

44 is stored at which time and in which direction (up or down) of the cycle the multiplexer 3 is to switch the input clock fl.

The signals "command" and "direction" of the sigma delta modulator 5 indicate whether the divider factor should be varied by 1 / p in the next cycle or not. They are recoded and accepted together with the programmed values in the third and fourth shift registers 43, 44. The outputs of these two shift registers 43, 44 control a counter 45 which manages the selected phase. The counter output is decoded with decoder 46 and indicates the selection lines for multiplexer 3. All counter states that are not used must also be decoded in a sensible manner to ensure that the circuit starts up from every state.

The greatest possible flexibility of the divider 3, 4 can be achieved by completely freely programmable load values for the shift registers 41 ... 44. This means that almost any division factor and output clock pattern can be set. Only one switch between two phases is possible per work cycle fl of the frequency divider 4. At one point in the cycle, the possibility of phase switching is reserved for the variable change of the division factor by 1 / p.

FIG. 4 describes the block diagram of the sigma delta modulator of the frequency synthesizer according to the invention.

In principle, the sigma delta modulator 5 is a simple adder 53 of the word width r with two input words ph_const and ph_var, which also have the word width r, plus a register device 52 and an overflow / underflow detection 51 for the signals "command" and "direction". The input word Wide ones are 2's complement numbers and are added to the always positive accumulator content with each cycle. It is detected whether the accumulator overflows or underflows due to the addition or the subtraction if both input words are negative overall. In this case there will be a signal

"command" generated. A second signal "direction" indicates whether an underflow or overflow has occurred. These two signals control the modification of the divider factor in frequency divider 4. If the accumulator overflows, the next output cycle is shortened, and if there is an underflow, it is extended. The accumulator reacts to an overflow or underflow with a module operation, which means that it automatically jumps from its highest value to "0" and vice versa.

In principle, the accumulator manages the phase error between the desired and the real output clock. For further clarification, an example is shown: 16.384MHz output frequency is to be generated from the 13MHz master reference clock frequency. The analog PLL generates a 6 phase clock (p = 6), this clock having a maximum frequency of 70MHz. In the analog PLL, the factors m and n are set to 8 and 42. The output frequency of the analog PLL is therefore fl = 13MHz * 42/8 = 68.25MHz. The intrinsic jitter is 1 / (6 * 68.25MHz) = 2.44ns. In order to generate fout = 16.384MHz from fl = 68.25MHz, the divider block should actually have a divider factor of 4.1656494. However, only divisors of q / p with p = 6 are possible. The closest divisor factor to 4.1656494 is therefore 25/6 = 4.16666. This results in an output frequency of fout = 16.38MHz, which means that it is too small by 4KHz.

In order to get to fout = 16.384MHz, the divider block has to shorten the output clock for individual clocks. This is also possible because the divider block can dynamically modify its division factor for one cycle by 1 / p. That means that in one output cycle the work cycle fl is not divided by 25/6, but by 24/6 or 26/6. The consequence of this is that the clock period of this one output clock is shortened or extended by the value of the Mtrinsian jitter. The shortening of the one output clock is generated by an overflow of the accumulator in the sigam delta modulator 5. With a battery word width of 12 bits, the battery takes on the values between 0 and 4095. If the accumulator overflows, this corresponds to a subtraction of 4096 from the accumulated content.

As long as the divider block divides by a factor of 25/6, 16.38MHz is generated instead of a frequency of 16.384MHz. The desired period is 1 / 16.384MHz = 61.035ns, the actual resulting period is 1 / 16.38MHz = 61.050ns. That means that with each output clock the phase of the actual output clock moves away from the phase of the desired clock by l / 16.38MHz-l / 16.384MHz = 14.90ps. A correction step by modifying the divider factor in the divider block corresponds to a phase shift of 2.44ns. As a result, everyone had to

2.44ns / 14.90ps = 163.84 cycles the plate factor on the divider block for an output cycle 24/6 instead of 25/6.

The accumulator in the sigma delta modulator 5 manages the phase error between the desired and the real output clock. The phase deviation of 14.90ps is mapped in a binary number and added to the accumulator content with each cycle. If the accumulator overflows, this corresponds to a subtraction of 4096 from the accumulator content with simultaneous correction of the output clock by 2.44ns. That means that the 4096 correspond to a phase deviation of 2.44ns. Accordingly, a bit in the accumulator indicates a phase deviation of 2.44ns / 4096 = 0.596ps. A phase deviation of 14.90ps then gives the number 1.90ps / 0.596ps = 25. Accordingly, the number 25 is added to each output clock in the accumulator. In As a result, the accumulator overflows every 4096/25 = 163.84 cycles and then triggers a change in the divider factor on the divider block from 25/6 to 24/6 for one cycle, exactly what was required.

The +25 is constantly applied in 2's complement format to the first input (ph_const) of the Sigma delta modulator 5. The second input (ph_var) of the sigma delta modulator is the control input for a purely digital PLL if the frequency synthesizer is used as an oscillator in a purely digital PLL. The output clock can be changed dynamically at this input. The number 1 at this input therefore means a frequency change in the example above by 61.035ns / 0.596ps = 9.768ppm. By processing 2's complement numbers at both inputs, frequency correction in the other direction is also possible.

Reference symbol list:

1 frequency synthesizer

2 phase locked loop 3 multiplexers

4 frequency dividers

5 sigma delta modulator

21 phase detector 22 loop filter, low pass filter

23 (voltage controlled) oscillator, ring oscillator

24 feedback path

25 first divisor

26 second divider, prescaler 27 control device

41 shift registers, cycle generator

42 shift registers, output signal generator

43 up shift register 44 down shift register

45 counter device, up / down counter

46 decoder device

51 Over / underflow detection 52 Register device

53 adding unit

Claims

claims

1. frequency synthesizer circuit (1)

- providing a phase-locked loop (2), of any frequency it a hoherfrequenten, -on- from an input side, the coupled reference clock (j_ _N) ^m or multiphase clock (fι_) at its output,

- With a phase-locked loop (2) downstream frequency divider (3, 4), from the high-frequency, single or multi-phase clock (fι_) by division any frequency with respect to its output clock (fouτ) ^at its output, and

- With a sigma-delta modulator (5) which drives the frequency divider (3, 4).

2. Circuit according to claim 1, characterized in that the phase-locked loop (2) has a series-connected phase detector (21), a loop filter (22) and an oscillator device (23) and one arranged between the input and output of the phase-locked loop (2) Has feedback path (24) into which a first divider device (25) with a first divider ratio (1 / n) is connected.

3. Circuit according to claim 1 or 2, so that a second divider device (27) upstream of the phase-locked loop (2) with a second divider ratio (1 / m) is provided.

4. Circuit according to one of claims 2 or 3, characterized in that the oscillator device (23) is designed as a voltage-controlled oscillator and / or as a ring oscillator with a plurality of clock taps.

5. Circuit according to one of the preceding claims, characterized in that the phase locked loop (2) is designed as a multi-phase clock generator for generating a multi-phase output clock signal (f] _) derived from the input clock signal (fj _.N ).

6. Circuit according to one of the preceding claims, characterized in that the frequency divider (3, 4) has a multiplexer (3) and a downstream divider (4) with a third division ratio (q / p), the divider (4) each Provides phase of the multi-phase output signal (fι_) of the phase locked loop (2) at its output.

7. Circuit according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the frequency divider (3, 4) has a cycle generator (41) and an output signal generator (42).

8. Circuit according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the frequency divider (3, 4) has at least one shift register (41 ... 44) whose load values are freely programmable.

9. Circuit according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the sigma-delta modulator (5) is designed as an adder with a first word width (r) and at least two

Control inputs and at least two control outputs, wherein a control signal (ph__const, ph_var) with the first word width (r) can be coupled into the control inputs and the two control outputs a directional control provide signal (DIRECTION) and / or a command control signal (COMMAND).

10. Circuit according to one of the preceding claims, characterized in that at least one divider ratio (1 / m, 1 / n, q / p) of the divider devices (25; 27; 3, 4) are freely adjustable by means of the control device (26) and / or are programmable.

11. A method of operating the frequency synthesizer circuit according to one of the preceding claims, characterized in that an output clock (ouτ) of a high-frequency, single-phase or multi-phase clock (f) _) is formed by division in the frequency divider (3, 4) , The higher-frequency single- or multi-phase clock is generated with a phase-locked loop (2) from a reference clock (fIN), the frequency of which is arbitrary in a certain range.

12. Integrated circuit with at least one monolithically integrated frequency synthesizer circuit (1) in a semiconductor chip according to one of claims 1 to 10.