WO2000026741A3 - A method for delivering data to an instruction processing unit - Google Patents

A method for delivering data to an instruction processing unit Download PDF

Info

Publication number
WO2000026741A3
WO2000026741A3 PCT/SE1999/001962 SE9901962W WO0026741A3 WO 2000026741 A3 WO2000026741 A3 WO 2000026741A3 SE 9901962 W SE9901962 W SE 9901962W WO 0026741 A3 WO0026741 A3 WO 0026741A3
Authority
WO
WIPO (PCT)
Prior art keywords
read request
processing unit
instruction processing
requested data
delivering data
Prior art date
Application number
PCT/SE1999/001962
Other languages
French (fr)
Other versions
WO2000026741A2 (en
Inventor
Matiss Jonas Zervens
Orvar Per Dahl
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to AU14326/00A priority Critical patent/AU1432600A/en
Priority to EP99971528A priority patent/EP1145094A3/en
Publication of WO2000026741A2 publication Critical patent/WO2000026741A2/en
Publication of WO2000026741A3 publication Critical patent/WO2000026741A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing

Abstract

A computer system temporarily stores a read request that results in a cache hit based on a previous read request that has not cached a requested data in a cache memory. While temporarily stored, a subsequent read request may be executed, without being stalled due to the pendency of an on going memory cycle. After the requested data from the previous read request is cached, the stored read request returns its corresponding the requested data.
PCT/SE1999/001962 1998-10-30 1999-11-01 A method for delivering data to an instruction processing unit WO2000026741A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU14326/00A AU1432600A (en) 1998-10-30 1999-11-01 A method for delivering data to an instruction processing unit
EP99971528A EP1145094A3 (en) 1998-10-30 1999-11-01 A method for delivering data to an instruction processing unit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18286598A 1998-10-30 1998-10-30
US09/182,865 1998-10-30

Publications (2)

Publication Number Publication Date
WO2000026741A2 WO2000026741A2 (en) 2000-05-11
WO2000026741A3 true WO2000026741A3 (en) 2002-01-10

Family

ID=22670389

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1999/001962 WO2000026741A2 (en) 1998-10-30 1999-11-01 A method for delivering data to an instruction processing unit

Country Status (3)

Country Link
EP (1) EP1145094A3 (en)
AU (1) AU1432600A (en)
WO (1) WO2000026741A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8255669B2 (en) 2008-01-30 2012-08-28 International Business Machines Corporation Method and apparatus for thread priority control in a multi-threaded processor based upon branch issue information including branch confidence information

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2310743A (en) * 1996-03-01 1997-09-03 Hewlett Packard Co Tracking cache misses in out-of-order instruction execution
US5787465A (en) * 1994-07-01 1998-07-28 Digital Equipment Corporation Destination indexed miss status holding registers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787465A (en) * 1994-07-01 1998-07-28 Digital Equipment Corporation Destination indexed miss status holding registers
GB2310743A (en) * 1996-03-01 1997-09-03 Hewlett Packard Co Tracking cache misses in out-of-order instruction execution

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BELAYNEH S ET AL: "A DISCUSSION ON NON-BLOCKING/LOCKUP-FREE CACHES", COMPUTER ARCHITECTURE NEWS, vol. 24, no. 3, June 1996 (1996-06-01), pages 18 - 25, XP000641020 *
FARKAS K I ET AL: "COMPLEXITY/PERFORMANCE TRADEOFFS WITH NON-BLOCKING LOADS", COMPUTER ARCHITECTURE NEWS, vol. 22, no. 2, 1 April 1994 (1994-04-01), pages 211 - 222, XP000450352 *

Also Published As

Publication number Publication date
AU1432600A (en) 2000-05-22
EP1145094A2 (en) 2001-10-17
EP1145094A3 (en) 2002-03-27
WO2000026741A2 (en) 2000-05-11

Similar Documents

Publication Publication Date Title
WO2002054230A3 (en) System and method for prefetching data into a cache based on miss distance
CA2249392A1 (en) Pixel engine data caching mechanism
US5961631A (en) Data processing apparatus and method for pre-fetching an instruction in to an instruction cache
WO2002017086A3 (en) Method and apparatus for pipelining ordered input/output transactions in a cache coherent, multi-processor system
GB2358941A (en) Processing ordered data requests to a memory
WO2002041155A3 (en) Method and apparatus for implementing pci dma speculative prefetching in a message passing queue oriented bus system
KR970029103A (en) Data processing system and data processing method
EP1031919A3 (en) Method for prefetching structured data
TW253946B (en) Data processor with branch prediction and method of operation
EP0735487A3 (en) A fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
IL169265A0 (en) Page descriptors for prefetching and memory management
MY104738A (en) Control of pipeland operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller.
CA2357085A1 (en) Cache update method and cache update control system employing non-blocking type cache
IL135044A0 (en) Cache memory operation
WO2003025757A3 (en) Method and apparatus for decoupling tag and data accesses in a cache memory
WO2004031964A3 (en) Method and apparatus for reducing overhead in a data processing system with a cache
US20030018853A1 (en) Method and apparatus for filling lines in a cache
ATE389208T1 (en) ASSOCIATIVE MEMORY FOR CACHE STORAGE
EP1011048A3 (en) cache controlling apparatus for dynamically managing data between cache modules and method thereof
US5367657A (en) Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems
WO2004088461A3 (en) Local emulation of data ram utilizing write-through cache hardware within a cpu module
US6308241B1 (en) On-chip cache file register for minimizing CPU idle cycles during cache refills
WO2002054256A3 (en) Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device
EP1107110A3 (en) Instruction loop buffer
WO2000026741A3 (en) A method for delivering data to an instruction processing unit

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref country code: AU

Ref document number: 2000 14326

Kind code of ref document: A

Format of ref document f/p: F

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1999971528

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 1999971528

Country of ref document: EP

AK Designated states

Kind code of ref document: A3

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG