WO2000025511A1

WO2000025511A1 - Methods and apparatus for charge coupled device image acquisition with selective vertical readout

Info

Publication number: WO2000025511A1
Application number: PCT/US1999/023356
Authority: WO
Inventors: David R. King
Original assignee: Cognex Corporation
Priority date: 1998-10-23
Filing date: 1999-10-07
Publication date: 2000-05-04

Abstract

An image acquisition method and apparatus uses timing logic that permits selective readout of portions of an image stored in a charge coupled device (CCD). That logic selectively skips portions of the image not of interest, e.g., by applying a succession of 'vertical' clocking signals to the CCD, causing it to transfer lines of image data to a readout register. No or few 'horizontal' clocking signals are applied in connection with the line-skipping operation, thereby, reducing or eliminating time otherwise occupied outputting unwanted pixels from the readout register. The timing logic also selectively generates a 'conventional' sequence of interspersed horizontal and vertical clocking signals, causing the CCD to output pixels from lines of the image of interest.

Description

METHODS AND APPARATUS FOR CHARGE COUPLED DEVICE IMAGE ACQUISITION WITH SELECTIVE VERTICAL READOUT

Background of the Invention

This application claims the benefit of priority of United States Provisional Patent Application Serial No. 60/105,499, filed October 23, 1998, the teachings of which are incorporated herein by reference.

The invention pertains to image acquisition and, particularly, to the control and readout of images acquired using charge coupled devices. The invention has application in video cameras and other image acquisition devices used in machine vision and in other industrial, research and recreational environments.

Manufacturers of video cameras and other digital image acquisition devices are increasingly reliant on charge coupled devices (CCD's) to capture images. These devices are made up of hundreds or thousands of microscopic semiconductor elements arranged in closely spaced arrays. When the array is exposed to light (or other radiation), each of its constituent elements accumulates an electronic charge proportional to the number of photons that strike it. By focusing a scene on such an array, an electronic image is formed with brighter regions ofthe scene corresponding to more highly charged elements and darker regions corresponding to less highly charged ones.

Typically, only one-half of the elements in a CCD array are used to collect light. In one prior art design, referred to as the interline transfer CCD, rows (or columns) of photosensitive elements are alternated with rows (or columns) of non- sensitive elements. The latter serve as "conduits" to transfer the electronic charges from the photosensitive elements to an output buffer, or readout register.

The acquisition of an image in a typical CCD array occurs over several phases. To begin, the photosensitive elements are grounded or "reset" to remove all previously accumulated charge. Once this is completed, light (or other energy) from a lens begins to accumulate, forming an image. Since CCD devices are not typically equipped with mechanical shutters, accumulation continues until the charges built-up in each ofthe photosensitive elements are transferred to the corresponding non- photosensitive elements. The period following the reset and before the transfer is, accordingly, referred to as the integration or shuttering period.

According to prior art image acquisition system designs, once the integration period ends, the charges transferred to the non-photosensitive elements are shifted up each column of non-photosensitive elements to the horizontal readout register. From there, they are output to a host device (e.g., machine vision workstation) and/or display to which the CCD has been coupled.

The size ofthe data stream generated by prior art CCD-based image acquisition devices is dependent on the size ofthe CCD array itself. For example, a camera based on the popular RSI 70 video standard with a 780 x 494 CCD array will necessarily generate an image data stream of about that size (i.e., technically, 640 x

480), whenever the shutter is triggered. The time required to output such an image data stream, too, is directly based on the size ofthe CCD array. The data stream size and readout time cannot be varied, according to the prior art, even if only a small number of lines within the image are to be used.

An object of this invention is to provide improved methods and apparatus for image acquisition and, more particularly, improved methods and apparatus for using charge coupled devices to acquire images.

Another object is to provide such methods and apparatus as speed the acquisition of images and reduce the size of image data streams, for example, in instances where regions of interest constitute less than an acquisition device's field of view.

Another object is to provide such methods and apparatus as reduce the resources required for, and costs associated with, image acquisition. Still another object ofthe invention is to provide such devices and methods as permit greater control of image acquisition using charge coupled devices.

Summary of the Invention

The foregoing are among the objects attained by the invention, aspects of which provide an image acquisition apparatus with timing logic that permits selective readout of portions of an image acquired by a charge coupled device (CCD). That timing logic selectively skips portions ofthe image not of interest, e.g., by applying a succession of "vertical" clocking signals to the CCD, without corresponding "horizontal" clocking signals. This causes the CCD to transfer lines of image data to a readout register where, in the absence of horizontal clocking they are, in effect, "merged" — or, more accurately, accumulated with prior and subsequent lines of skipped data. The timing logic also selectively generates, e.g., after the line-skipping phase, a "conventional" sequence of interspersed horizontal and vertical clocking signals, causing the CCD to transfer lines to the readout register and to output them, e.g., to a host.

By way of example, an image acquisition apparatus according to the invention can rapidly generate an image from intermediate lines of a CCD. To this end, the aforementioned timing logic performs a line-skipping operation (e.g., issuing a succession of vertical clocking signals with few or no horizontal clocking signals) to skip past an initial portion ofthe image. The logic then performs a line-readout operation (e.g., issuing a sequence of interspersed vertical and horizontal clocking signals) outputting pixels of interest to the host. Since few or no "horizontal" clocking signals are applied in connection with the line-skipping operation, time otherwise required to output unwanted pixels from the readout register is reduced or eliminated.

Related aspects ofthe invention provide for execution of multiple "cycles" of line-skipping and line-readout operations, wherein the "skipping" process is started and stopped dynamically, allowing multiple sub-regions ofthe CCD array to be accessed in an optimized fashion, e.g., as required by the host.

Further aspects ofthe invention pertain to the number of horizontal clocking signals applied by the timing logic to the CCD during the line-skipping phase. In preferred aspects ofthe invention, that number is zero or substantially zero (i.e., a minimum number of HCLK pulses, if any, required to electrically discharge the CCD's readout register of unwanted pixel data). In other aspects that number is less than "N," where N is the number of horizontal clocking signals applied during the line-readout phase. Thus, if during the readout phase the timing generator applies, say, 640 horizontal clocking signals to the CCD for each line clocked into the readout register, the number of horizontal clocking signals applied to the CCD during the line-skipping phase is less than 640 and, preferably, substantially less than 640 (e.g., zero).

In other aspects, the invention provides apparatus as described above in which the timing logic performs the line-skipping operation zero or more times, depending on the value of an applied code ~ referred to hereinafter as a selective vertical readout (SNR) code. For example, an SVR value of zero may indicate that no lines ofthe image are to be skipped; a value of one may indicate that a first line or a first successive group of lines is to be skipped; a value of two may indicate that first and second lines (or successive groups of lines) are to be skipped; and so forth.

Further aspects ofthe invention provide an image acquisition apparatus as described above in which the line-skipping phase is initiated by a "transfer" signal, e.g., generated by a host or by further logic in the acquisition apparatus itself. According to this aspect, the line-readout operation can be initiated by a "read" signal that is also generated, for example, by the host or other logic within the acquisition apparatus.

Still other aspects ofthe invention provide improvements to an image acquisition apparatus ofthe type having a charge coupled device (CCD) with a readout register and plural image collection sites arranged into a plurality of rows (lines) and columns (pixels). The improvement is characterized by a timing generator that performs line-skipping and line-readout operations as described above.

Yet still further aspects ofthe invention provide methods of operating an image acquisition device paralleling the operations described above.

These and other aspects ofthe invention are evident in the drawings and in the description that follows. Apparatus constructed and/or operated in accord with the invention have utility in industry, research, recreation and other areas of pursuit.

Such apparatus, which have particular application, by way of example, in machine vision, facilitate the rapid generation of images from CCD-based cameras and other image acquisition devices. They also facilitate generation of data streams sized in accord with regions of interest.

Brief Description of the Drawings

A more complete understanding ofthe invention may be attained by reference to the drawings, in which:

Fig. 1 depicts a machine vision system employing a charge coupled device (CCD) image acquisition apparatus according to the invention;

Fig. 2 depicts a CCD image acquisition apparatus according to a practice of the invention;

Figs. 3 - 4 depict sequences of timing and data signal generation in a CCD image acquisition apparatus according to the invention; and

Fig. 5 depicts a methodology of signal generation and operation in a CCD image acquisition apparatus according to the invention. Detailed Description of the Illustrated Embodiment

Fig. 1 depicts a machine vision system 10 employing a charge coupled display (CCD) image acquisition apparatus 12 in accord with the invention. Though illustrated in connection with such a system, those skilled in the art will appreciate that apparatus and methods according to the invention have utility in other imaging applications, as well.

Illustrated system 10 includes a host processing unit 14, which is coupled to image acquisition apparatus 12 by way of bus 16. In a preferred embodiment, host 14 represents a machine vision workstation or "vision processor," e.g., ofthe type commercially available in the marketplace and, preferably, from the assignee hereof. Alternatively, it represents any special or general purpose digital data processing apparatus ofthe type used in obtaining and/or processing image data from an image acquisition device. Bus 16 preferably represents a "backplane" or other high-speed data link between host 14 and image acquisition apparatus 12. Alternatively, it can represent a network link (e.g., LAN or WAN), telecommunications link (e.g., via modem) or other communications link suitable for passing commands and/or image data between the illustrated devices.

Image acquisition device 12 is a camera or other device suitable for image acquisition via a charge coupled device (CCD). In the illustrated embodiment, device 12 is a video camera adapted for use in machine vision. Of course, the teachings herein may be applied to still cameras, video cameras or other image acquisition devices adapted to other applications.

Acquisition device 12 includes a camera control unit (CCU) 18 and a camera head unit (CHU) 20 that serve functions analogous to those of like-named components of conventional image acquisition devices in use the marketplace. Thus, for example, CCU 18 serves as an interface between host 14 and image acquisition device 12, ter alia, interpreting commands from the host to the image acquisition device, and reformatting data generated by the image acquistion device for transmission to the host. Illustrated CCU 18 and CHU 20 are, more particularly, constructed and operated in the manner described herein to permit selective readout of image data contained in portions of CCD array.

Illustrated image acquisition device 12 includes a CCD array 22 of type conventionally used for image acquisition. This is preferably an interline transfer CCD, though other CCD arrays amenable for use in conjunction with the teachings herein may be used as well. CCD array 22 includes a plurality of image collection sites arranged into a plurality of rows and columns. In one embodiment, for example, those sites are arranged in an array of 640 x 480. Other sizes and arrangement of photosensitive collection sites can be used as well. As used herein, the rows ofthe array are referred to as "lines," whereas the individual columns in each row are referred to as "pixels."

Per convention, CCD array 22 responds to applied vertical clock (VCLK) signals by transferring successive lines of image data to a readout register (not shown). Successive pixels in that register are output, e.g., to an analog digital converter in the CCU 18, in response to applied horizontal clock (HCLK) signals.

Illustrated machine vision system 10 is shown imaging an object 24 utilizing image acquisition device 12 as discussed hereinbefore and hereinafter. More particularly, CCU 18 services requests by processing commands received from the host 14 over the bus 16 and, in turn, issues ShutterJL and Readout_L pulses, along with an SVR control code to the CHU, all as described in further detail below. The

Shutter-L pulse is used to control the integration time ofthe CHU 20, while the ReadoutJ signal initiates the readout cycle. The SVR code is a three-bit code in the illustrated embodiment — and, hence, is referred to as SVR(2:0) ~ used to by the CHU 18 to determine which regions ofthe image in the CCD array 22 are to be skipped over. Fig. 2 depicts an image acquisition apparatus 12 according to one practice of the invention. Referring to the drawing, CHU 20 includes a decoder 26 that synchronizes the Shutter_L and Readout_L signals with the CHU's internal clocking. The decoder 26 also generates pulses that initiate and control the generation of images by the CCD 22. To this end, the decoder 26 generates a Reset pulse that causes CCD timing generator 28 to clear its photosensitive sites in preparation for a new integration cycle. The Transfer pulse informs the CCD timing generator 28 that the integration cycle has expired and that the charges currently residing in the photo-sensitive areas ofthe array 22 are to be moved into the non-photosensitive readout sites. The Read pulse informs the CCD timing generator that the CCU 18 is ready to accept the image and that a sequence of vertical and horizontal transfer cycles (VCLK and HCLK) required to output the contents ofthe CCD sensor should be executed. The CHU 20 generates a video signal (Video), a pixel clock (PCLK), and a data validation signal (DataValid_L) for application to the CCU 20 as described below.

Illustrated CCU 18 includes acquire timing generator 30 that processes commands received from the host 14 via bus 16. It is responsible for setting the SVR(2:0) code lines (e.g., a three-wire bus segment) based on an SVR value selected, e.g., by the host 14. Timing generator 30 is also responsible for issuing the sequence of Shutter_L and Readout_L signals required by the CHU 20. The acquire timing generator 30 receives pixel clock (PCLK) and data validation (DataValid_L) signals from the CHU 20. These signals are used to derive the clock required for the analog to digital (A/D) converter 32, as well as to qualify the validity ofthe digitized data (ImageData) prior to transmitting it to the host 14 via bus 16.

With continued reference to Figure 2, the image acquisition device 12 includes a progressive scan CCD array 22 consisting of Total ActiveLines lines, each with M active pixels. That array is divided into vertical segments 22a - 22h which, in the illustrated embodiment, are of equal size, as governed by the equation:

VsegmentSize = TotalActiveLines/[SVR(2:0)+l] where:

TotalActiveLines is the maximum possible vertical resolution ofthe CCD 22 (e.g. 480);

SVR(2:0) is the decimal representation ofthe maximum value for the selectable vertical readout code, e.g., seven in the illustrated embodiment; and

VsegmentSize is the number of lines contained within any one vertical sub-region ofthe CCD.

In order to produce an image, a CCD requires three basic cycles. The first, the reset cycle, is used to clear any residual charge from the photo-sensitive areas, effectively forcing the pixels to black. The next step, the transfer cycle (commonly referred to as the charge transfer interval), moves the charge accumulated since the most recent reset cycle into the non-photo-sensitive readout sites. Since the amount of charge accumulated is proportional to the length of time between the reset and transfer cycles the difference (in time) between these two constitutes an electronic shutter mechanism. The final step involves the readout cycle which is used to move the individual pixels from the readout sites to the CCU 18. This step, requiring a vertical transfer clock (VCLK) sequence, involves moving an entire line of pixels from their protected cells into a horizontal readout register. Once there, the pixels are then shifted out serially using a series of horizontal transfer clock (HCLK) cycles at a rate dictated by the CHU's 20 internal pixel clock (PCLK) rate. The total number of horizontal clock cycles per line and vertical clock cycles per frame is dictated by the number of rows and columns contained within the CCD.

In an image acquisition device according to the invention, the selective vertical readout code, SVR, determines what portion ofthe CCD array 22 is output to the CCU 18 upon issuance ofthe Read pulse: with SVR(2:0) equal to 0 the entire contents ofthe CCD image are transferred to the CCU; with SVR(2:0) equal to 1, the CCD timing generator 28 (i) issues VCLK pulses that cause the first segment 22a of the array 22 to be skipped over, (ii) issues interleaved VCLK and HCLK pulses that cause image data in the remaining segments 22b - 22h to be transferred to the CCU; with SVR(2:0) equal to 2, the CCD timing generator 28 (i) issues VCLK pulses that cause the first two segments 22a - 22b ofthe array 22 to be skipped over, (ii) issues interleaved VCLK and HCLK pulses that cause image data in the remaining segments 22c - 22h to be transferred to the CCU; and so forth.

The relationship governing the total number of lines output by the CCD array 22 to CCU 18, e.g., for transfer to the host 14 is:

LinesAcquired = TotalActiveLines - [VSegmentSize x SNR(2:0)]

Fig. 3 illustrates a sequence of clocking and data signals generated in connection with the acquisition and outputting of entire image from the CCD 22.

That sequence may be better understood through the discussion that follows, as annotated with parenthetical references to Fig. 5, which illustrates the methodology behind such signal generation.

At the outset, host 14 loads a "shutter duration and SVR control" command into registers ofthe acquire timing generator 30. Included in the command are the duration ofthe shutter pulse (in microseconds) and the selected vertical readout (i.e., indicating which subregions 22a-22h of array 22 are to be skipped). These values can be programmed, along with the command itself, into the generator's 30 registers. A Host Write signal loads the "start shutter" command, informing the CCU 18 that a new image acquisition sequence should be started. (See, Step 60 of Fig. 5).

Upon decoding the "start shutter" command, the acquire timing generator 30 sets the value of SVR(2:0) for the upcoming acquire and asserts the Shutter_L pulse for the specified duration. (Step 62). The high to low transition (i.e. leading edge) ofthe Shutter_L pulse is detected by the decoder 26, which then asserts the Reset signal. (Step 64). Upon sensing the Reset signal, the timing generator 28 executes the CCD sensor clock sequence required to clear out any charge remaining in the photo-sensitive areas ofthe CCD sensor.

The integration period is terminated by the low to high transition (trailing edge) ofthe Shutter_L pulse. (Step 66). This edge, when sensed by the decoder 26 causes it to issue the Transfer pulse (Step 68) which, in turn, informs the timing generator 28 that the charge currently residing in the photo-sensitive collection sites is to be transferred to the corresponding non-photo-sensitive (i.e. protected) readout sites.

Once the charge transfer cycle is complete the image is ready to be transmitted to the CCU 18. In the illustrated embodiment, no further action is taken until the host 14 informs the acquire timing generator 30 that it is ready to accept the image.

Upon receiving a "start readout" instruction from the host 14, the acquire timing generator 30 asserts the readout signal, ReadoutJ (Step 70). The high to low transition (i.e. leading edge) of this signal causes the decoder 26 to issue a Read strobe. (Step 72). This pulse, in turn, causes the timing generator 28 to commence the sequence of vertical and horizontal clock cycles (Steps 74, 76) required to completely transfer the image residing in the readout cells to the CCU 18 (Step 78), where it is digitized and passed along to the host 14 (Step 80) via the bus 16.

As shown in Fig. 3, prior to asserting DataValid_L the timing generator 28 asserts a single vertical clock cycle (VCLK) to move one line of charge into the readout register. This is followed by a burst of M horizontal clock pulses (HCLK) where M is the total number of pixels per line ofthe array 22. The data validation signal (DataValid_L) is used by the CCU 18 to distinguish between valid and invalid portions ofthe video signal. The pixel clock (PCLK) ensures that the video signal (Video) is sampled at its" optimum point at the A/D converter in order to maximize the accuracy ofthe digitalization process. Fig. 4 illustrates a sequence of clocking and data signals generated in connection with the acquisition and outputting of a vertical subregion of an image from the CCD 22. As above, the discussion of that figure is annotated with parenthetical references to Fig. 5,

A distinction between the timing sequences of Figs. 3 and 4 is addition ofthe line skipping sequence. This period is used to rapidly scan over the unwanted vertical lines ofthe CCD 22. The skip interval is automatically initiated by the timing generator 28 whenever the Read pulse is asserted and SVR(2:0) is non-zero. The detail signal breakout at the bottom of Fig. 4 illustrates this process. During this interval, the timing generator 28 calculates how many lines must be discarded prior to starting the normal readout process. This is a function ofthe SVR(2:0) signals and, more particularly, ofthe expression:

LinesSkipped = VSegmentSize x SVR(2:0)

During the line-skipping phase (Step 73 of Fig. 5) , the timing generator 28 (Figure 3) asserts multiple vertical clock signals and no HCLK signal — apart from those necessary to discharge the CCD's horizontal readout register (i.e., to discharge previously dumped line pixels). In one embodiment, a 6: 1 ratio (or, more generally,

N: 1) of VCLK to HCLK signals is used, wherein 6 (or N) lines are clocked into the readout register via application of VCLK pulses for each burst of HCLK pulses (which discharge or "condition" the readout register to accept additional lines). Because these HCLK pulses are merely used to recondition the register to accept further data, the data valid signal is not set (as it would be for an actual readout operation).

Once the skip cycle has been completed, the timing generator 28 reverts back to the normal image readout sequence (Steps 74, 76) of one VCLK cycle for every burst of M HCLK pulses, asserting the data validation signal (DataValidJL) in accordance with the detail highlighted in Fig. 3. In further embodiments ofthe invention, multiple "cycles" of line-skipping and line-readout operations are executed. Thus, for example, at the request ofthe host, the "skipping" process is started and stopped dynamically, thereby skipping multiple sub-regions ofthe CCD array. As discussed above, the data validation signal (DataValid L) is used by the CHU 20 to distinguish between valid and invalid portions ofthe video signal, while the pixel clock (PCLK) signal ensures that the video signal (Video) is sampled at its optimum point at the A/D converter 32 in order to maximize the accuracy ofthe digitalization process.

Described above are methods and apparatus meeting the desired goals. Those skilled in the art will appreciate that the embodiments shown in the drawing are merely examples ofthe invention and that other embodiments, incorporating changes therein, fall within the scope ofthe invention. Thus, by way of non-limiting example, it will be appreciated that, whereas the illustrated embodiment utilizes a CCD array that transfers pixels vertically to a readout register whence they are output horizontally, the invention has equal application to arrays in which these orientations are "reversed" or otherwise altered (e.g., arrays that transfer pixels horizontally to a readout register whence they are output vertically). In such cases, the application of clocking signals is reversed or otherwise altered accordingly.

By way of further non-limiting example, it will be appreciated that the CCD array can be divided into greater or fewer subregions than those show in Fig. 2 and discussed above. Likewise, it will be appreciated that different codes or bit patterns can be used in place of SVR(2:0), referred to in the illustrated embodiment.

By way of still further non-limiting example, it will be appreciated that the line-skipping operation can be initiated in response to a Transfer pulse, e.g., as opposed to being initiated in response to a Read pulse. In such cases, the timing of Read pulse generation is adjusted to correspond with the end ofthe like-skipping operation.

Claims

In via ofthe foregoing, what I claim is:

1. An image acquisition apparatus comprising:

a charge coupled device (CCD) having a readout register and having a plurality of image collection sites arranged into a plurality of lines, each of which contains a plurality of pixels,

the CCD responding to a first signal by transferring one or more successive lines to the readout register, and responding to a second signal by outputting one or more successive pixels from the readout register,

first timing logic that is coupled to the CCD, the first timing logic performing, one or more times, a line skipping step comprising the successive substeps of:

i. applying to the CCD the first signal,

ii. applying the second signal to the CCD fewer than M times, where

M is an integer,

the first timing logic performing, one or more times, a line readout step comprising the successive substeps of

i. applying to the CCD the first signal,

ii. applying the second signal to the CCD at least M times.

2. An image acquisition apparatus according to claim 1 , wherein the first timing logic performs the line skipping step, then, performs the line readout step.

3. An image acquisition apparatus according to claim 2, wherein the first timing logic performs the line skipping step one or more times, depending on a value of an applied selective readout signal.

4. An image acquisition apparatus according to claim 3, wherein the first timing logic performs the line skipping step a number of times proportional to a value ofthe selective readout signal.

5. An image acquisition apparatus according to claim 4, wherein the first timing logic responds to a read signal by performing the line skipping step one or more times, depending on a value ofthe selective readout signal, and wherein the first timing logic responds to a read signal by performing the line readout step.

6. An image acquisition apparatus according to claim 5, comprising second timing logic that generates the read signal.

7. An image acquisition apparatus according to claim 6, wherein the second timing logic generates the transfer signal as a function of an applied shutter signal, and generates the read signal as a function of an applied readout signal.

8. An image acquisition apparatus according to claim 7, wherein the first timing logic performs the line skipping step a number of times proportional to a value ofthe selective readout signal, and wherein the first timing logic performs the line readout step a number of times sufficient to cause it to output at least a portion ofthe pixels in the line currently in the buffer.

9. An image acquisition apparatus according to claim 1 , wherein the first timing logic responds to a read signal by performing the line skipping step one or more times, depending on a value ofthe selective readout signal.

10. An image acquisition apparatus according to claim 9, wherein the first timing logic performs the line skipping step a number of times proportional to a value ofthe selective readout signal.

11. An image acquisition apparatus according to claim 1 , wherein the first timing logic responds to a read signal by performing the line readout step.

12. An image acquisition apparatus according to claim 11 , wherein the first timing logic performs the line readout step a number of times sufficient to cause it to output at least a portion ofthe pixels in the line currently in the buffer.

13. An image acquisition apparatus comprising:

a charge coupled device (CCD),

the CCD responding to a first signal by transferring one or more successive lines to a buffer and responding to a second signal by outputting one or more successive pixels from the buffer,

i. applying to the CCD a first signal,

ii. applying the second signal to the CCD substantially zero times,

i. applying to the CCD a first signal, ii. applying the second signal to the CCD to cause it to output at least a portion ofthe pixels in the line currently in the buffer.

14. An image acquisition apparatus according to claim 13, wherein the first timing logic performs the line skipping step, then, performs the line readout step.

15. An image acquisition apparatus according to claim 14, wherein the first timing logic performs the line skipping step one or more times, depending on a value of an applied selective readout signal.

16. An image acquisition apparatus according to claim 15, wherein the first timing logic performs the line skipping step a number of times proportional to a value ofthe selective readout signal.

17. An image acquisition apparatus according to claim 16, wherein the first timing logic responds to a read signal by performing the line skipping step one or more times, depending on a value ofthe selective readout signal, and then performs the line readout step.

18. An image acquisition apparatus according to claim 17, wherein the first timing logic performs the line skipping step a number of times proportional to a value ofthe selective readout signal, and wherein the first timing logic performs the line readout step a number of times sufficient to cause it to output at least a portion ofthe pixels in the line currently in the buffer.

19. An image acquisition apparatus according to claim 18, comprising second timing logic that generates the read signal.

20. An image acquisition apparatus according to claim 19, wherein the second timing logic generates read signal as a function of an applied readout signal.

21. An image acquisition apparatus according to claim 13, wherein the first timing logic responds to a read signal by performing the line skipping step one or more times, depending on a value ofthe selective readout signal.

22. An image acquisition apparatus according to claim 21 , wherein the first timing logic performs the line skipping step a number of times proportional to a value ofthe selective readout signal.

23. An image acquisition apparatus according to claim 13, wherein the first timing logic responds to a read signal by performing the line readout step.

24. In image acquisition apparatus ofthe type having

the CCD responding to vertical clock (VCLK) signal by transferring one or more successive lines to the readout register, and responding to a horizontal clock (HCLK) signal by outputting one or more successive pixels from the readout register,

the improvement wherein the image acquisition apparatus comprises

a timing generator, coupled to the CCD, that performs a line skipping step comprising:

i. applying the VCLK signal to the CCD,

ii. applying the HCLK signal to the CCD substantially zero times,

the timing generator performing a line readout step comprising: i. applying the VCLK signal to the CCD,

ii. applying the HCLK signals to the CCD to cause it to output at least a portion ofthe pixels in the line currently in the buffer.

35. In an image acquisition apparatus according to claim 34 , the further improvement wherein the timing generator performs the line skipping step, then, performs the line readout step.

36. In an image acquisition apparatus according to claim 35 , the further improvement wherein the timing generator performs the line skipping step one or more times, depending on a value of an applied selective readout signal.

37. In an image acquisition apparatus according to claim 36, the further improvement wherein the timing generator performs the line skipping step a number of times proportional to a value ofthe selective readout signal.

38. In an image acquisition apparatus according to claim 37, the further improvement wherein the timing generator responds to a read signal by performing the line skipping step one or more times, depending on a value of the selective readout signal, and wherein the timing generator then performs the line readout step.

39. In an image acquisition apparatus according to claim 38, the further improvement wherein the timing generator performs the line skipping step a number of times proportional to a value ofthe selective readout signal, and wherein the timing generator performs the line readout step a number of times sufficient to cause it to output at least a portion ofthe pixels in the line currently in the buffer.

40. In an image acquisition apparatus according to claim 34, the further improvement wherein the timing generator responds to a read signal by performing the line skipping step one or more times, depending on a value of the selective readout signal.

41. In an image acquisition apparatus according to claim 40, the further improvement wherein the timing generator performs the line skipping step a number of times proportional to a value ofthe selective readout signal.

42. In an image acquisition apparatus according to claim 34 , the further improvement wherein the timing generator responds to a read signal by performing the line readout step.

43. A method of operating an image acquisition apparatus of the type having

the method comprising the steps of:

performing one or more times a line skipping step comprising:

i. applying to the CCD the first signal,

ii. applying the second signal to the CCD fewer than M times, where

M is an integer, performing one or more times a line readout step comprising:

i. applying to the CCD the first signal,

ii. applying the second signal to the CCD at least M times.

44. A method of operating an image acquisition apparatus according to claim 43, comprising performing the line skipping step, then, performing the line readout step.

45. A method of operating an image acquisition apparatus according to claim 44, comprising the step of performing the line skipping step one or more times, depending on a value of an applied selective readout signal.

46. A method of operating an image acquisition apparatus according to claim 45, comprising the step of performing the line skipping step a number of times proportional to a value ofthe selective readout signal.

47. A method of operating an image acquisition apparatus according to claim 46, comprising the steps of responding to a read signal by performing the line skipping step one or more times, depending on a value ofthe selective readout signal, and responding to a read signal by performing the line.

48. A method of operating an image acquisition apparatus according to claim 47, comprising the step of generating the read signal as a function of an applied readout signal.

49. A method of operating an image acquisition apparatus according to claim 48, comprising the step of performing the line skipping step a number of times proportional to a value ofthe selective readout signal, and performing the line readout step a number of times sufficient to cause at least a portion ofthe pixels in the line currently in the buffer to be output.

50. A method of operating an image acquisition apparatus according to claim 43, comprising the step of responding to a read signal by performing the line skipping step one or more times, depending on a value ofthe selective readout signal.

51. A method of operating an image acquisition apparatus according to claim 50, comprising the step of performing the line skipping step a number of times proportional to a value ofthe selective readout signal.

52. A method of operating an image acquisition apparatus according to claim 43, comprising the step of responding to a read signal by performing the line readout step.

53. A method of operating an image acquisition apparatus according to claim 52, comprising the step of performing the line readout step a number of times sufficient to cause at least a portion ofthe pixels in the line currently in the buffer to be output.

54. A method of operating an image acquisition apparatus ofthe type having

a charge coupled device (CCD),

the method comprising the steps of:

performing one or more times a line skipping step comprising:

i. applying to the CCD a first signal, ii. applying the second signal to the CCD substantially zero times,

performing one or more times a line readout step comprising:

i. applying to the CCD a first signal,

ii. applying the second signal to the CCD to cause at least a portion of the pixels in the line currently in the buffer to be output.

55. A method of operating an image acquisition apparatus according to claim 54, comprising performing the line skipping step, then, performing the line readout step.

56. A method of operating an image acquisition apparatus according to claim 55, comprising the step of performing the line skipping step one or more times, depending on a value of an applied selective readout signal.

57. A method of operating an image acquisition apparatus according to claim 56, comprising the step of performing the line skipping step a number of times proportional to a value ofthe selective readout signal.

58. A method of operating an image acquisition apparatus according to claim 57, comprising the steps of responding to a read signal by performing the line skipping step one or more times, depending on a value ofthe selective readout signal, and then performing the line readout step.

59. A method of operating an image acquisition apparatus according to claim 58, comprising the steps of performing the line skipping step a number of times proportional to a value ofthe selective readout signal, and performing the line readout step a number of times sufficient to cause at least a portion ofthe pixels in the line currently in the buffer to be output.

60. A method of operating an image acquisition apparatus according to claim 59, comprising the step of generating a transfer signal as a function of an applied shutter signal, and then generating the read signal as a function of an applied readout signal.

61. A method of operating an image acquisition apparatus according to claim 54, comprising the step of responding to a read signal by performing the line skipping step one or more times, depending on a value of the selective readout signal.

62. A method of operating an image acquisition apparatus according to claim 61, comprising the step of performing the line skipping step a number of times proportional to a value ofthe selective readout signal.

63. A method of operating an image acquisition apparatus according to claim 54, comprising the step of responding to a read signal by performing the line readout step.

64. In a method of operating an image acquisition apparatus ofthe type having

the improvement comprising the steps of

performing a line skipping step comprising: i. applying the VCLK signal to the CCD,

ii. applying the HCLK signal to the CCD substantially zero times,

performing a line readout step comprising::

i. applying the VCLK signal to the CCD,

ii. applying the HCLK signals to the CCD to cause at least a portion ofthe pixels in the line currently in the buffer to be output.

75. In a method of operating an image acquisition apparatus according to claim

74, the further improvement comprising performing the line skipping step, then, performing the line readout step.

76. In a method of operating an image acquisition apparatus according to claim

75, the further improvement comprising performing the line skipping step one or more times, depending on a value of an applied selective readout signal.

77. In a method of operating an image acquisition apparatus according to claim

76, the further improvement comprising performing the line skipping step a number of times that proportional to a value ofthe selective readout signal.

78. In a method of operating an image acquisition apparatus according to claim 77, the further improvement comprising responding to a read signal by performing the line skipping step one or more times, depending on a value of the selective readout signal, and then performing the line readout step.

79. In a method of operating an image acquisition apparatus according to claim 78, the further improvement comprising performing the line skipping step a number of times that proportional to a value ofthe selective readout signal, and performing the line readout step a number of times sufficient to cause at least a portion ofthe pixels in the line currently in the buffer to be output.

80. In a method of operating an image acquisition apparatus according to claim 74, the further improvement comprising responding to a read signal by performing the line skipping step one or more times, depending on a value of the selective readout signal.

81. In a method of operating an image acquisition apparatus according to claim 80, the further improvement comprising performing the line skipping step a number of times that proportional to a value ofthe selective readout signal.

82. In a method of operating an image acquisition apparatus according to claim 74, the further improvement comprising responding a read signal by performing the line readout step.