WO2000021134A1 - Esd protection circuit with pad capacitance-coupled parasitic transistor clamp - Google Patents

Abstract

An ESD protection circuit (150) has first (101) and second (102) circuit terminals, and a lateral bipolar junction transistor (Q), which has a collector terminal coupled to the first circuit terminal and an emitter terminal coupled to the second circuit terminal. A capacitor (C) is coupled between the first circuit terminal and base terminals of the bipolar junction transistor, wherein the base terminals are close to and in-line with the base region. The capacitor has a low impedance to ESD events applied to the first circuit terminal so that ESD events cause the bipolar junction transistor to turn on in forward conductance mode to conduct ESD current from said ESD event without breakdown of the collector-base junction of the transistor.

Description

ESD PROTECTION CIRCUIT WITH PAD CAPACITANCE-COUPLED PARASITIC TRANSISTOR CLAMP

CROSS-REFERENCES TO RELATED APPLICATIONS

This nonprovisional U.S. national application, filed under 35 U.S.C. § 111(a), claims, under 37 C.F.R. § 1.78(a)(3), the benefit of the filing date of provisional U.S. national application no. 60/103,010, filed on 10/5/1998 under 35 U.S.C. § 111(b), the entirety of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention The present invention relates to electrostatic discharge (ESD) protection, and, more particularly, for an ESD protection clamp circuit for protecting integrated circuits from electrostatic discharge.

Description of the Related Art

Various types of circuits and other devices are vulnerable to damage from electrostatic discharge (ESD), such as high voltages in electrical equipment, or from a user becoming electrostatically charged, for example by friction or induction. Integrated circuits (ICs), particularly ICs formed of MOS (metal-oxide semiconductor) transistors, are especially vulnerable to such ESD damage. ESD may be applied in this manner to input/output (I/O) or power pins or pads of the IC, which can damage the IC. As ICs have increased in complexity to include a larger number of circuit elements, the geometry of the circuit elements has decreased in order to maintain a relatively small IC size. With decreasing geometries of the circuit elements, providing adequate levels of ESD protection has become increasingly more difficult. In MOS circuits the gate oxide thickness has decreased to below 10 nanometers (nm), and breakdown voltages are often less than 10V and thus can be extremely sensitive to ESD. Fowler Nordheim (FN) tunneling through the oxide can occur below 7V. Device junction breakdown voltages, which are often used to protect the sensitive gate oxide directly, or to trigger a protection structure such as a snap- back device, have remained high to minimize hot carrier generation. In many cases, the minimum junction breakdown voltage is above the gate dielectric breakdown voltage.

Supply voltages have also been reduced. For IC devices having geometries down to

0.8 μm, supply voltages have been held at 5V. However, below that level, either dual supply (5V and 3.3N) supplies, or a single low- voltage supply have been used. As device geometries shrink ever further, even lower device voltages such as 2.0V are being utilized.

Various protection techniques have been developed to protect circuitry from ESD.

The main goal of ESD protection is to shunt ESD-caused current away from vulnerable circuitry and through a special path designed to handle such events at low voltages. Thus, the high voltage and current caused by ESD is diverted away from the main circuitry of the device. Such ESD circuits or structures (sometimes referred to as ESD protection circuits or clamps) may, for example, be placed in parallel across two input pins or pads, such as an I/O pad and ground, and therefore also in parallel across sensitive circuitry coupled to the two pads. Ideally, such ESD protection is invisible to the normal operation of the circuit, so that its presence does not slow down or otherwise negatively interfere with the operation of the remaining IC circuitry when no ESD event is occurring.

Some prior art clamping or triggering structures for ESD protection involve the use of zener diodes, which conduct current when a breakdown voltage is reached, thereby clamping the ESD voltage at a certain level. Such devices have been made using the lightly doped drain (LDD) diffusions and heavier source/drain diffusions of the MOS transistors of the IC to form zener diodes in the 6-8 volt range. However, if FΝ tunneling occurs below 7 volts, these zener diodes do not provide adequate I/O and gate protection for large ESD pulses if used to trigger larger energy-handling circuits. Lower voltage diodes cannot be easily made without adding additional process steps, and would tend to be leaky due to band- to-band tunneling.

Attempts have been made to provide ESD protection using a series of stacked diodes.

However, these suffer from a basic problem relating to the temperature coefficient of the diodes. The temperature coefficient of a single diode is about -2 mN/ C. Over the normal operating temperature range of -55 C to 125 C, the change in voltage is about 140 mV. For a ten-diode stack, the change would be approximately 1.4V. This change is sufficient to make a compromise between low leakage at high temperatures and adequate voltage protection margin at low temperature virtually impossible to achieve.

Two commonly-used ESD protection structures are the SCR (silicon or semiconductor controlled rectifiers), and the npn bipolar transistor. Both types of structures exhibit a low- voltage, low-resistance state (known as the holding or clamping voltage) when a certain triggering voltage (or current) has been reached. Usually, the triggering voltage is higher than the holding voltage. Unless specifically designed otherwise, the SCR usually has the lowest holding voltage.

SCRs have been used, both parasitically and deliberately, to protect ICs, such as the SCR techniques described in U.S. Pat. Nos. 4,400,711, 4,405,933, 4,631,567 and 4,692,781. The major advantage of these SCR protection structures is their high energy- absorbing capability. Similarly, various forms of protection structures have been built around the npn snap-back phenomenon, such as the structures and techniques described in U.S. Pat. No. 5,519,242. This and similar structures take advantage of the parasitic npn bipolar junction transistor existing in every NMOS transistor. Many of these approaches are now known as variants of the grounded-gate NMOS (ggNMOS).

Various problems have accompanied conventional ESD protection techniques. For example, some ESD protection clamps may have too high a leakage current, or may not trigger quickly enough for very fast transients. Also, the SCR techniques described above requires a finite time to reach the low-voltage clamping state once the required trigger current has been reached. This delay becomes increasingly serious as IC geometries shrink below the 0.3 μm level. The ggNMOS device is also vulnerable to failure because the gate oxide failure voltage is close to the junction breakdown voltage used to trigger the structure into the low-voltage clamping state. For these and other reasons, current ESD protection techniques and circuits may not work as well with current and future IC processes, which are accompanied by ever-stricter requirements.

It is, therefore, desirable for an ESD protection circuit or clamp to have a relatively low trigger voltage close to the holding voltage, with a very fast trigger or response time, in order to be compatible with ever-lower IC operating voltages having ever-more vulnerability to ESD. SUMMARY

An ESD protection circuit has first and second circuit terminals, and a lateral bipolar junction transistor, which has a collector terminal coupled to the first circuit terminal and an emitter terminal coupled to the second circuit terminal. A capacitor is coupled between the first circuit terminal and base terminals of the bipolar junction transistor, wherein the base terminals are close to and in-line with the base region. The capacitor has a low impedance to ESD events applied to the first circuit terminal so that ESD events cause the bipolar junction transistor to turn on in forward conductance mode to conduct ESD current from said ESD event without breakdown of the collector-base junction of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will become more fully apparent from the following description, appended claims, and accompanying drawings in which:

Fig. 1 is a schematic diagram of an integrated circuit (IC) having an ESD protection clamp circuit, in accordance with an embodiment of the present invention;

Fig. 2 is graph illustrating the current versus voltage characteristics of a prior art npn protection structure as well as that of the ESD protection clamp circuit of Fig. 1; and

Fig. 3 is diagram illustrating an IC layout of the protection clamp of Fig. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to Fig. 1, there is shown a schematic diagram of an integrated circuit

(IC) 100 having logic circuits 120 and an ESD protection clamp circuit 150, in accordance with an embodiment of the present invention. ESD protection clamp circuit 150 includes NMOS field-effect transistor (FET or MOSFET) M, parasitic npn transistor Q, and capacitor C, which has first and second capacitor terminals 151 and 152. Parasitic transistor Q and capacitor C together comprise the ESD protection clamp of the present invention. Capacitor

C may also be referred to as a pad capacitor.

ESD circuit 150 comprises two circuit or signal terminals or pads 101, 102, for coupling to outside nodes, signals, or devices such as a power supply and ground. Pad 102 may be coupled, for example, to ground or the common substrate, and is usually connected to an external source of reference potential. Pad 101 may be an I/O pin coupleable to an I/O signal or a power pin coupleable to an external source of positive voltage potential. (In an alternative embodiment, pad 101 always operates at equal or higher voltages than pad 102, even if pad 102 is at a potential other than ground.) An ESD voltage spike may be applied to pad 101 with respect to pad 102, and may damage circuitry of IC 100 such as logic circuits 120 coupled between pads 101 and 102.

The NMOS device (MOSFET M) defines an inherent, parasitic bipolar npn transistor Q, but does not function as an active NMOS device. In one embodiment, electrode or terminal 152 of capacitor C may be formed by integrating an N-well into the drain area of MOSFET M, and is thus inherently coupled to the drain terminal D of MOSFET M as well as to the collector c of the parasitic transistor Q. Electrode or terminal 151 of capacitor C may be formed by the same material (usually amorphous silicon or polysilicon) used to form the gate of MOSFET M, and is coupled to the base region of parasitic npn transistor Q.

Thus, as illustrated in Fig. 1, collector c of parasitic npn transistor Q is coupled to pad 101 , to the drain terminal D of MOSFET M, and to terminal 152 of pad capacitor C; and emitter e of transistor Q is coupled to pad 102 and the source terminal S of MOSFET M; and the base terminal b of transistor Q is coupled to terminal 151 of capacitor C. In an alternative embodiment, capacitor C may be formed or placed in other ways between the collector terminal and the base terminal of transistor Q. As will be appreciated, capacitor C provides a mechanism to dynamically couple the transient ESD voltage at terminal 101 to the base (Pbase region) of parasitic npn transistor Q. When an ESD pulse (which has an extremely high frequency components because of the inherently high rate of rise of an ESD event) is applied to pad 101, the impedance of capacitor C is very low, and the ESD pulse thus reaches the base terminal of transistor Q. This causes transistor Q to turn on to forward conductance at a certain triggering voltage, which allows the ESD current to flow between the collector c and emitter e of transistor Q, thus clamping the voltage at pad 101 to a maximum safe clamping voltage. In this manner, ESD transient noise switches on parasitic transistor Q via capacitor C to shunt ESD current from the ESD event from pad or terminal 101 to 102. As will be appreciated, one advantage of clamping circuit 150 is that transistor Q actually turns on to forward conductance, unlike a zener diode clamp or snap-back triggered device which operate in the breakdown mode. Because of this, the ESD-caused current is conducted more evenly through transistor Q than it would be through a semiconductor junction in the breakdown mode. This causes the impact ionization to be spread over a wider area, causing the ESD protection of the present invention to be less prone to local conduction damage as would occur if the device were allowed to breakdown between the collector and the emitter, relying on impact ionization to trigger the device into the conduction state. Parasitic npn transistor Q can conduct a large amount of current to shunt the ESD-caused current to ground via pad 102, depending on the emitter area facing the collector (the depth of the junction multiplied by the width of the emitter).

Referring now to Fig. 2, there is shown a graph 200 illustrating the current versus voltage characteristics of the prior art npn protection structure (curve 201) as well as that of the ESD protection clamp circuit (curve 208) of the present invention. The horizontal axis shows the ESD voltage across the protection structure as the current flowing therethrough increases due to an ESD event. In previous generations of ICs, the IC may operate at an operating voltage of 5V, and not be damaged until the voltage across the circuit due to an ESD reaches 20 or 25V. Thus, an ESD clamp may be used which is triggered at 10 or 12V, and which has a holding voltage of 6 or 7V, resulting in a delta between the triggering and holding voltages of 4V or more.

This is illustrated by curve 201 of Fig. 2, which shows the current- voltage characteristic of a prior art snap-back protection structure. As the voltage increases across the ESD protection clamp, a point is reached where the current between the collector and emitter begins to increase due to voltage breakdown of the collector-base junction. When the current reaches a critical level, illustrated by point 202 on curve 201, a snap-back occurs, and the voltage across the protection clamp is reduced to a lower voltage, illustrated by point 204, called the holding voltage. As the ESD current increases the voltages across the clamp also increases, as shown by slope 206. An important requirement of all ESD protection clamps is to keep the maximum voltage across the clamp to a level below which damage can occur to the clamp or the protected circuitry. The present invention provides advantages which allow it to work with smaller geometry ICs. For example, IC 100 may operate at only 2V or so, and may be damaged by ESD when the voltage across the circuit exceeds 6V. Thus, there is only a small acceptable margin between the triggering voltage and the holding voltage. The ESD clamp of the present invention, as will be appreciated, may be configured to operate within these limits, as shown in curve 208. The triggering voltage may also be configured to be equal to the holding voltage, rather than higher than the holding voltage. Thus, a triggering voltage as well as an equal holding voltage of, e.g., 3V may be employed by clamp 150 as illustrated by curve 208 of Fig. 2. Due to close coupling of the ESD transient to the base of npn transistor Q, transistor Q turns on to the high current state, illustrated in curve 208, without having to go through the collector-base breakdown region. The present invention responds very quickly to ESD events, and can operate with lower clamp, triggering, and holding voltages than is possible with conventional ESD protection techniques.

Referring now to Fig. 3, there is shown a diagram illustrating an IC layout of one embodiment of ESD protection circuit 150 of Fig. 1. In this layout, ESD protection circuit

150 comprises n-plus active region 301, N-well region 302, n-plus active region 303, P-well region 305, and salicide blocked region 304. Blocking the salicide on the drain side of MOSFET M, the collector region of lateral npn transistor Q, allows some resistance to be formed in the n-plus active region, ensuring even current distribution during conduction of npn transistor Q.

Layout portion 311 contains the drain of MOSFET M, the collector of parasitic npn transistor Q, and the integrated capacitor C. In particular, n-plus active region 301 forms the collector c of lateral npn transistor Q, and connects to the N-well 302, which forms one electrode of capacitor C. The other electrode of capacitor C is formed from the polysilicon portion (denoted C in Fig. 3), having a contacted extension (terminal 151) coupled by conductive means to the base terminals 355 of npn transistor Q, whose base is formed under the polysilicon portion 353. Thus, capacitor C is formed from two plates: one plate being the polysilicon layer C, and the second plate is the N-well region 302 contacted by n-plus region 301 which is extended into the P-well 305, and forms the drain of MOSFET M, and the collector of npn transistor Q. The dielectric of capacitor C may be formed from the same material as the gate dielectric of MOSFET M, or it may use different material and/or material thickness.

Layout portion 312 contains the gate of MOSFET M and the base contacts 355 for transistor Q, which are coupled by conductive means, as shown, to terminal 151 of capacitor C. The present invention provides for close coupling of base contacts 355 to the actual base region of transistor Q, which is formed under the polysilicon gate region 353, between n-plus region 301 and n-plus region 303. The base coupling contacts 355 are formed through openings in the gate polysilicon region 353 to be close to and in-line with the underlying base region 357. The close coupling ensures minimum time delay to triggering the npn transistor into the conduction mode, minimizing or even eliminating the transient "overshoot" voltage illustrated by point 202 of curve 202 of Fig. 2. Placing the base contact regions 355 further from the actual base region would increase the time required to trigger the npn into conduction and increase the overshoot voltage.

Layout portion 313 contains the source of MOSFET M as well as the emitter e of transistor Q. Pad 101 is connected to the common n-plus region 301, forming the contact to terminal 152 of capacitor C and the collector of parasitic lateral npn transistor Q. Pad 102 is connected to the n-plus region 303, which forms the emitter of npn transistor Q.

Thus, in the layout of ESD protection circuit 150 shown in Fig. 3, a MOSFET M may be laid out and configured such that it also forms a parasitic, lateral npn transistor Q; and a capacitance C is formed from a polysilicon area over an extended drain region, and is coupled to the base region of the parasitic npn transistor Q to provide improved ESD protection for the logic circuitry 120 of Fig. 1, as well as other circuitry coupled between pads 101 and 102.

In the layout embodiment protection circuit 150 illustrated in Fig. 3, the gate of MOSFET M is not coupled to its drain, but is coupled to the source through some conductive means. In one embodiment, the gate terminal of MOSFET M is coupled to the source terminal thereof through a series resistor. In an alternative embodiment, the gate of MOSFET M is coupled to its source terminal through another NMOS device, which would be diode-connected, gate-to-drain. The present invention may also be applied in other technologies than CMOS-based ICs. For example, the present invention may also be employed to protect NMOS-based ICs or pure bipolar-based ICs. It may also be used as a trigger circuit for SCR-based protection circuits, as will be appreciated.

It will be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated above in order to explain the nature of this invention may be made by those skilled in the art without departing from the principle and scope of the invention as recited in the following claims.

Claims

CLAIMSWhat is claimed is:

1. An ESD protection circuit, comprising:

(a) first and second circuit terminals; (b) a lateral bipolar junction transistor having a collector terminal coupled to the first circuit terminal and an emitter terminal coupled to the second circuit terminal; and

(c) a capacitor coupled between the first circuit terminal and base terminals of the bipolar junction transistor, wherein the base terminals are close to and in-line with the base region, wherein the capacitor has a low impedance to ESD events applied to the first circuit terminal so that said ESD events cause the bipolar junction transistor to turn on in forward conductance mode to conduct ESD current from said ESD event without breakdown of the collector-base junction of the transistor.

2. The circuit of claim 1, further comprising a MOSFET transistor, wherein: the bipolar junction transistor is a parasitic bipolar junction transistor formed by the drain, source and gate regions of the MOSFET transistor; the gate of the MOSFET transistor is formed in such as a way as to allow for a contact to the underlying semiconductor material without contacting the

MOSFET transistor gate material; and the contacts to the underlying semiconductor material are close to and in-line with the base region of the bipolar junction transistor.

3. The circuit of claim 2, wherein the MOSFET transistor is an NMOS transistor.

4. The circuit of claim 2, wherein one terminal of the capacitor is formed by an extension of the collector region of the bipolar transistor, and the second terminal is formed from the same material as the gate material of the MOSFET transistor.

5. The circuit of claim 1, wherein the first circuit terminal is one of an input terminal, an output terminal, and a power supply terminal, and the second circuit terminal is coupled to one of ground and a source of reference potential.