WO2000017600A1

WO2000017600A1 - Improved chip slapper detonator

Info

Publication number: WO2000017600A1
Application number: PCT/US1999/021985
Authority: WO
Inventors: Barry T. Neyer; Robert Tomasoski; Robert Tetreault
Original assignee: Eg & G, Inc.
Priority date: 1998-09-22
Filing date: 1999-09-22
Publication date: 2000-03-30
Also published as: AU6397699A

Abstract

An improved chip slapper including a conductive film deposited on the substrate forming a bridge area (14) separating two lands (16'', 18) wherein there is a gap (42, 48) in one land (16'') for preventing current flow through the bridge area (14) to prevent inadvertent detonation of the chip slapper. A trigger lead (42) disposed in the gap (42, 48) and connected to voltage source (50) eliminates the need for an external switch.

Description

IMPROVED CHIP SLAPPER DETONATOR

FIELD OF INVENTION

This invention relates to an improved chip slapper type detonator with an integral switch.

BACKGROUND OF INVENTION Prior art chip slapper detonators include a substrate (for example ceramic) upon which is deposited a conductive metal film such as copper. The copper is etched using etching processes common to the electronics industry to form a narrow bridge area separating two wide conductive lands. A dielectric coating such as polyimide is then applied over the film pattern.

A capacitor is connected to the two conductive lands through a high voltage, typically gas-filled switch. The capacitor is charged to a high voltage (several thousand volts) and when the switch is closed, the capacitor delivers current through the chip slapper. The narrow bridge area then vaporizes and generates a plasma which accelerates the dielectric coating to a very high velocity. This dielectric material then slaps into an explosive and the resulting shock wave detonates the explosive. Chip slappers of this type are used in military, nώiing, automotive, and construction applications.

The high voltage switch used in prior art chip slappers, however, is often the most expensive component of the chip slapper typically costing as much as several hundred dollars. And, these switches can often fail when subjected to shock forces. Therefore, such prior art chip slapper designs cannot be used in all applications. Prior art fuze designs are also susceptible to high electromagnetic radiation environments which can cause inadvertent initiation thereby presenting a severe safety hazard.

Current military standards specify that chip slappers must not detonate or degrade when up to 500 volts is applied. This requirement is often difficult to meet in prior art chip slapper designs.

SUMMARY OF INVENTION

It is therefore an object of this invention to provide an improved chip slapper and method of manufacturing a chip slapper.

It is a further object of this invention to provide such an improved chip slapper and method which ehminates the need for an external switch.

It is a further object of this invention to provide such an improved chip slapper and method which is less expensive to manufacture than prior art chip slappers.

It is a further object of this invention to provide such an improved chip slapper and method which is more reliable than prior art chip slappers.

It is a further object of this invention to provide a safer chip slapper.

It is a further object of this invention to provide a smaller, lighter weight, and more energy efficient chip slapper design.

It is a further object of this invention to provide an improved chip slapper which is not susceptible to shock forces.

It is a further object of this invention to provide such a chip slapper which is not susceptible to electromagnetic radiation. It is a further object of this invention to provide an improved chip slapper which is immune to voltage levels specified by military standards and which does not fire or degrade when subjected to such voltages.

This invention results from the realization that a chip slapper with an integral dielectric switch can be manufactured by forming an over-voltage gap in one of the lands of the chip slapper to prevent inadvertent detonation of the chip slapper since no current will flow through the gap until a voltage of a level sufficient to breakdown the gap in the land is applied thus ekminating the need for an external, expensive gas-filled switch susceptible to shock and radiation failure.

This invention results from the further realization that if a trigger line is disposed in the gap and is subjected to negative high voltage pulse, the result is a less expensive, more robust, and more reliable chip slapper as compared to chip slappers with an external switch.

This invention features an improved chip slapper comprising a conductive film deposited on the substrate forming a bridge area separating two lands; and a gap in one land for preventing current flow through the bridge area to prevent inadvertent detonation of the chip slapper. Further included may be a trigger lead disposed in the gap connected to voltage source for triggering the detonation of the chip slapper.

This invention also features a method of manufacturing an improved chip slapper, the method comprising: depositing a conductive film on a substrate and forming a bridge area separating two land areas; and forming a gap in one land area for preventing current flow through the bridge area to prevent inadvertent detonation of the chip slapper. Further included may be the step of disposing a trigger lead in the gap and connecting the trigger lead to a voltage source for triggering the detonation of the chip slapper.

DISCLOSURE OF PREFERRED EMBODIMENT

Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:

Fig. 1 is a schematic view of a prior art chip slapper;

Fig. 2 is a schematic view of one embodiment of the chip slapper of the subject invention;

Fig. 3 is a schematic view of another embodiment of the chip slapper of this invention; and

Fig. 4 is a flow chart depicting the primary steps associated with manufacturing the chip slapper of this invention.

Prior art chip slapper 10, Fig. 1, includes ceramic substrate 12 upon which is deposited conductive metal film such as copper. The copper layer is etched to form narrow bridge area 14 separating lands 16 and 18. A dielectric coating 19 such as polyimide is then applied over the film pattern.

Capacitor 20 is connected to lands 16 and 18 through high voltage gas filled switch 22. Voltage source 24 charges capacitor 20 to a voltage level of several thousand volts. When switch 22 is closed, capacitor 20 delivers current through bridge area 14

which vaporizes and generates a plasma that accelerates dielectric coating 19 to a very high velocity. This dielectric coating then slaps into an explosive and the resulting shock wave detonates the explosive.

As delineated in the Background of the Invention above, such prior art chip slappers require external switch 22 which can be the most expensive component of the system. Prior art systems are also susceptible to shock forces and radiation and may fire or degrade when subjected to voltage levels specified by military standards.

In the subject invention, however, expensive and unreliable switch 22 is eliminated and the switching function previously provided by switch 22 is integrated with the structure of the chip slapper itself thereby providing a less expensive, a more reliable, safer, lighter weight, more energy efficient, and more robust design less susceptible to shock forces and electromagnetic radiation and also immune to voltage levels specified by military specifications.

Chip slapper 30, Fig. 2 of this invention also includes ceramic substrate 12 and conductive land 18 connected to capacitor 20 energized by voltage source 24. Land 16', however, connected to bridge portion 14 and capacitor 20 is etched to include gap 32 separating land portion 34 from land portion 36. This gap is filled with a dielectric material when the dielectric coating such as polyimide is applied to chip slapper 30. When a voltage level less than the dielectric strength of the dielectric material in gap 32 is applied to the chip slapper, no current will flow across gap 32 because of the break in the electrical circuit. When a voltage level larger than dielectric strength of the dielectric filled gap is applied, however, the voltage will breakdown the gap. The dielectric

strength of the gap can be made to take on any value by adjusting the width of the gap. Thus, chip slapper 30 can be connected directly to capacitor 20 and no external switch is required. By carefully choosing the correct gap geometry (e.g. 1-10 mils in width) and capacitor size (e.g., .02-.5 microfarads), then only when the capacitor voltage is of a sufficient level to break down gap 32 (e.g., 1-3 KV) would there be sufficient energy to cause chip slapper 30 to detonate the explosive. Gap 32 thus prevents current flow to bridge area 14 until the correct voltage level is applied thus preventing inadvertent detonation of the chip slapper. Gap 32 is thus referred to as an "over voltage gap. "

In another embodiment, conductive trigger lead 42, Fig. 3 (e.g. copper) is disposed in the gap and connected to trigger voltage source 50. Thus, there are now two gaps 46 and 48 in conductive land 16" forming land portions 34' and 36'. These two gaps serve the same purpose as gap 32, Fig. 2, namely preventing current flow unless the voltage level across the gap exceeds the dielectric strength of the dielectric material present in gaps 46 and 48. When, however, a negative high voltage pulse (e.g., 1-3 KV) is applied to trigger lead 42, it causes a breakdown on the high voltage side of the chip slapper. The resulting voltage is sufficient to breakdown the ground side of the chip slapper allowing current flow through the device. Thus, the chip slapper of Fig. 3, functions as a normal switched chip slapper detonator but without the need for an external switch. Trigger lead 42 can be formed by conventional etching process in the same manner that lands 16" and 18 and bridge area 14 are formed. Gaps 46 and 48 are typically 1-10 mils wide and trigger lead 48 is typically several (10-20) mils wide.

Thus, the chip slapper designs shown in Figs. 2 and 3 alleviate a major concern in the industry, namely accidental initiation or damage of the chip slapper. In the chip slapper designs shown in Figs. 2 and 3 no current would flow unless the voltage across lands 16' and 18 is greater than the dielectric strength of the material filing the gap or gaps. Thus, the chip slapper designs shown in Figs. 2 and 3 are immune to voltage levels of 500 volts or less and subjecting such a chip slapper to 500 volts DC will not fire or degrade the subject chip slappers because no current would flow.

Accordingly, the chip slapper designs shown in Figs. 2 and 3 as compared to the prior art chip slapper design shown in Fig. 1 are safer, more reliable, less expensive, smaller, lighter weight, more energy efficient, not susceptible to shock forces or electromagnetic radiation, and will not fire or degrade when subjected to specified voltage levels.

In accordance with the method of this invention, a conductive film, for example copper, is deposited on a ceramic substrate, step 60, Fig. 4. The copper layer is then etched to form the two opposing land areas (for example land areas 16' and 18, Fig. 2) and bridge area 14, Fig. 2, step 62, Fig. 4.

To make the chip slapper shown in Fig. 2, the copper layer is removed (etched) from gap area 32, step 64, Fig 4. To make the chip slapper shown in Fig. 3, the copper layer is removed from gap areas 46 and 48, step 66, Fig. 4. A dielectric coating is then applied, step 68. In practice, steps 62 and 64 occur simultaneously to make the chip slapper shown in Fig. 2 and steps 62 and 66 occur simultaneously to make the chip slapper shown in Fig. 3.

Although specific features of this invention are shown in some drawings and not others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. _

Other embodiments will occur to those skilled in the art and are within the following claims:

What is claimed is:

Claims

1. An improved chip slapper comprising:

a conductive film deposited on the substrate forming a bridge area separating two lands; and a gap in one land for preventing cuπent flow through the bridge area to prevent inadvertent detonation of the chip slapper.

2. The improved chip slapper of claim 1 further including a trigger lead disposed in said gap, the lead connected to voltage source for triggering the detonation of the chip slapper.

3. An improved chip slapper comprising: a substrate; a conductive film deposited on the substrate forming a bridge area separating two lands; a gap in one land for preventing cuπent flow through the bridge area; and a trigger lead disposed in said gap connected to a voltage source for triggering the detonation of the chip slapper.

4. A method of manufacturing an improved chip slapper, the method comprising: depositing a conductive film on a substrate and forming a bridge area separating two land areas; and forming a gap in one said land area for preventing cuπent flow through the bridge area to prevent inadvertent detonation of the chip slapper.

5. The method of claim 4 further including disposing a trigger lead in the gap and connecting the trigger lead to a voltage source for triggering the detonation of the chip slapper.

6. A method of manufacturing an improved chip slapper, the method comprising: depositing a conductive film on a substrate and forming a bridge area separating two land areas; forming a gap in one said land area for preventing cuπent flow through the bridge area; and disposing a trigger lead in the gap and connecting the trigger lead to a voltage source for triggering the detonation of the chip slapper.