WO2000016392A1 - Method of manufacturing a semiconductor device with a bipolar transistor - Google Patents
Method of manufacturing a semiconductor device with a bipolar transistor Download PDFInfo
- Publication number
- WO2000016392A1 WO2000016392A1 PCT/EP1999/006416 EP9906416W WO0016392A1 WO 2000016392 A1 WO2000016392 A1 WO 2000016392A1 EP 9906416 W EP9906416 W EP 9906416W WO 0016392 A1 WO0016392 A1 WO 0016392A1
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- WIPO (PCT)
- Prior art keywords
- mask
- electrically insulating
- layer
- insulating region
- base
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000005498 polishing Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000002002 slurry Substances 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000012777 electrically insulating material Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000007521 mechanical polishing technique Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
- H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
Definitions
- the invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body with a bipolar transistor including a base, an emitter and a collector, said base being formed by providing the semiconductor body with a doped semiconducting layer which locally borders on a monocrystalline part of the semiconductor body where it forms a first semiconductor region which is monocrystalline and constitutes the base of the transistor, and which semiconductive layer borders, outside said base, on a non- monocrystalline part of the semiconductor body where it forms a second semiconductor region which is not monocrystalline and which constitutes a connection region of the base, the non- monocrystalline part of the semiconductor body being obtained by covering the semiconductor body with a mask and replacing, on either side thereof, a part of the semiconductor body by an electrically insulating region, and by providing the electrically insulating region with a polycrystalline semiconducting layer before the provision of the semiconducting layer.
- Such a method is known from European patent application, filed by the current applicant (PHN 17.066) under application no. 98202894.6 on 31-08-1998.
- a description is given of a method for the manufacture of a so-called differential bipolar transistor.
- Such a transistor is obtained by providing a semiconducting layer on a crystalline and a non-crystalline part of the semiconductor body, which forms at said locations, respectively, a crystalline semiconductor region, the base of the transistor, and a non- crystalline semiconductor region, a connecting region of the base.
- the crystalline part of the semiconductor body forms the collector, and in the semiconducting layer the emitter is formed at the location of the base.
- the non-monocrystalline part of the semiconductor body is formed by an electrically insulating region which surrounds the collector and on which a polycrystalline semiconducting layer is situated which serves as the host layer during the provision of the semiconducting layer.
- LOCOS Local Oxidation Of Silicon
- a method in accordance with the invention is characte ⁇ zedin that the polycrystalline layer is selectively provided on the elect ⁇ cally insulating region, use being made of the mask to form the elect ⁇ cally insulating region
- the method in accordance with the invention is much simpler than the known method. Additional photolithographic and etch steps are not necessary to (re-)expose the collector.
- the use of the mask employed for forming the elect ⁇ cally insulating region has an important additional advantage which is connected with the following surp ⁇ sing realization: by applying chemico-mechanical polishing du ⁇ ng the selective application of the polycrystalline layer, said polycrystalline layer can be provided in the same manner as the elect ⁇ cally insulating region, thereby making its manufacture easy.
- a method in accordance with the invention has the important advantage that the aperture which the polycrystalline semiconducting layer should have above the collector is formed in a self- recording manner relative to said collector. As a result, the dimensions of the transistor to be formed can be much better controlled, thus enabling, in particular, said dimensions to be very small and hence the transistor very fast.
- the polycrystalline semiconducting layer is provided onto the mask and the elect ⁇ cally insulating region, and the resulting structure is leveled off by means of chemico-mechanical polishing, the mask remaining bu ⁇ ed in the polycrystalline semiconducting layer, and subsequently the polycrystalline semiconducting layer is removed to such an extent that the mask is re-exposed.
- a method in accordance with the invention is made simple by applying this technique.
- the mask is, for example, a nit ⁇ de mask which, as m the known method, can be used to form so-called LOCOS oxide which forms the elect ⁇ cally insulating region on either side of the collector. Re-exposing the mask can take place simultaneously with leveling off the structure by means of CMP.
- the electrically insulating region is formed by making grooves in the semiconductor body on either side of the mask, providing an electrically insulating layer in the grooves and on the mask, whereafter an electrically insulating layer is provided in the grooves and on the mask, and the resultant structure is leveled off by means of chemico-mechanical polishing, the mask remaining buried in the electrically insulating layer, whereafter the electrically insulating layer is removed to such an extent that the mask is re-exposed, whereafter a part of the resultant electrically insulating region is removed, the mask remaining intact.
- an amsotropic etching technique such as plasma etching
- Such a method, in which chemico-mechanical polishing can also be used to form the electrically insulating region, keeps the method simple because both the electrically insulating region and the polycrystalline layer are formed in the same manner.
- the formation of the electrically insulating region in this manner results in a very flat structure, thereby substantially simplifying the subsequent selective provision in a similar manner of the polycrystalline semiconducting layer, since an electrically insulating region formed by so-called LOCOS oxide, results in a structure which is not very flat, thereby hampering the chemico-mechanical process to be carried out after the provision of the polycrystalline layer.
- This profile can be obtained by forming a recess in the structure using a wet-chemical etchant which is selective with respect to electrically insulating material.
- the mask can be exposed by means of the CMP step, but also by a separate (anisotropic) etch step after the structure has been leveled off by means of CMP, the mask still being buried in the insulating layer. If the anisotropic etch step is carried out using an etchant which etches the electrically insulating material in a selective manner with respect to the mask, then the additional advantage is obtained that no separate etch step is necessary to provide the structure, after exposure of the mask, with the profile necessary to apply the polycrystalline layer.
- the method of this variant can very suitably be used to manufacture transistors having very small dimensions.
- the mask used in this operation is preferably removed. This can be achieved in a simple manner by immersing the mask in an etchant which is selective with respect to the mask. As a result, the collector is re-exposed, and the semiconducting layer can be provided. Subsequently, the emitter can be formed so as to border on the base.
- silicon dioxide is used as the material for the electrically insulating region
- silicon nitride is used as the material for the mask.
- These materials can be readily selectively removed relative to each other and relative to silicon. These materials can also very suitably be used in combination with the chemico-mechanical polishing technique.
- Figs. 1 through 10 are diagrammatic, cross-sectional views, at right angles to the thickness direction, of a semiconductor device with a bipolar transistor, at successive stages in the manufacture using a method in accordance with the invention.
- the Figures are diagrammatic and not drawn to scale, in particular the dimensions in the thickness direction being exaggerated for clarity. Semiconductor regions of the same conductivity type are generally hatched in the same direction. Like reference numerals refer to like regions whenever possible.
- Figs. 1 through 10 are diagrammatic, cross-sectional views, at right angles to the thickness direction, of a semiconductor device with a bipolar transistor, at successive stages in the manufacture using a method in accordance with the invention. Fig.
- the semiconductor body 10 is a diagrammatic, cross-sectional view, at right angles to the thickness direction, of the finished device comprising a bipolar transistor.
- the semiconductor body 10 comprises (not shown in the drawing) a monocrystalline substrate of p + -type silicon covered with a 1 ⁇ m thick monocrystalline epitaxial layer 3 of n-type silicon with a doping concentration of 1 x 10 16 at/cm 3 which forms a collector 3 of the transistor.
- the epitaxial layer 3 accommodates a 0.3 ⁇ m recessed insulation region 8 which, in this case, includes silicon dioxide and surrounds the collector 3.
- a polycrystalline, p-type silicon layer 4 having a thickness of 50 nm and a doping concentration of, in this example, 1 x 10 20 at/cm 3 .
- an, in this case 150 nm thick, p- type semiconducting layer 1 which, in this case contains SiGe with 20 at.% germanium.
- the part 1A of the semiconducting layer 1 bordering on the collector 3 is monocrystalline and forms a base 1A of the transistor.
- the remaining part IB of the semiconducting layer 1 is polycrystalline, borders on the polycrystalline layer 4 and forms a connecting region IB of the base 1A of the transistor At the location of the base 1A, the doping concentration is 1 x 10 19 at/cm , at the location of the connecting region IB, the doping concentration is higher and amounts to 1 x 10 20 at/cm 3 .
- the semiconducting layer 1 there is a 0.3 ⁇ m thick insulating layer of silicon dioxide having a recessed portion above the base 1A, which is filled with an emitter connection 7 of n-type polycrystalline silicon whose doping concentration is approximately 10 21 at/cm 3
- an emitter 2 of the transistor which is recessed m the base 1 A which is of the n-conductivity type, has a thickness of 40 nm and a doping concentration of approximately 10 20 at/cm 3
- the device further includes (not shown in the Figure) elect ⁇ cal connections of the connecting region 11 of the emitter 2, of the connecting region IB of the base 1 A and of a connecting region (not shown either in the drawing) of the collector 3.
- the width of the part of the semiconductor body shown in the drawing is several micrometers, the collector 3 and the base 1A have a width of approximately 1 ⁇ m, and the width of the emitter 2 and the emitter connection 7 is approximately 0 5 ⁇ m.
- a p-type silicon substrate (not shown m the drawing) is first provided with an epitaxial n-type silicon layer 3 (see Fig. 1).
- This n-type silicon layer is provided with a mask 20, which in this case is formed from a 200 nm thick silicon nit ⁇ de layer 20 by means of photolithography and etching.
- plasma etching see Fig. 2
- 0.3 ⁇ m deep grooves 21 are formed in the semiconductor body 10 on either side of the mask 20.
- LPCVD Low Pressure Chemical Vapor Deposition
- the oxide layer 8 is subjected to a chemico-mechanical polishing so as to ensure that the resultant structure is flat and the surface of the (remaining part) of the mask 20 is re-exposed.
- a slurry of silicon dioxide particles and potassium hydroxide.
- a suitable slurry is, for example, ssl2 by Cabbot.
- the elect ⁇ cally insulating region 8 is subsequently selectively provided with a polycrystalline semiconducting layer 4, in which process use is made of the mask 20 which was used to form the elect ⁇ cally insulating region 8.
- the method in accordance with the invention is much simpler than the known method. First of all, additional photolithography and etching, as m the known method, are not necessary to remove (again) the polycrystalline layer 1 above the collector 3.
- a chemico-mechanical polishing technique becomes very suitable to obtain the desired result.
- Another important advantage of a method in accordance with the invention is that the aperture in the polycrystalline semiconducting layer 4 above the collector 3 is formed in a self- recording manner relative to said collector 3. As a result, the dimensions of the transistor to be formed can be controlled much better, thus enabling very small and very fast transistors to be achieved.
- the surface of the semiconductor body 10 is first provided with a several tens of micrometers thick polycrystalline semiconducting layer 4, in this case by means of LPCVD from a gas mixture containing silane and hydrogen.
- the polycrystalline layer 4 is removed by means of chemico- mechanical polishing to such an extent the resultant structure is flat.
- the mask 20 is still buried in the polycrystalline layer 4.
- use is made of the same slurry as in the above-described chemico-mechanical polishing step. It is alternatively possible, however, to use a different slurry which is more specially developed for etching polycrystalline silicon.
- an anisotropic etch technique such as plasma etching, is used to etch back the polycrystalline layer 4 until the mask 20 is exposed.
- the insulating region 8 is provided, in a selective and self-recording manner, with the polycrystalline semiconducting layer 4.
- the mask 20 is removed by means of etching, in this case by means of warm phosphoric acid, without the polycrystalline layer 4 and the collector 5 being attacked.
- the resultant structure is used to continue the manufacture of the transistor.
- the geometry and dimensions of the various regions of the transistor may be chosen so as to be different.
- a device in accordance with the invention can also be a more complex device than a single bipolar transistor.
- the device may comprise a number of different active or passive components.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Bipolar Transistors (AREA)
Abstract
The invention relates to the manufacture of a so-called differential bipolar transistor comprising a base (1A), an emitter (2) and a collector (3), the base (1A) being formed by applying a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body (10) where it forms the (monocrystalline) base (1A), and which semiconducting layer (1) borders, outside said monocrystalline part, on a non-monocrystalline part (4, 8) of the semiconductor body (10) where it forms a (non-monocrystalline) connecting region (1B) of the base (1A). In a method in accordance with the invention, the polycrystalline layer (4) is selectively provided on the electrically insulating region (8), in which process use is made of the mask (20) to form the electrically insulating region (8). This method is less laborious than the known method. In addition, the resultant transistors have excellent properties and their dimensions may be very small. Preferably, both in the manufacture of the insulating region (8), preferably an oxide-filled groove (8), and in the process of selectively applying the polycrystalline layer (4) to the insulating region, use is made of a deposition step followed by a chemico-mechanical polishing step.
Description
Method of manufacturing a semiconductor device with a bipolar transistor.
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body with a bipolar transistor including a base, an emitter and a collector, said base being formed by providing the semiconductor body with a doped semiconducting layer which locally borders on a monocrystalline part of the semiconductor body where it forms a first semiconductor region which is monocrystalline and constitutes the base of the transistor, and which semiconductive layer borders, outside said base, on a non- monocrystalline part of the semiconductor body where it forms a second semiconductor region which is not monocrystalline and which constitutes a connection region of the base, the non- monocrystalline part of the semiconductor body being obtained by covering the semiconductor body with a mask and replacing, on either side thereof, a part of the semiconductor body by an electrically insulating region, and by providing the electrically insulating region with a polycrystalline semiconducting layer before the provision of the semiconducting layer.
Such a method is known from European patent application, filed by the current applicant (PHN 17.066) under application no. 98202894.6 on 31-08-1998. In said document, a description is given of a method for the manufacture of a so-called differential bipolar transistor. Such a transistor is obtained by providing a semiconducting layer on a crystalline and a non-crystalline part of the semiconductor body, which forms at said locations, respectively, a crystalline semiconductor region, the base of the transistor, and a non- crystalline semiconductor region, a connecting region of the base. The crystalline part of the semiconductor body forms the collector, and in the semiconducting layer the emitter is formed at the location of the base. The non-monocrystalline part of the semiconductor body is formed by an electrically insulating region which surrounds the collector and on which a polycrystalline semiconducting layer is situated which serves as the host layer during the provision of the semiconducting layer. The electrically insulating region is formed by a LOCOS (= Local Oxidation Of Silicon) oxide on which a polycrystalline layer is provided in which an aperture is formed at the location of the collector by means of photolithography and etching.
A drawback of the known method is that it is relatively laboπous, partly because a photolithographic step followed by an etch step is necessary to form an aperture in the polycrystalline layer above the collector
It is an object of the invention to provide a method which is less intπcate and nevertheless yields transistors of at least the same quality
To achieve this, a method in accordance with the invention is characteπzedin that the polycrystalline layer is selectively provided on the electπcally insulating region, use being made of the mask to form the electπcally insulating region As a result, the method in accordance with the invention is much simpler than the known method. Additional photolithographic and etch steps are not necessary to (re-)expose the collector. In the selective deposition process, the use of the mask employed for forming the electπcally insulating region has an important additional advantage which is connected with the following surpπsing realization: by applying chemico-mechanical polishing duπng the selective application of the polycrystalline layer, said polycrystalline layer can be provided in the same manner as the electπcally insulating region, thereby making its manufacture easy. Finally, a method in accordance with the invention has the important advantage that the aperture which the polycrystalline semiconducting layer should have above the collector is formed in a self- recording manner relative to said collector. As a result, the dimensions of the transistor to be formed can be much better controlled, thus enabling, in particular, said dimensions to be very small and hence the transistor very fast.
In a preferred embodiment of a method in accordance with the invention, the polycrystalline semiconducting layer is provided onto the mask and the electπcally insulating region, and the resulting structure is leveled off by means of chemico-mechanical polishing, the mask remaining buπed in the polycrystalline semiconducting layer, and subsequently the polycrystalline semiconducting layer is removed to such an extent that the mask is re-exposed. Chemico-mechanical polishing (= CMP) enables a method in accordance with the invention to be earned out in a controlled manner and with excellent results. In addition, a method in accordance with the invention is made simple by applying this technique. The mask is, for example, a nitπde mask which, as m the known method, can be used to form so-called LOCOS oxide which forms the electπcally insulating region on either side of the collector. Re-exposing the mask can take place simultaneously with leveling off the structure by means of CMP. It can also be achieved by means of etching after the CMP treatment using an amsotropic etching technique, such as plasma etching
In a very important embodiment of a method in accordance with the invention, the electrically insulating region is formed by making grooves in the semiconductor body on either side of the mask, providing an electrically insulating layer in the grooves and on the mask, whereafter an electrically insulating layer is provided in the grooves and on the mask, and the resultant structure is leveled off by means of chemico-mechanical polishing, the mask remaining buried in the electrically insulating layer, whereafter the electrically insulating layer is removed to such an extent that the mask is re-exposed, whereafter a part of the resultant electrically insulating region is removed, the mask remaining intact. Such a method, in which chemico-mechanical polishing can also be used to form the electrically insulating region, keeps the method simple because both the electrically insulating region and the polycrystalline layer are formed in the same manner. In addition, the formation of the electrically insulating region in this manner results in a very flat structure, thereby substantially simplifying the subsequent selective provision in a similar manner of the polycrystalline semiconducting layer, since an electrically insulating region formed by so-called LOCOS oxide, results in a structure which is not very flat, thereby hampering the chemico-mechanical process to be carried out after the provision of the polycrystalline layer. By selectively removing a small part of the electrically insulating region formed with respect to the mask, the profile in the surface necessary for the preferred embodiment is achieved. This profile can be obtained by forming a recess in the structure using a wet-chemical etchant which is selective with respect to electrically insulating material. Also in this variant, the mask can be exposed by means of the CMP step, but also by a separate (anisotropic) etch step after the structure has been leveled off by means of CMP, the mask still being buried in the insulating layer. If the anisotropic etch step is carried out using an etchant which etches the electrically insulating material in a selective manner with respect to the mask, then the additional advantage is obtained that no separate etch step is necessary to provide the structure, after exposure of the mask, with the profile necessary to apply the polycrystalline layer. Also in this case, a suitable technique for anisotropic (selective) etching is the plasma-etched technique. Finally, partly because of the absence of 1OCOS oxide, the method of this variant can very suitably be used to manufacture transistors having very small dimensions. After the formation of the electrically insulating region and the formation of the polycrystalline semiconducting layer thereon, the mask used in this operation is preferably removed. This can be achieved in a simple manner by immersing the mask in an etchant which is selective with respect to the mask. As a result, the collector is re-exposed, and the
semiconducting layer can be provided. Subsequently, the emitter can be formed so as to border on the base.
Preferably, silicon dioxide is used as the material for the electrically insulating region, and silicon nitride is used as the material for the mask. These materials can be readily selectively removed relative to each other and relative to silicon. These materials can also very suitably be used in combination with the chemico-mechanical polishing technique. __
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
In the drawings:
Figs. 1 through 10 are diagrammatic, cross-sectional views, at right angles to the thickness direction, of a semiconductor device with a bipolar transistor, at successive stages in the manufacture using a method in accordance with the invention. The Figures are diagrammatic and not drawn to scale, in particular the dimensions in the thickness direction being exaggerated for clarity. Semiconductor regions of the same conductivity type are generally hatched in the same direction. Like reference numerals refer to like regions whenever possible. Figs. 1 through 10 are diagrammatic, cross-sectional views, at right angles to the thickness direction, of a semiconductor device with a bipolar transistor, at successive stages in the manufacture using a method in accordance with the invention. Fig. 10 is a diagrammatic, cross-sectional view, at right angles to the thickness direction, of the finished device comprising a bipolar transistor. The semiconductor body 10 comprises (not shown in the drawing) a monocrystalline substrate of p+-type silicon covered with a 1 μm thick monocrystalline epitaxial layer 3 of n-type silicon with a doping concentration of 1 x 1016 at/cm3 which forms a collector 3 of the transistor. The epitaxial layer 3 accommodates a 0.3 μm recessed insulation region 8 which, in this case, includes silicon dioxide and surrounds the collector 3. On the epitaxial layer there is provided a polycrystalline, p-type silicon layer 4 having a thickness of 50 nm and a doping concentration of, in this example, 1 x 1020 at/cm3. On said silicon layer and on the collector 3, there is provided an, in this case 150 nm thick, p- type semiconducting layer 1 which, in this case contains SiGe with 20 at.% germanium. The part 1A of the semiconducting layer 1 bordering on the collector 3 is monocrystalline and forms a base 1A of the transistor. The remaining part IB of the semiconducting layer 1 is polycrystalline, borders on the polycrystalline layer 4 and forms a connecting region IB of the
base 1A of the transistor At the location of the base 1A, the doping concentration is 1 x 1019 at/cm , at the location of the connecting region IB, the doping concentration is higher and amounts to 1 x 1020 at/cm3. Above the semiconducting layer 1, there is a 0.3 μm thick insulating layer of silicon dioxide having a recessed portion above the base 1A, which is filled with an emitter connection 7 of n-type polycrystalline silicon whose doping concentration is approximately 1021 at/cm3 Below this, there is an emitter 2 of the transistor which is recessed m the base 1 A which is of the n-conductivity type, has a thickness of 40 nm and a doping concentration of approximately 1020 at/cm3. The device further includes (not shown in the Figure) electπcal connections of the connecting region 11 of the emitter 2, of the connecting region IB of the base 1 A and of a connecting region (not shown either in the drawing) of the collector 3. The width of the part of the semiconductor body shown in the drawing is several micrometers, the collector 3 and the base 1A have a width of approximately 1 μm, and the width of the emitter 2 and the emitter connection 7 is approximately 0 5 μm.
The device of this example is manufactured as will be descπbed hereinbelow using a method in accordance with the invention. A p-type silicon substrate (not shown m the drawing) is first provided with an epitaxial n-type silicon layer 3 (see Fig. 1). This n-type silicon layer is provided with a mask 20, which in this case is formed from a 200 nm thick silicon nitπde layer 20 by means of photolithography and etching. By means of plasma etching (see Fig. 2), 0.3 μm deep grooves 21 are formed in the semiconductor body 10 on either side of the mask 20. Subsequently, (see Fig. 3) a 1 μm thick layer 8 of silicon dioxide is provided on the surface of the semiconductor body 10 by means of LPCVD (= Low Pressure Chemical Vapor Deposition). Next, (see Fig. 4) the oxide layer 8 is subjected to a chemico-mechanical polishing so as to ensure that the resultant structure is flat and the surface of the (remaining part) of the mask 20 is re-exposed. In this process, use is made of a "slurry" of silicon dioxide particles and potassium hydroxide. A suitable slurry is, for example, ssl2 by Cabbot.
Subsequently, (see Fig. 5) a part of the insulation oxide 8 is removed again by means of an etchant compπsing hydrogen fluoπde, in which process the mask 20 is not attached and projects 0.1 μm above the surface of the semiconductor body 10 after the etch process. In accordance with the invention, the electπcally insulating region 8 is subsequently selectively provided with a polycrystalline semiconducting layer 4, in which process use is made of the mask 20 which was used to form the electπcally insulating region 8. As a result, the method in accordance with the invention is much simpler than the known method. First of all, additional photolithography and etching, as m the known method, are not necessary to remove (again) the polycrystalline layer 1 above the collector 3. By virtue of the
use of the mask 20 to selectively provide the insulating region 8 with the polycrystalline layer 4, a chemico-mechanical polishing technique becomes very suitable to obtain the desired result. Another important advantage of a method in accordance with the invention is that the aperture in the polycrystalline semiconducting layer 4 above the collector 3 is formed in a self- recording manner relative to said collector 3. As a result, the dimensions of the transistor to be formed can be controlled much better, thus enabling very small and very fast transistors to be achieved.
In this example, (see Fig. 6) the surface of the semiconductor body 10 is first provided with a several tens of micrometers thick polycrystalline semiconducting layer 4, in this case by means of LPCVD from a gas mixture containing silane and hydrogen.
Subsequently, (see Fig. 7) the polycrystalline layer 4 is removed by means of chemico- mechanical polishing to such an extent the resultant structure is flat. At this stage, the mask 20 is still buried in the polycrystalline layer 4. In this process, use is made of the same slurry as in the above-described chemico-mechanical polishing step. It is alternatively possible, however, to use a different slurry which is more specially developed for etching polycrystalline silicon. Next, (see Fig. 8) an anisotropic etch technique, such as plasma etching, is used to etch back the polycrystalline layer 4 until the mask 20 is exposed. In this manner, the insulating region 8 is provided, in a selective and self-recording manner, with the polycrystalline semiconducting layer 4. Subsequently, (see Fig. 9) the mask 20 is removed by means of etching, in this case by means of warm phosphoric acid, without the polycrystalline layer 4 and the collector 5 being attacked. The resultant structure is used to continue the manufacture of the transistor. The further content of the method used in this example can be summarized as follows (see Fig. 10): the application of the semiconducting layer 1, the provision above the base 1A of a further mask of silicon nitride, depositing an insulating layer 6 on said mask, followed by planarization of the structure by means of chemico-mechanical polishing, the removal of the further mask and providing polycrystalline silicon 7 in the resultant aperture, thus forming the emitter 2, which itself forms a connecting region for the emitter 2. Furthermore, the base 1 A and the collector 3 are provided (via their connecting region) with connecting conductors. For further particularities regarding this part of the manufacture of the transistor, reference is made to the above-mentioned European patent application (PHN 16.077).
The invention is not limited to the above examples, and within the scope of the invention many modifications and variations are possible to those skilled in the art. For example, other compositions and thicknesses for the different (semiconductor) regions or
layers can be selected. It is also possible to use other deposition techniques, such as MBE (= Molecular Beam Epitaxy) and CVD (= Chemical Vapor Deposition). It is also possible to modify the manufacture in various ways.
Also the geometry and dimensions of the various regions of the transistor may be chosen so as to be different.
A device in accordance with the invention can also be a more complex device than a single bipolar transistor. The device may comprise a number of different active or passive components. The transistor may also form part of a BI(C)MOS (= Bipolar (Complementary) Metal Oxide Semiconductor) IC.
Claims
1. A method of manufacturing a semiconductor device comprising a semiconductor body with a bipolar transistor including a base, an emitter and a collector, said base being formed by providing the semiconductor body with a doped semiconducting layer which locally borders on a monocrystalline part of the semiconductor body where it forms a first semiconductor region which is monocrystalline and constitutes the base of the transistor, and which semiconductive layer borders, outside said base, on a non-monocrystalline part of the semiconductor body where it forms a second semiconductor region which is not monocrystalline and which constitutes a connection region of the base, the non- monocrystalline part of the semiconductor body being obtained by covering the semiconductor body with a mask and replacing, on either side thereof, a part of the semiconductor body by an electrically insulating region, and by providing the electrically insulating region with a polycrystalline semiconducting layer before the provision of the semiconducting layer, characterized in that the polycrystalline layer (4) is selectively provided on the electrically insulating region (8), use being made of the mask (20) to form the electrically insulating region (8).
2. A method as claimed in claim 1, characterized in that the polycrystalline semiconducting layer (4) is provided onto the mask (20) and the electrically insulating region (8), and the resulting structure is leveled off by means of chemico-mechanical polishing, the mask (20) remaining buried in the polycrystalline semiconducting layer (4), and subsequently the polycrystalline semiconducting layer (4) is removed to such an extent that the mask (20) is re-exposed.
3. A method as claimed in claim 2, characterized in that the mask (20) is re- exposed by means of etching the polycrystalline semiconducting layer.
4. A method as claimed in claim 1, 2 or 3, characterized in that the electrically insulating region (8) is formed by making grooves (21) in the semiconductor body (10) on either side of the mask (20), providing an electrically insulating layer (8) in the grooves (21) and on the mask (20), whereafter an electrically insulating layer (8) is provided in the grooves (21) and on the mask (20), and the resultant structure is leveled off by means of chemico- mechanical polishing, the mask (20) remaining buried in the electrically insulating layer (8), whereafter the electrically insulating layer (8) is removed to such an extent that the mask (20) is re-exposed, whereafter a part of the resultant electrically insulating region (8) is removed, the mask (20) remaining intact.
5. A method as claimed in claim 4, characterized in that the mask (20) is exposed by means of chemico-mechanical polishing, and the removal of a part of the electrically insulating region (8) formed takes place by means of etching, in which process the mask (20) remains intact. _
6. A method as claimed in claim 4, characterized in that both exposing the mask (20) and removing a part of the electrically insulating region (8) formed, the mask (20) remaining intact, takes place by means of etching.
7. A method as claimed in any one of the preceding claims, characterized in that after the formation of the electrically insulating region (8) and after the provision of the polycrystalline semiconducting layer (4), the mask (20) is removed, whereafter the emitter (2) is formed in the surface of the semiconducting layer (1) at the location of the base (1A).
8. A method as claimed in any one of the preceding claims, characterized in that silicon dioxide is used as the material for the electrically insulating region (8) and silicon nitride is used as the material for the mask (20).
9. A semiconductor device comprising a bipolar transistor is obtained using a method as claimed in any one of the preceding claims.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99969180A EP1048066B1 (en) | 1998-09-11 | 1999-08-31 | Method of manufacturing a semiconductor device with a bipolar transistor |
JP2000570829A JP2002525851A (en) | 1998-09-11 | 1999-08-31 | Method of manufacturing a semiconductor device having a bipolar transistor |
DE69935967T DE69935967T2 (en) | 1998-09-11 | 1999-08-31 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH A BIPOLAR TRANSISTOR |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98203054.6 | 1998-09-11 | ||
EP98203054 | 1998-09-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000016392A1 true WO2000016392A1 (en) | 2000-03-23 |
Family
ID=8234106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP1999/006416 WO2000016392A1 (en) | 1998-09-11 | 1999-08-31 | Method of manufacturing a semiconductor device with a bipolar transistor |
Country Status (5)
Country | Link |
---|---|
US (1) | US6150224A (en) |
EP (1) | EP1048066B1 (en) |
JP (1) | JP2002525851A (en) |
DE (1) | DE69935967T2 (en) |
WO (1) | WO2000016392A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1082758A2 (en) * | 1998-11-13 | 2001-03-14 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device comprising a bipolar transistor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0378794A1 (en) * | 1989-01-18 | 1990-07-25 | International Business Machines Corporation | Vertical bipolar transistor structure and method of manufacturing |
US5117271A (en) * | 1990-12-07 | 1992-05-26 | International Business Machines Corporation | Low capacitance bipolar junction transistor and fabrication process therfor |
US5656514A (en) * | 1992-07-13 | 1997-08-12 | International Business Machines Corporation | Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile |
EP0795899A1 (en) * | 1996-03-14 | 1997-09-17 | Daimler-Benz Aktiengesellschaft | Method for fabricating a heterojunction bipolar transistor |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5106767A (en) * | 1990-12-07 | 1992-04-21 | International Business Machines Corporation | Process for fabricating low capacitance bipolar junction transistor |
-
1999
- 1999-08-31 EP EP99969180A patent/EP1048066B1/en not_active Expired - Lifetime
- 1999-08-31 JP JP2000570829A patent/JP2002525851A/en active Pending
- 1999-08-31 DE DE69935967T patent/DE69935967T2/en not_active Expired - Lifetime
- 1999-08-31 WO PCT/EP1999/006416 patent/WO2000016392A1/en active IP Right Grant
- 1999-09-10 US US09/393,944 patent/US6150224A/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0378794A1 (en) * | 1989-01-18 | 1990-07-25 | International Business Machines Corporation | Vertical bipolar transistor structure and method of manufacturing |
US5117271A (en) * | 1990-12-07 | 1992-05-26 | International Business Machines Corporation | Low capacitance bipolar junction transistor and fabrication process therfor |
US5656514A (en) * | 1992-07-13 | 1997-08-12 | International Business Machines Corporation | Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile |
EP0795899A1 (en) * | 1996-03-14 | 1997-09-17 | Daimler-Benz Aktiengesellschaft | Method for fabricating a heterojunction bipolar transistor |
Also Published As
Publication number | Publication date |
---|---|
JP2002525851A (en) | 2002-08-13 |
US6150224A (en) | 2000-11-21 |
DE69935967D1 (en) | 2007-06-14 |
EP1048066A1 (en) | 2000-11-02 |
EP1048066B1 (en) | 2007-05-02 |
DE69935967T2 (en) | 2008-01-10 |
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