WO2000014892A1 - Correlateur analogique a temps continu et spectre etale, et procede le concernant - Google Patents

Correlateur analogique a temps continu et spectre etale, et procede le concernant Download PDF

Info

Publication number
WO2000014892A1
WO2000014892A1 PCT/US1999/020525 US9920525W WO0014892A1 WO 2000014892 A1 WO2000014892 A1 WO 2000014892A1 US 9920525 W US9920525 W US 9920525W WO 0014892 A1 WO0014892 A1 WO 0014892A1
Authority
WO
WIPO (PCT)
Prior art keywords
correlator
input signal
output
multiplier
signal
Prior art date
Application number
PCT/US1999/020525
Other languages
English (en)
Other versions
WO2000014892B1 (fr
Inventor
Gregory T. Uehara
Original Assignee
University Of Hawaii
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University Of Hawaii filed Critical University Of Hawaii
Priority to AU63847/99A priority Critical patent/AU6384799A/en
Publication of WO2000014892A1 publication Critical patent/WO2000014892A1/fr
Publication of WO2000014892B1 publication Critical patent/WO2000014892B1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/709—Correlator structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers

Definitions

  • This invention pertains generally to structures and methods for correlating signals, and more particularly to a structure and method for performing continuous-time analog correlation of signals in direct sequence spread-spectrum communication systems.
  • DS-CDMA direct sequence code-division multiple access
  • CCD Charge Coupled Devices
  • K. Onodera and P. Gray See reference [5]
  • SC Switched-Capacitor
  • conventional SC sampling arrays require large areas on the chip die which translates to higher manufacturing cost.
  • Analog-to-digital (A/D) converters are used to convert an analog input signal to the digital domain where correlation and all other processing is performed. These techniques are effective for low bit rate systems. But as data rates increase, the sampling rate of the A/D converter increases much faster. Thus, digital implementations for future higher rate systems will required an increased power consumption which is undesirable for battery operated portable systems.
  • the performance of the digital correlators is usually compromised by the use of a smaller number of bits in the A/D conversion and processing which affects the size and power of the circuit implementation.
  • A/D converters use smaller number of bits prior to the correlation of the signal that reduces the robustness to continuous-wave interferers.
  • This invention provides a novel integrated circuit structure, method of correlating, and method for the design of a correlator including embodiments for a correlator for DS- CDMA spread-spectrum systems in the analog domain.
  • the inventive structure and method provide both for significantly lower power consumption than known conventional digital correlator implementations and a relatively small required die area.
  • the inventive structure and method uses a different approach and implements the correlation using continuous-time processing. The result is an overall simpler implementation with a lower power consumption and minimal die area, as compared to heretofore known techniques.
  • the invention includes a correlator structure which receives two input signals, the receive baseband signal which is the demodulated receive signal after the RF carrier has been removed and a PN code signal.
  • the correlator includes a multiplier coupled to an integrate-and-dump circuit. The multiplier multiplies the two input signals and produces a multiplier output current that is integrated by an integrate- and-dump function which produces a voltage which is proportional to the correlation between the two input signals. This voltage is the correlator output voltage.
  • the invention includes a correlator method of multiplying the receive baseband signal with a locally generated PN code signal producing a multiplied output current. Then integrating the multiplied output current onto a continuous-time and switched capacitor circuit thus producing a correlator output voltage.
  • FIG. 1 is an illustration showing an exemplary embodiment of a block diagram of the baseband signaling portion of a receiver for DS-CDMA applications.
  • FIG. 2a is an illustration showing an exemplary embodiment of a block diagram for a digital implementation of the block diagram of FIG. 1.
  • FIG. 2b is an illustration showing an exemplary embodiment of a block diagram for the inventive analog implementation of the block diagram of FIG. 1, and method for reducing the speed requirements of the analog-to-digital interface and for reducing the overall power consumption of the receiver.
  • FIG. 3 a is an illustration showing an exemplary embodiment of a first embodiment of the analog correlator.
  • FIG. 3b is an illustration showing an exemplary embodiment of a second embodiment of the analog correlator utilizing a fully-differential architecture.
  • FIG. 4a is an illustration showing an exemplary embodiment illustrating the first embodiment of the analog correlator of FIG. 3 a.
  • FIG. 4b is an illustration showing waveforms corresponding to signals in the embodiment of FIG. 4a and illustrating the operation of the analog correlator.
  • FIG. 4 is an illustration showing an exemplary embodiment of a Gilbert cell multiplier circuit.
  • FIG. 5a is an illustration showing a flow diagram of the functions performed by the exemplary embodiment of the analog correlator shown in FIG. 3 a.
  • FIG. 5b is an illustration showing a flow diagram of the functions performed by the exemplary embodiment of the analog correlator utilizing fully-differential processing shown in FIG. 3b.
  • FIG. 6a is an illustration showing the circuit structure of the Gilbert cell or Gilbert multiplier in CMOS technology utilizing NMOS transistors.
  • FIG. 6b is an illustration showing the circuit structure of the Gilbert cell utilizing degeneration resistors to modify the performance of the structure shown in FIG. 6a.
  • FIG. 7 is an illustration showing an exemplary embodiment of an IC correlator including the multiplier, current coupling circuit, load capacitors, and reset circuit where the correlator employs a telescopic integrator section also providing common-mode feedback.
  • FIG. 8 is an illustration showing an exemplary embodiment of an IC correlator including the multiplier, current coupling circuit, load capacitors, and reset circuit where the correlator employs a folded-cascode integrator section also providing common-mode feedback.
  • FIG. 9 is an illustration showing an exemplary embodiment of a circuit implementing the PN Code Level Translator function required to interface the Receive PN Code Generator output to the analog correlator.
  • This invention provides a new integrated circuit structure for a correlator, method of correlation, and method for the design of a correlator for DS-CDMA spread-spectrum systems in the analog domain.
  • the inventive structure and methods provide both for significantly lower power consumption than known conventional digital correlator implementations and a relatively small required die area.
  • This new approach for analog implementation of the correlator function for spread spectrum systems which can be implemented in digital CMOS technologies exploits the ease with which both multiplication and integration can be performed in the analog domain. Since it performs the correlation in the analog domain, it can be used to correlate arbitrary analog waveforms.
  • the inventive approach is also appropriate for high-speed and low-power applications.
  • the invention is ideally suited to operate with DS-CDMA signaling.
  • the inventive structure and method implements the correlation using continuous- time processing and is amendable to integrated circuit technologies. The result is an implementation having a lower power consumption and minimal die area, as compared to heretofore known structures and techniques.
  • An interferer can be, among others, another user, multipath fading, reflections, other noise generated from electrical devices.
  • the present analog correlator can be implemented, unlike the SAW and CCD prior art approaches, in a low-cost standard digital silicon CMOS technology utilizing the accepted power supply for CMOS systems, for example a standard 3V supply for a 0.35 Fm CMOS technology.
  • the present analog correlator further implements the correlation via a high-performance multiplication and integration thus implementing the ideal equations directly, unlike the Ad Hoc Mixed-Signal implementations with highly compromised performance as described above. This high-performance and integration results in performance which approaches the ideal expected for DS-CDMA signaling.
  • the Switched-Capacitor Analog approach described above operates in the charge domain and thus tends to be parasitic sensitive.
  • the present correlator operates using voltages and currents allowing the correlator to be designed to be more robust to parasitic capacitance.
  • One of the novel features of the correlation approach of the present invention is that it can achieve 7-8 bits of processing at a lower power consumption and smaller die area than can be achieved in the prior art digital implementations.
  • the prior art digital implementations have compromised performance with the use of a small numbers of bits in the front-end A/D converter or have very high power consumption with the use of 7-8 bits in the front-end A/D converter.
  • the present correlator achieves wide dynamic range, robustness to continuous- wave interferers and large effective numbers of bits in correlation in a small die area while being far less sensitive to parasitic capacitance.
  • the present invention can be used in a wide range of communication applications such as wireless networking (home networks, local area networks, wide-area networks), global positioning system (GPS), radio-frequency identification (RF ID), cellular voice and data, satellite voice and data, wired networking such as cable modems, toys which communicate over wireless links, remote sensing; and data storage applications such as magnetic storage hard drives, compact disks, and digital video disks (DVD).
  • wireless networking home networks, local area networks, wide-area networks
  • GPS global positioning system
  • RF ID radio-frequency identification
  • cellular voice and data such as cable modems, toys which communicate over wireless links, remote sensing
  • data storage applications such as magnetic storage hard drives, compact disks, and digital video disks (DVD).
  • DS-CDMA digital versatile disks
  • phase-shift key modulation phase-shift key modulation
  • FIG. 1 An exemplary embodiment of the key receiver baseband signal processing blocks is provided in FIG. 1.
  • RF radio-frequency
  • correlator 255 includes a multiplier circuit 260 and an integrate-and- dump circuit 265.
  • Multiplier 260 within correlator 255 receives Receive Baseband Signal 120 from, for example, an RF demodulator followed by a filter (not shown) as is known in the art. Multiplier 260 also receives a second input signal, the output signal of the Pseudorandom Number (PN) Code Generator 295 which is described in greater detail hereinafter.
  • PN Pseudorandom Number
  • the multiplier output signal 310 is communicated to the integrate-and-dump circuit 265 which generates a correlator output signal representing the correlation between the signals applied to the two multiplier inputs.
  • the integrate-and-dump circuit 265 integrates the multiplier output for the duration of a data bit. At the end of an integration period: a) the output of circuit 265 is sampled by circuit block(s) that follow; b) the output is reset to a zero reference; and c) integration for the following received bit commences.
  • the correlator output signal is communicated to two blocks: a Decision circuit 280 which utilizes the correlator output to determine the received data bits; and to the serial combination of a Chip Synchronization circuit 285 a Voltage- or Numerically- Controlled Oscillator 290.
  • Synchronization circuit 285 is responsible for generating a control signal derived from correlator output 330, while controlled oscillator 290 receives the synchronization circuit output 286 and generates a clock signal 291 that is provided as the input to Receive PN Code Generator 295.
  • the Receive PN Code Generator output 121 is the second input into mixer 260 as already described.
  • Decision circuit 280 may be a simple thresholding circuit as is know in the art or more complex (such as a sequence detector). The decision circuit 280 generates an output bit 122 decision for each correlated bit received.
  • Data transmission for systems employing phase-shift keying signaling is typically sent in quadrature, that is data is sent on two carriers at the same frequency separated by a 90 degree phase difference and thus doubling the amount of information that can be transmitted and received.
  • Architectures for quadrature reception can be devised utilizing the correlator invention as a building block by using the correlator invention (described more fully below) in places where the correlation function is required.
  • FIG. 2a A block diagram of an embodiment of a digital implementation of the block diagram of FIG. 1 is shown in FIG. 2a.
  • This system 200 has features in common with the system already shown and described relative to FIG. 1, except that the receive baseband signal 201 is passed through an analog-to-digital (A/D) converter 204 at the front-end prior to Correlator 211 and all of the baseband processing blocks.
  • Correlator 211 receives as input, the output of ADC 210 and the output of Receive PN Code Generator 214 as already described.
  • each of the blocks except the oscillator 235 (which may be implemented in either the analog or digital domain) are implemented in the digital domain.
  • the analog-to-digital interface 204 and all the digital processing must be operated at a minimum of twice and often greater than twice the chip rate.
  • the chip rate is the rate at which the modulating PN code is generated and typically a minimum of 10 and as much as 1000 or more times greater than the data bit rate. Sampling the input signal and processing at the minimum of twice the chip rate is required in order to maintain benefits of DS-CDMA (See reference [4]).
  • the number of bits in the analog-to-digital conversion is limited to a small number (typically one or two) due to power consumption considerations in the correlator. This limits the dynamic range of the Receive Baseband Signal 201 as well as the overall receiver sensitivity.
  • the receiver channel architecture illustrated in FIG. 2b provides structure and method for: 1) reducing the speed requirements of the analog-to-digital interface 204; 2) reducing the overall power consumption of the receiver which is implemented through the correlator of the present invention; 3) increasing the input dynamic range; and 4) increasing receiver sensitivity.
  • the multiplication of the Receive Baseband Signal 120 with the Receive PN code signal 125 in correlator 255 and the subsequent integrate-and-dump operation are performed in the analog domain. This allows analog-to-digital converter 275 to operate at a rate near the data bit rate as opposed to multiples of the chip rate (See reference [4]) and eliminates the need for the high-speed digital correlation.
  • analog correlator 255 A first embodiment of analog correlator 255 is shown with signal inputs and outputs in the block diagram of FIG. 3a.
  • the two input signals are voltages: Vm 120, which is the Receive Baseband Signal; and V PN Local 125, which is a level translated version of the Receive PN code generator output 121.
  • the correlator is comprised of five key blocks: (1) an analog multiplier 260; (2) a current coupling circuit 353; (3) an integration capacitor 315; (4) an integration reset circuit 354; and (5) a PN code level translator 360.
  • the analog multiplier 260 generates a multiplier output current lout 310 that has a bias component Ibi as that is constant, independent of the input signal, and a signal component Isignai that is proportional to the product between the two input voltage signals.
  • the current coupling circuit 353 which couples I ou t 359, and more preferably just the signal carrying component ignai to the integration capacitance Cmtegrate 315 which integrates the multiplier output current 310.
  • the integration reset circuit 354 initializes or precharges the correlator output voltage V ou t 310 across the integration capacitance 315 to a zero reference value.
  • the PN code level translator 360 converts receive PN code generator output 121 from binary levels with values equal to the power supply or ground to appropriate levels for receive PN code signal 125 into the multiplier 260.
  • FIG. 4a shows a conceptual block diagram illustrating the functioning of the analog correlator described above.
  • the multiplier 260 multiplies the receive baseband signal 120 and the receive PN code signal 125 and outputs a multiplier output current 310 proportional to the product of the input voltages.
  • the Current Coupling Circuit 353 of FIG. 3 a is simply a wire connecting the multiplier output to the integration capacitor Curate 315.
  • the integration reset circuit 354 of FIG. 3a is an NMOS initialization switch 340.
  • the gate terminal of the initialization switch 340 is coupled to a reset signal 335 while the source of the initialization switch 340 is coupled to the negative terminal of the integration capacitor 315 (also connected to ground).
  • the correlator output 330 is shown in FIG. 4b for three data bits where a "1" data bit is followed by a succession of two "0" data bits.
  • the Receive Baseband Signal 120 is shown as a pseudorandom number (PN) code with one polarity representing a "1" data bit and the same code with the opposite polarity for the "0" data bit.
  • PN pseudorandom number
  • the receive PN code generator aligns the locally generated PN code to the incoming receive baseband signal 120 as shown.
  • the reset f reset signal 335 is shown active (HIGH) for one chip time at the beginning of each received bit. During this time, the correlator output voltage V ou t 330 is reset to zero volts.
  • the multiplier output current 310 is integrated by the integration capacitor 315. In this example, since input signals 120 and 125 are aligned, multiplier output current 310 is constant with a positive polarity in the case of the "1" data bit and constant with a negative polarity in the case of the "0" data bits.
  • the correlator output voltage 330 ramps linearly to a positive value in the case of the "1" bit and to a negative value for the "0" data bits.
  • the correlator output voltage 330 is sampled by the stage that follows (possibly an A D converter). Then, reset 335 becomes active and turns on reset switch 340, resetting the integration capacitor 315 to zero volts for the start of a new correlation cycle.
  • Resetting the integration capacitance once every data bit highlights a signal processing compromise.
  • reset signal 335 is on for one chip time, thus the multiplier output current 310 is simply shunted to ground. The result is the multiplier output current 310 during this time interval makes zero contribution to the correlation, and can compromise the accuracy of the correlation.
  • Two possible solutions follow. The first possible solution is to reduce the time duration that the reset signal 335 is active. This will reduce the amount of output current shunted to ground and minimize any error effect of the reset process on the correlation.
  • a second possible solution is to use an architecture where one multiplier feeds two time-interleaved integrate-and-dump sections. While one section is integrating the output current from the multiplier, the other is resetting the voltage across its integration capacitor.
  • the multiplier output switches to the second section while the first is reset. In this way, zero correlation time is spent by either of the correlators in the reset mode during a correlation interval. Solutions such as these enable the effect of the reset process to be sufficiently small as to become inconsequential or even eliminated for a modest cost in additional hardware.
  • a preferred embodiment of analog correlator 255 utilizes a fully-differential architecture as shown in FIG. 3b.
  • the fully-differential architecture results in increased dynamic range and rejection of common-mode signals which are typically noise signals.
  • the same five key functional blocks of FIG. 3a are present except that the output of the multiplier has two output currents I ou u 310a and I ou t 2 310b and the signal information is contained in the difference between these two output currents 310a and 310b.
  • Current coupling circuits 353a and 353b are shown separately but may be implemented together as a single block.
  • the correlator output voltage V out 390 is defined as the difference between V ou t+ 375 and V ou t- 385 which are defined across the integration capacitors ntegratei 315a and Ci constitutionaltegrate 2 315b, respectively.
  • Multiplier output currents 310a and 310b may be coupled to capacitors 315a and 315b directly to integrate the output currents.
  • the signal components (I s ignai) of the output current are coupled to the integration capacitors 315a and 315b.
  • Integration reset circuits 354a and 354b reinitialize the correlator output voltages 330a and 330b at the end (or beginning) of an integration period.
  • a similar PN Code Level Translator 360 can be used as described for the approach shown in FIG. 3 a in the fully-differential implementation.
  • the fully-differential architecture requires the addition of common-mode feedback. Possible implementations for each of these blocks are presented hereinafter.
  • FIG. 5 a A flow-chart of the correlation procedure is shown in FIG. 5 a.
  • the correlation between two input signals is continuously performed for a finite duration called a correlation period.
  • this structure is suitable for applications where the data bit period is equal to the correlation period.
  • an output signal proportional to the correlation between the two input signals is generated 653.
  • a Receive RF Signal 670 is processed by the RF Front- End 671 which removes the RF carrier, provides amplitude control and establishes the input common-mode level of the Receive Baseband Signal 120.
  • the Receive baseband signal 120 is one of two inputs into the multiplier block 650 which performs the analog multiplication of the two input signals.
  • the Receive PN Code Generator Output 121 is level translated 672 to generate the second analog multiplier input 125. These two signals are multiplied in the analog domain and a multiplier output signal is generated 651.
  • the multiplier output 651 is then integrated 652.
  • the multiplier output 651 can be a current, in which case the integration function 652 can be performed by feeding this current to a capacitor. The continuous integration of the current onto the capacitor will generate an output voltage across the capacitor.
  • the integration of the multiplier output 651 produces the correlator output 653.
  • the correlator output 653 is then sampled 654.
  • the reset function 654 then triggers the integrator is reset to a zero reference.
  • the integration is performed by integrating the multiplier output current onto a capacitor (or capacitors in the case of a fully-differential implementation)
  • the voltage across the capacitor is reset to a zero reference. The process is then repeated until the entire received RF signal has been correlated.
  • the effect of leakage currents associated with reverse biased PN junctions can accumulate over time and become significant over the course of a long correlation period.
  • the multiplier output is a current and the integration is performed by integrating the output current onto a capacitor.
  • Reverse biased PN junctions inherent in integrated circuit transistor structures will be connected to the integrating capacitor.
  • the leakage current will result in the removal of current from or the addition of current to the integrating capacitance, affecting the accuracy of the correlation.
  • One solution is to use a composite correlator structure in which the inventive analog correlator is followed by a second structure called a Partial Result Accumulator.
  • FIG. 5b A flow-chart for the correlation of two signals utilizing a composite correlator comprising the inventive analog correlator 255 and a Partial Result Accumulator 701 is shown in FIG. 5b.
  • This structure enables and affects a composite correlation period longer than the correlation period of the analog correlator 255.
  • the composite correlation period will typically be comprised of a multiplicity of equal or nearly equal duration correlation periods of the analog correlator 255.
  • the composite correlator output is the accumulated sum of analog correlator outputs 653 over the composite correlation period. Each sample of the analog correlator output is called a partial result.
  • a composite correlator output is generated by accumulating partial results over the composite correlation period.
  • both the accumulator which implements the accumulate function 682 and the integrator which implements the integrate function 652 in the inventive analog correlator 255 are reset to zero and the composite correlation commences.
  • the first correlation period of the inventive analog correlator is complete (defined by the correlator reset signal 335)
  • its output is sampled 680 by the partial result accumulator 701 and comprises the first partial result.
  • the integrator implementing the integration function 652 in the inventive analog correlator is then reset and the next correlation period begins.
  • reset signal 335 signifies the end of the second correlation period of analog correlator 255, the partial result accumulator
  • the partial result accumulator 701 can be implemented in either the analog or digital domain.
  • An analog implementation might use switched-capacitor techniques where the partial results are sampled from the analog correlator 255 output onto sampling capacitors of equal value. A correlator output is generated by summing the charge sampled onto the sampling capacitors, and converting the total sampled charge to an output voltage.
  • the partial result accumulator 701 is a switched-capacitor circuit. Other switched-capacitor embodiments are possible.
  • a digital implementation will involve an A/D converter.
  • Partial correlation results are generated by the inventive analog correlator 255 and sampled and converted to digital representation by an A/D converter.
  • the partial result accumulator is a digital integrator circuit which accumulates digital representations of the partial results. While this method involves an A/D converter in the correlation, the A/D converter is able to operate at a rate that is still much less than the chip rate and benefits of the inventive analog correlator 255 can still be realized.
  • FIG. 6a illustrates a prior art Gilbert cell or multiplier implemented in CMOS technology.
  • the Gilbert cell 260 is shown constructed from a set of grouped NMOS transistors. An implementation comprised of PMOS transistors is also possible with the appropriate modifications.
  • the circuit receives two differential input voltages V; strictly 120 and a V PN Local 125.
  • Multiplier output currents I ou ti 310a and I ou t 2 310b both contain a common bias term which biases the NMOS transistors and a signal term opposite in polarity from one another and proportional to the product between inputs 120 and 125.
  • Designing the input coupling circuits such that the input common- mode level for both pairs of inputs V; n 120 and a V N ocal 125 is such that all six transistors (366, 368, 370, 372, 376, and 378) operate in the saturation region with zero differential input is desirable.
  • Designing the Gilbert multiplier 260 such that transistors 376 and 378 operate as a linear transconductor stage is also desirable.
  • transistors 366, 368, 370, and 372 together with the input voltage levels of VpN Locai 125 such that transistor pair 366-368 and pair 370-372 operate as current switches such that all the current from transistors 376 and 378 flows in either 366 or 368 and 370 or 372, respectively, and such that this switching occurs with the minimum excursion of voltages on nodes 373a and 373b is also desirable.
  • the Gilbert multiplier circuit see B. Gilbert "A precise four quadrant multiplier with sub- nanosecond response," IEEEJ. Solid-State Circuits, pp. 365-373, Dec. 1968; which is hereby incorporated by reference.
  • the U.S. Patent No. 5,768,700, "High Conversion Gain CMOS Mixer", describing the use of a Gilbert cell is also incorporated by reference.
  • multiplier is the modified Gilbert multiplier shown in FIG. 6b.
  • resistors 387 and 388 are added to degenerate the differential pair comprised of transistors 380 and 381.
  • the same desirable design parameters for the multiplier of FIG. 6a described above still apply.
  • the result of the degeneration is to reduce the input transconductance, increase the input linear range, and increase the linearity of the transconductance of the input differential pair to which voltage Vi estate 120 is applied.
  • MOS or IGFET transistor structures or combination technologies which include both
  • differential pairs M1-M2 366-368 and M3-M4 370-372 can be degenerated with resistors or triode region transistors to increase input linear range as had been shown in FIG. 6b;
  • the current that flows into its two output terminals which are the nodes connecting the drains of Ml 366 and M3 370 and the drains of M2 368 and M4 372 have two components, a bias component equal to one-half of bias current Ib si 415, and a differential component proportional to the product between the two input voltages V P N
  • a preferred embodiment of the Current Coupling Circuits 371, integration capacitors Cimegratei 374 and Ci nteg rate 2 384, and the integration reset circuit 373 of FIG. 3b is shown in a compact form in FIG. 7.
  • a Gilbert multiplier 260 is shown coupled to the circuit components which perform the three key functions of current coupling, integration, and reset described earlier.
  • Biasing current transistors 420a and 420b provide the bias current component from the positive supply VDD 10 for the Gilbert multiplier 260. Since the correlator output nodes 425a, 425b are high impedance nodes, common-mode feedback is used to define and stabilize the DC bias voltage of these nodes near a common-mode output reference voltage V o o m 390 that is generated by a separate circuit.
  • Integration capacitors Cintegratei 316 and Ci n t eg rate 317 perform double duty. First, they act as the integration capacitors 376.
  • the multiplier output 310 of Gilbert multiplier 260 has two components, a bias term and a signal term.
  • the bias term is provided by first and second PMOS biasing current source devices 420a and 420b. Since the current from VDD 10 is fixed by the first and second biasing current source devices 420a and 420b, the differential multiplier output current 310 from the Gilbert multiplier 260 can only flow to the integration capacitors 316 and 317. Thus, this coupling circuit 353 removes the bias term and couples only the signal carrying term to capacitors 316 and 317 as is preferred.
  • both bias and signal terms of the multiplier output current 310 can be output to the integration capacitors and the resulting common-mode voltage resulting from the bias term removed by a later signal processing step). Second, they participate in implementing common-mode feedback. During the period that the reset signal 335 of FIG. 3b is active (HIGH), signal 335 of FIG. 7 is LOW thus activating the first, second and third PMOS reset switches 430a, 430b, and 435.
  • first and second biasing current transistors 420a and 420b When the third reset switch 435 turns on, the gates of first and second biasing current transistors 420a and 420b (node 426) are coupled to the gate-drain connection of a third biasing current transistor 420c (node 427) through third reset transistor 435.
  • the first and second biasing current transistors 420a and 420b now have the same gate-source voltage as the third biasing current transistor 420c and as a result, they mirror the current which flows in the third biasing current transistor 420c which equals the second biasing current Ibias2 416.
  • the first and second PMOS reset switches 430a and 430b turn on and force correlator output nodes 425a and 425b to the output common-mode voltage Voc m 390.
  • the output common-mode voltage 390 will typically be chosen to maximize the output voltage swing at the correlator output voltage V out 330; for example, in the case where the power supply is 3 V, an appropriate value for 390 will be around 2 V.
  • the reset signal 335 becomes inactive, the first, second and third PMOS reset switches 430a, 430b, and 435 are turned off.
  • the differential signal currents from the multiplier flow to the integration capacitors 316, 317 causing the voltage at output nodes 425a and 425b to move in opposite directions. Capacitors 316 and 317 couple output node voltage changes back to node 426.
  • FIG. 8 Another embodiment of the Current Coupling Circuits 373 and 383, integration capacitors Cinugratei 315a and Cintegmtc2 315b, and the first and second integration reset circuits 373 and 383 of FIG. 3b are shown in FIG. 8. While the approach shown in FIG. 7 utilizes the so-called telescopic architecture, the embodiment of Fig. 8 utilizes a folded- cascode architecture. Compared with the telescopic architecture, the fold-cascode provides: increased output voltage swing; more flexibility in definition of the output common-mode voltage level; and increased output resistance at the output nodes. A high output resistance is important in order to maintain linearity in the integration function.
  • the Gilbert Multiplier couples to the sources of PMOS common-gate transistors 611a and 611b.
  • PMOS transistors 610a and 610b mirror the current in 610c and act as first and second current sources, providing bias current from VDD 10 to the Gilbert multiplier and to first and second NMOS cascode current sources comprised of transistor pair 612a and 613a and transistor pair 612b and 613b (where 612a and 612b are the cascode transistors), through first and second PMOS common-gate transistors 611a and 611b.
  • the differential multiplier output current 310 from the Gilbert multiplier 260 can only flow into the integration capacitance 316 and 317.
  • this coupling circuit 353 utilizing the folded- cascode architecture removes the bias term (as did the telescopic architecture described earlier) and couples only the signal carrying term to capacitors 316 and 317 as is preferred.
  • both bias and signal terms of the multiplier output current 310 can be output to the integration capacitors and the resulting common-mode voltage resulting from the bias term removed by a later signal processing step as was the case with the telescopic architecture.
  • the integration capacitance 316 and 317 perform double duty, acting as the integration capacitance and participating in common-mode feedback.
  • the presence of common-mode feedback ensures the assumption that the total DC bias current from VDD 101 is equal to the total DC bias current into VSS 100.
  • Switching and operation of the integration reset circuit 373 is similar to that with the telescopic architecture except that it uses NMOS transistors and thus, is not described again.
  • This architecture can also benefit from the use of gain-boost amplifiers that involve the use of amplifier stages and the cascode devices 611a, 611b, 612a, and 612b to further increase output resistance, and thus the linearity of the integration.
  • gain-boost amplifiers that involve the use of amplifier stages and the cascode devices 611a, 611b, 612a, and 612b to further increase output resistance, and thus the linearity of the integration. This well known technique is described in the literature and is not described further.
  • Both the telescopic and folded-cascode architectures have been used in transconductance amplifiers for CMOS and BiCMOS A/D converters, digital-to-analog converters, and other mixed-signal applications.
  • the Receive PN code generator output 121 is a digital signal with binary values equal to the power supply (VDD 451a) or ground 451b as shown in the left side of FIG. 9a. These levels are not suitable to interface to Gilbert cell embodiments of the multiplier 260 which require differential signals VPN L ocai+ 491 and VPN oc l- 492 as shown in the right side of FIG. 9a.
  • Reference voltages or binary levels VI 461 and V2 462 are designed with the following three design goals described in the discussion of the design of the Gilbert multiplier design above and summarized here: a) so that their average value provides an appropriate common-mode level for input V PN L ocal 125 to the Gilbert multiplier 260; b) so that the voltage swing is large enough to switch the current between current switch devices in the Gilbert multiplier 260, and c) so that the node voltages at the drains of the input differential pair 376, 378 connected to Vj counsel 120 is minimized during switching of input 125.
  • FIG. 9b A preferred embodiment of the PN Code Level Translator 360 is shown in FIG. 9b.
  • This implementation has the advantages of zero DC power in all portions of the translation circuit that are switching with the PN code and a high operating speed capability.
  • Reference voltage levels VI 461 and V2 462 are applied to multiplier input nodes 491 and 492 through switches 484-487 controlled by receive PN code generator output 121 via logic circuits contained in the PN Code Level Translator Logic 488.
  • the PN Code Level Translator Logic 488 converts input 121 to generate control signals 482 and 483 that are alternately active and control switches 484-487. For example, in one implementation, when input 121 is logic HIGH, 482 is active HIGH and 483 is in the inactive state LOW. Under these conditions, 482 activates switches S 1 484 and S4 487 connecting input V PN Loc l + 491 to VI 461 through switch SI 484 and V PN Local- 492 to V2
  • control signal 482 is inactive, and switches S 1 484 and S4 487 are in the off state.
  • the first and second reference voltages VI 461 and V2 462 can be generated in a number of ways.
  • One embodiment is to use a resistor ladder from the power supply (VDD 451a) to ground 451b and tap off at appropriate points to define reference voltage levels 461 and 462.
  • the use of large resistor values in the resistor ladder minimizes the power dissipated by this circuit.
  • Appropriate use of capacitors (not shown) connected between first and second reference voltages VI 461 and V2 462 and ground minimize the magnitude of voltage transients on first and second reference voltage levels 461 and 462 during switching.
  • the inventive structure advantageously provides the correlation function as required in communication systems employing DS-CDMA signaling enabling architectures and implementations that: can achieve lower power consumption than conventional digital methods with the use of simple, power efficient circuit structures; are amenable to integration in low-cost integrated circuit technologies and can thus result in increased system integration at lower cost than previous analog implementations utilizing surface acoustic wave (SAW) filter technology; can achieve a higher sensitivity than practical digital implementations by performing the correlation prior to the introduction of quantization noise introduced by analog-to-digital conversion; can accommodate a higher dynamic range by maintaining linearity in the correlation over a wider input signal range than practical digital implementations; can require less area on an integrated circuit as compared with a digital approach due to its simplicity; and have qualities that will become increasingly attractive when compared to digital implementations as chip rates and data rates increase since very high bandwidth multiplication and integration can be implemented by the simple, elegant structure of a multiplier cell whose output current feeds a capacitor to implement a correlator
  • This inventive structure is capable of providing this function for other applications requiring the determination of the correlation between two signals; but is especially effective when one of the signals is a binary signal or can be approximated as such as is the case in the baseband processing of DS-CDMA systems where the PN sequence is a binary signal.
  • the present invention provides significant advantages over the prior art.
  • Some of the important effects of the present correlator which can function for DS-CDMA receivers in the analog domain include: (1) receivers with significantly lower power consumption than with conventional digital and recently proposed analog approaches; (2) amenable to integration on low-cost integrated circuit processes such as digital silicon CMOS technologies, thus resulting in high-integration receivers; (3) performing correlation prior to the analog-to-digital conversion and thus realizes the benefits of DS- CDMA processing to continuous-wave and other interferers; and (4) large input dynamic range, relaxing requirements of power control in overall system design.

Abstract

La présente invention concerne un corrélateur destiné à être mis en oeuvre dans des applications à spectre étalé utilisant un traitement du signal du domaine analogique dans le temps continu. Le corrélateur inclut un multiplicateur (260) couplé à une capacité d'intégration (315), et un circuit de réinitialisation d'intégration (354) couplé à la capacité d'intégration (315). Le corrélateur est conçu pour recevoir un premier signal d'entrée (120) et un deuxième signal d'entrée (125). Le multiplicateur (260) multiplie le premier signal d'entrée (120) par le deuxième signal d'entrée (125) pour produire un courant de sortie de multiplicateur (310a, 310b), lequel est ensuite intégré par la capacité d'intégration (315) pour produire une tension de sortie de corrélateur (330). Le circuit de réinitialisation d'intégration (354) réinitialise ensuite la capacité d'intégration (315) à une tension de réinitialisation.
PCT/US1999/020525 1998-09-08 1999-09-07 Correlateur analogique a temps continu et spectre etale, et procede le concernant WO2000014892A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU63847/99A AU6384799A (en) 1998-09-08 1999-09-07 Spread-spectrum continuous-time analog correlator and method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9950798P 1998-09-08 1998-09-08
US60/099,507 1998-09-08

Publications (2)

Publication Number Publication Date
WO2000014892A1 true WO2000014892A1 (fr) 2000-03-16
WO2000014892B1 WO2000014892B1 (fr) 2000-05-18

Family

ID=22275335

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/020525 WO2000014892A1 (fr) 1998-09-08 1999-09-07 Correlateur analogique a temps continu et spectre etale, et procede le concernant

Country Status (3)

Country Link
US (1) US6330274B1 (fr)
AU (1) AU6384799A (fr)
WO (1) WO2000014892A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016113537A1 (fr) * 2015-01-16 2016-07-21 The Secretary Of State For Defence Procédé de positionnement par satellite, et récepteur de positionnement par satellite
CN110081991A (zh) * 2019-05-05 2019-08-02 聚辰半导体股份有限公司 一种可用于温度传感器的小数倍信号放大装置及方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6493404B1 (en) * 1999-03-01 2002-12-10 Sharp Kabushiki Kaisha Recycling integrator correlator
TW483255B (en) * 1999-11-26 2002-04-11 Fujitsu Ltd Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission
US7205939B2 (en) 2004-07-30 2007-04-17 Novariant, Inc. Land-based transmitter position determination
US7532160B1 (en) 2004-07-30 2009-05-12 Novariant, Inc. Distributed radio frequency ranging signal receiver for navigation or position determination
US7342538B2 (en) 2004-07-30 2008-03-11 Novariant, Inc. Asynchronous local position determination system and method
US7271766B2 (en) 2004-07-30 2007-09-18 Novariant, Inc. Satellite and local system position determination
US7315278B1 (en) 2004-07-30 2008-01-01 Novariant, Inc. Multiple frequency antenna structures and methods for receiving navigation or ranging signals
US7339526B2 (en) 2004-07-30 2008-03-04 Novariant, Inc. Synchronizing ranging signals in an asynchronous ranging or position system
US7339524B2 (en) * 2004-07-30 2008-03-04 Novariant, Inc. Analog decorrelation of ranging signals
US7339525B2 (en) 2004-07-30 2008-03-04 Novariant, Inc. Land-based local ranging signal methods and systems
US7428259B2 (en) * 2005-05-06 2008-09-23 Sirf Technology Holdings, Inc. Efficient and flexible GPS receiver baseband architecture
US20070149113A1 (en) * 2005-12-28 2007-06-28 Fitzrandolph David K Signal presence detection
US7746274B2 (en) * 2006-06-20 2010-06-29 Atheros Communications, Inc. Global positioning receiver with PN code output
US7782252B2 (en) * 2007-06-02 2010-08-24 Inchul Kang System and method for GPS signal acquisition
US8049665B1 (en) 2007-06-02 2011-11-01 Inchul Kang System and method for selecting a local C/A code for GPS signal processing
WO2010046957A1 (fr) * 2008-10-24 2010-04-29 株式会社アドバンテスト Démodulateur d’amplitude orthogonale, procédé de démodulation, dispositif à semi-conducteurs utilisant ceux-ci, et dispositif de test
US8232831B2 (en) * 2009-11-24 2012-07-31 Bae Systems Information And Electronic Systems Integration Inc. Multiple input/gain stage Gilbert cell mixers
US8638888B2 (en) * 2011-07-21 2014-01-28 Infineon Technologies Ag Analog correlation technique for ultra low power receivers
KR101982895B1 (ko) * 2011-07-28 2019-05-27 엘모스 세미콘두크터르 아크티엔게젤샤프트 Uwb 장치를 동작하는 방법
DE102012019342A1 (de) 2012-10-03 2014-04-03 Johann Christoph Scheytt Mixed-signal PSSS-Empfänger
US10084983B2 (en) * 2014-04-29 2018-09-25 Fermi Research Alliance, Llc Wafer-scale pixelated detector system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567588A (en) * 1984-03-23 1986-01-28 Sangamo Weston, Inc. Synchronization system for use in direct sequence spread spectrum signal receiver
US5574721A (en) * 1994-12-09 1996-11-12 Stanford Telecommunications, Inc. Orthogonal code tracking system having phantom carrier signal
US5822423A (en) * 1996-03-20 1998-10-13 Numerex Investment Corporation Apparatus and method for supervising derived channel communications

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2461411B1 (fr) 1979-07-13 1985-10-31 Trt Telecom Radio Electr Systeme de transmission de donnees utilisant les principes d'etalement du spectre
US4400790A (en) 1981-01-06 1983-08-23 E-Systems, Inc. Transversal correlator
US4475208A (en) * 1982-01-18 1984-10-02 Ricketts James A Wired spread spectrum data communication system
JPS6484933A (en) * 1987-09-26 1989-03-30 Kenwood Corp Receiver
US5146471A (en) 1989-03-23 1992-09-08 Echelon Systems Corporation Correlator for spread spectrum communications systems
JP2720076B2 (ja) * 1989-07-17 1998-02-25 京セラ株式会社 直接スペクトラム拡散受信機の自動校正装置
CH679718A5 (fr) 1989-10-19 1992-03-31 Ascom Zelcom Ag
GB9027716D0 (en) * 1990-12-20 1991-02-13 British Telecomm Optical communications system
US5175557A (en) * 1991-07-18 1992-12-29 Motorola, Inc. Two channel global positioning system receiver
US5388126A (en) 1992-12-21 1995-02-07 Rypinski; Chandos A. Baseband signal processor for a microwave radio receiver
US5276705A (en) 1993-01-06 1994-01-04 The Boeing Company CCD demodulator/correlator
US5488629A (en) 1993-02-17 1996-01-30 Matsushita Electric Industrial Co., Ltd. Signal processing circuit for spread spectrum communications
US5768700A (en) 1996-03-14 1998-06-16 Advanced Micro Devices, Inc. High conversion gain CMOS mixer
JPH10229378A (ja) * 1996-04-02 1998-08-25 Sharp Corp マッチドフィルタ
US5872446A (en) 1997-08-12 1999-02-16 International Business Machines Corporation Low voltage CMOS analog multiplier with extended input dynamic range
US5847623A (en) 1997-09-08 1998-12-08 Ericsson Inc. Low noise Gilbert Multiplier Cells and quadrature modulators

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567588A (en) * 1984-03-23 1986-01-28 Sangamo Weston, Inc. Synchronization system for use in direct sequence spread spectrum signal receiver
US5574721A (en) * 1994-12-09 1996-11-12 Stanford Telecommunications, Inc. Orthogonal code tracking system having phantom carrier signal
US5822423A (en) * 1996-03-20 1998-10-13 Numerex Investment Corporation Apparatus and method for supervising derived channel communications

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016113537A1 (fr) * 2015-01-16 2016-07-21 The Secretary Of State For Defence Procédé de positionnement par satellite, et récepteur de positionnement par satellite
CN110081991A (zh) * 2019-05-05 2019-08-02 聚辰半导体股份有限公司 一种可用于温度传感器的小数倍信号放大装置及方法

Also Published As

Publication number Publication date
AU6384799A (en) 2000-03-27
US6330274B1 (en) 2001-12-11
WO2000014892B1 (fr) 2000-05-18

Similar Documents

Publication Publication Date Title
US6330274B1 (en) Spread-spectrum continous-time analog correlator and method therefor
JP3373746B2 (ja) Ｄｓ−ｃｄｍａ基地局間非同期セルラ方式における初期同期方法および受信機
Perrott et al. A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
Toker et al. High-output-impedance transadmittance type continuous-time multifunction filter with minimum active elements
Senderowicz et al. A 23 mW 256-tap 8 MSample/s QPSK matched filter for DS-CDMA cellular telephony using recycling integrator correlators
Onodera et al. A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speed wireless applications [LANs]
KR100295785B1 (ko) 부호분할다중통신장치
EP0859471B1 (fr) Système de communication à multiplexage par répartition de code
TOGURA et al. Low power current-cut switched-current matched filter for CDMA
US6263012B1 (en) Receiver apparatus for CDMA communication system
Yamasaki et al. A low-power and compact CDMA matched filter based on switched-current technology
Verhelst et al. Design of an energy-efficient pulsed UWB receiver
Yuce A differential-based multiple bit rate PSK receiver: Theory, architecture, and SOI CMOS implementation
Yamasaki et al. A low-power floating-gate-MOS-based CDMA matched filter featuring coupling capacitor disconnection
Nie et al. An IEEE 802.15. 4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CMOS
Kakhki et al. An energy efficient coherent IR-UWB receiver with non-coherent-assisted synchronization
Onodera et al. A 75 mW 128 MHz DS-CDMA baseband correlator for high-speed wireless applications
Eltokhy et al. A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications
Sheng et al. 1.1 Wideband Digital Portable Communications
Eltokhy et al. A study on circuit design of integrated CMOS analog matched filter
Worapishet et al. Low power switched-current FIR core for modern wireless transceivers
Togura et al. Novel low-power switched-current matched filter for direct-sequence code-division-multiple-access wireless communication
Delgado-Restituto et al. Design considerations for a linear modulation DCSK chaos-based radio
JP2000188560A (ja) フィルタ回路
Chen et al. Cmos low-power analogue baseband circuits for a non-coherent low data rate IR-UWB receiver

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref country code: AU

Ref document number: 1999 63847

Kind code of ref document: A

Format of ref document f/p: F

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: B1

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: B1

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

B Later publication of amended claims
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase