WO2000014882A1 - Frequency synthesizers - Google Patents

Frequency synthesizers Download PDF

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Publication number
WO2000014882A1
WO2000014882A1 PCT/JP1999/004713 JP9904713W WO0014882A1 WO 2000014882 A1 WO2000014882 A1 WO 2000014882A1 JP 9904713 W JP9904713 W JP 9904713W WO 0014882 A1 WO0014882 A1 WO 0014882A1
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WO
WIPO (PCT)
Prior art keywords
frequency
period
synthesizer according
voltage
frequency synthesizer
Prior art date
Application number
PCT/JP1999/004713
Other languages
French (fr)
Inventor
Gary Smith
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to AU54463/99A priority Critical patent/AU5446399A/en
Publication of WO2000014882A1 publication Critical patent/WO2000014882A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Definitions

  • This invention relates to a frequency synthesizer for use, for example, in a communications receiver or transmitter such as a digital telephone.
  • a GSM (global system for mobile communication) telephone may make use of a frequency synthesizer for switching between receive and transmit frequencies or for frequency hopping during either transmission or receiving. Such a frequency synthesizer will be required to hop over a 70 MHz bandwidth within one GSM time slot (570 microseconds).
  • Air interface specifications standards for mobile radiotelephones place a tight requirement on the design of frequency synthesizers in respect of lock time, phase noise and phase error. These parameters are closely linked and impose restrictions on the design.
  • An improvement in lock time which does not force changes to other design parameters would be a valuable addition to the prior art . Such an improvement in lock time would also allow greater flexibility in the design process and. provide greater ease of manufacture.
  • a frequency synthesizer comprising a VCO (voltage controlled oscillator) in a phase locked loop, and a speed-up circuit, the speed-up circuit comprising a detector for detecting a difference in period between a reference frequency and a feedback signal frequency, and a circuit for generating a voltage proportional to the difference in period between the reference frequency and the feedback signal frequency, amplifying the voltage and applying the amplified voltage to a frequency control voltage input of the VCO.
  • VCO voltage controlled oscillator
  • Fig. 1 is a block diagram of a frequency synthesizer including a speed-up circuit
  • Fig. 2 is a block diagram of the speed-up circuit
  • Fig. 3 is a circuit diagram of a loop filter.
  • a block diagram of a frequency synthesizer according a preferred embodiment of the present invention is shown and the synthesizer comprises a voltage controlled oscillator (VCO) in a phase locked loop (PLL) .
  • the PLL has phase detector 1, charge pump 2, loop filter 3, VCO 4 and frequency divider 5 and operates to lock the feedback frequency F in phase with the reference signal R.
  • the frequency division ratio N of divider 5 is changed and the frequency of the feed back signal F also changes.
  • the difference in phase between the two signals R and F fed to the phase detector 1 produces an output from phase detector 1 to the charge pump 2.
  • phase detector 1 depends on the amount and direction of the difference in phase between the two signals R and F.
  • the output from the charge pump 2 acts via loop filter 3 to change the frequency of the VCO.
  • the output of VCO 4 fed back to the frequency divider 5 produces a change in the frequency of the feedback signal F and the PLL locks to the new frequency.
  • the adaptive speed-up circuit is shown as in Fig. 1 and comprises time period difference detector 6, time-to- voltage converter 7 and amplifier 8.
  • a measurable time difference will exist between the period of the reference frequency R and the period of the feedback frequency F.
  • the difference in the times of the periods of the frequencies R and F will be proportional to the change of frequency required.
  • a measure of this time difference at the instant when a frequency change is requested will provide an indication of the channel which the synthesizer is seeking to acquire.
  • a time difference measurement of the periods of the frequencies R and F may therefore be converted to a voltage, the value of which will depend upon the frequency change required for the VCO.
  • the time difference measurement is made in detector 6 of Figs. 1 and 2 by means of the circuit shown in Fig. 2, infra.
  • the outputs from period difference detector 6 are fed to time-to-voltage converter 7.
  • the reference frequency R is input to D-type flip-flop (D-FF) 9 which gives an output when the amplitude of reference frequency R is positive.
  • D-FF D-type flip-flop
  • the AND gate 14 is connected across the outputs of flip-flops 9 and 10 and AND gate 14 resets the output lines of flip-flops 9 and 10 to zero when the outputs from flip-flops 9 and 10 are coincident.
  • the frequency and duration of the output pulses from both flip-flops 9 and 10 are the same.
  • the positive output pulses from flip-flops 9 and 10 are fed to charge pumps 11 and 12.
  • a positive pulse applied to charge pump 11 causes a current to flow as an output from charge pump 11 to increase the charge on capacitor 13.
  • a positive pulse applied to charge pump 12 causes a current drain from the capacitor 13 to charge pump 12 to decrease the charge on capacitor 13.
  • the frequency R is the same as frequency F the charge on capacitor 13 remains unchanged as the current output from charge pump 11 and the current drain to charge pump 12 are equivalent and effectively cancel one another.
  • a change in the feedback frequency F resulting from the switching of frequency divider 5 of Fig. 1 will, however, give rise to differences in the duration of the outputs from flip-flops 9 and 10.
  • An output pulse will be generated by flip-flop 10 before an output is generated by flip- lop 9.
  • the output from flip-flop 9 causes reset to zero for both outputs of flip-flops 9 and 10 by the action of AND gate 14.
  • the input pulse to charge pump 12 is therefore of longer duration than the input pulse to charge pump 11 causing an overall current drain from capacitor 13.
  • the feedback frequency F is changed to a frequency lower than the reference frequency R the input pulses to charge pump 11 will be of longer duration than the input pulses to charge pump 12.
  • the output from charge pump 11 will therefore predominate and the voltage on capacitor 13 will be increased.
  • the voltage across capacitor 13 is applied to a high impedance input of amplifier 8.
  • the output from amplifier 8 is applied to the base of loop filter 3 as a speed-up voltage for faster frequency acquisition by the VCO.
  • a circuit diagram of loop filter 3 is shown in Fig. 3 with capacitors Cl, C2 and C3 and resistors Rl and R2. As shown in Fig. 3, both input and output of loop filter 3 are balanced.
  • the balanced output from charge pump 2 is input to loop filter 3 at point 15 and the output from loop filter 3 at point 16 is applied to the frequency control input of the VCO 4 which is a balanced input.
  • the output from amplifier 8 is applied to the base of loop filter 3 at point 17.
  • charge pumps 11 and 12 remain inoperative until the synchronization input (sync) allows them to operate.
  • the synchronization input allows charge pumps 11 and 12 to operate for a specified time, i.e., within a gate period, the duration of the gate period being the duration of a single period of the lower of the two frequencies, the reference frequency and the feedback frequency.
  • the synchronization input is generated by a control cirsuit (not shown) which receives a request for frequency change from an external circuit and controls frequency divider 5.
  • the exemplary speed-up circuit has been found to provide improved lock times almost irrespective of the channel jump and direction, with greater flexibility in choice and design of the synthesizer.
  • the speed-up circuit can be implemented on silicon as an integral part of the synthesizer or can be fabricated as a separate circuit external to the synthesizer.
  • a further advantage of the invention is that once the voltage has been applied to the base of the loop filter there will be no loss of filter performance and the filter will retain the phase and gain margin as designed.
  • the channel locking on a synthesizer may be considered to consist of two parts: a frequency acquisition part and a phase acquisition part.
  • the speed-up circuit as described acts almost to achieve the frequency acquisition part thus giving rise to a significant improvement in lock times .

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A frequency synthesizer suitable for use with a radiotelephone has a voltage controlled oscillator (VCO) (4) in a phase locked loop (PLL). When the synthesizer is switched to a new frequency, a speed-up circuit operates and applies a voltage to the voltage control input of the VCO (4) such that the required frequency is acquired quickly by the VCO (4). The speed-up circuit has a time period difference detector (6) for measuring the time period difference between the reference and feedback frequencies of the PLL, a time-to-voltage converter (7) for obtaining a voltage proportional to the difference in period of the reference and feedback frequencies, and an amplifier (8) for amplifying the output of the converter (7). The output of the amplifier (8) is applied to the VCO (4) via a base of the loop filter (3) of the PLL.

Description

DESCRIPTION FREQUENCY SYNTHESIZERS
Technical Field
This invention relates to a frequency synthesizer for use, for example, in a communications receiver or transmitter such as a digital telephone.
Background Art
There exists a large number of publications relating to frequency synthesizers and the need for achieving short locking times in frequency synthesizers. Reference is made to our co-pending application GB 2 317 279 A.
A GSM (global system for mobile communication) telephone, for instance, may make use of a frequency synthesizer for switching between receive and transmit frequencies or for frequency hopping during either transmission or receiving. Such a frequency synthesizer will be required to hop over a 70 MHz bandwidth within one GSM time slot (570 microseconds).
Air interface specifications standards for mobile radiotelephones place a tight requirement on the design of frequency synthesizers in respect of lock time, phase noise and phase error. These parameters are closely linked and impose restrictions on the design. An improvement in lock time which does not force changes to other design parameters would be a valuable addition to the prior art . Such an improvement in lock time would also allow greater flexibility in the design process and. provide greater ease of manufacture.
Disclosure of the Invention
It is an object of the invention to provide improved lock times for frequency synthesizers without introducing adverse effects on other design parameters.
According to the invention there is provided a frequency synthesizer comprising a VCO (voltage controlled oscillator) in a phase locked loop, and a speed-up circuit, the speed-up circuit comprising a detector for detecting a difference in period between a reference frequency and a feedback signal frequency, and a circuit for generating a voltage proportional to the difference in period between the reference frequency and the feedback signal frequency, amplifying the voltage and applying the amplified voltage to a frequency control voltage input of the VCO.
Brief Description of the Drawings
Fig. 1 is a block diagram of a frequency synthesizer including a speed-up circuit;
Fig. 2 is a block diagram of the speed-up circuit; and
Fig. 3 is a circuit diagram of a loop filter.
Best mode for Carrying Out the Invention
An example of the invention will now be described with reference to the drawings in which like reference numerals identify identical elements. With reference to Fig. 1, a block diagram of a frequency synthesizer according a preferred embodiment of the present invention is shown and the synthesizer comprises a voltage controlled oscillator (VCO) in a phase locked loop (PLL) . The PLL has phase detector 1, charge pump 2, loop filter 3, VCO 4 and frequency divider 5 and operates to lock the feedback frequency F in phase with the reference signal R. In order to change to another channel, the frequency division ratio N of divider 5 is changed and the frequency of the feed back signal F also changes. The difference in phase between the two signals R and F fed to the phase detector 1 produces an output from phase detector 1 to the charge pump 2.
The output from phase detector 1 depends on the amount and direction of the difference in phase between the two signals R and F. The output from the charge pump 2 acts via loop filter 3 to change the frequency of the VCO. The output of VCO 4 fed back to the frequency divider 5 produces a change in the frequency of the feedback signal F and the PLL locks to the new frequency. This example as described so far above conforms to normal prior art practice.
The adaptive speed-up circuit is shown as in Fig. 1 and comprises time period difference detector 6, time-to- voltage converter 7 and amplifier 8. At the instant when a frequency change is requested a measurable time difference will exist between the period of the reference frequency R and the period of the feedback frequency F. The difference in the times of the periods of the frequencies R and F will be proportional to the change of frequency required. As the difference in time of the periods is proportional to the size of the frequency jump demanded then a measure of this time difference at the instant when a frequency change is requested will provide an indication of the channel which the synthesizer is seeking to acquire.
A time difference measurement of the periods of the frequencies R and F may therefore be converted to a voltage, the value of which will depend upon the frequency change required for the VCO. With reference to Figs. 1 and 2, the time difference measurement is made in detector 6 of Figs. 1 and 2 by means of the circuit shown in Fig. 2, infra. The outputs from period difference detector 6 are fed to time-to-voltage converter 7. The reference frequency R is input to D-type flip-flop (D-FF) 9 which gives an output when the amplitude of reference frequency R is positive. Similarly when the amplitude of the feedback frequency F is positive D-type flip-flop 10 gives an output. The AND gate 14 is connected across the outputs of flip-flops 9 and 10 and AND gate 14 resets the output lines of flip-flops 9 and 10 to zero when the outputs from flip-flops 9 and 10 are coincident.
When the frequency R is the same as frequency F, i.e., when the PLL is locked to that frequency, the frequency and duration of the output pulses from both flip-flops 9 and 10 are the same. The positive output pulses from flip-flops 9 and 10 are fed to charge pumps 11 and 12. A positive pulse applied to charge pump 11 causes a current to flow as an output from charge pump 11 to increase the charge on capacitor 13. A positive pulse applied to charge pump 12 causes a current drain from the capacitor 13 to charge pump 12 to decrease the charge on capacitor 13. When the frequency R is the same as frequency F the charge on capacitor 13 remains unchanged as the current output from charge pump 11 and the current drain to charge pump 12 are equivalent and effectively cancel one another.
A change in the feedback frequency F resulting from the switching of frequency divider 5 of Fig. 1 will, however, give rise to differences in the duration of the outputs from flip-flops 9 and 10. Consider an increase in the feedback frequency F such that the frequency F is a higher frequency than the reference frequency R. An output pulse will be generated by flip-flop 10 before an output is generated by flip- lop 9. The output from flip-flop 9 causes reset to zero for both outputs of flip-flops 9 and 10 by the action of AND gate 14.
The input pulse to charge pump 12 is therefore of longer duration than the input pulse to charge pump 11 causing an overall current drain from capacitor 13. Similarly when the feedback frequency F is changed to a frequency lower than the reference frequency R the input pulses to charge pump 11 will be of longer duration than the input pulses to charge pump 12. The output from charge pump 11 will therefore predominate and the voltage on capacitor 13 will be increased.
The voltage across capacitor 13 is applied to a high impedance input of amplifier 8. The output from amplifier 8 is applied to the base of loop filter 3 as a speed-up voltage for faster frequency acquisition by the VCO. A circuit diagram of loop filter 3 is shown in Fig. 3 with capacitors Cl, C2 and C3 and resistors Rl and R2. As shown in Fig. 3, both input and output of loop filter 3 are balanced. The balanced output from charge pump 2 is input to loop filter 3 at point 15 and the output from loop filter 3 at point 16 is applied to the frequency control input of the VCO 4 which is a balanced input. The output from amplifier 8 is applied to the base of loop filter 3 at point 17.
In order that the speed-up circuit is effective only following a frequency change demand, charge pumps 11 and 12 remain inoperative until the synchronization input (sync) allows them to operate. When a frequency change is demanded the synchronization input allows charge pumps 11 and 12 to operate for a specified time, i.e., within a gate period, the duration of the gate period being the duration of a single period of the lower of the two frequencies, the reference frequency and the feedback frequency. The synchronization input is generated by a control cirsuit (not shown) which receives a request for frequency change from an external circuit and controls frequency divider 5.
The exemplary speed-up circuit has been found to provide improved lock times almost irrespective of the channel jump and direction, with greater flexibility in choice and design of the synthesizer. The speed-up circuit can be implemented on silicon as an integral part of the synthesizer or can be fabricated as a separate circuit external to the synthesizer.
A further advantage of the invention is that once the voltage has been applied to the base of the loop filter there will be no loss of filter performance and the filter will retain the phase and gain margin as designed.
The channel locking on a synthesizer may be considered to consist of two parts: a frequency acquisition part and a phase acquisition part. The speed-up circuit as described acts almost to achieve the frequency acquisition part thus giving rise to a significant improvement in lock times .

Claims

1. A frequency synthesizer comprising: a VCO (voltage controlled oscillator) in a phase locked loop; and a speed-up circuit; the speed-up circuit comprising: a detector for detecting a difference in period between a reference frequency and a feedback signal frequency; and a circuit for generating a voltage proportional to the difference in period between the reference frequency and the feedback signal frequency, amplifying the voltage and applying the amplified voltage to a frequency control voltage input of the VCO.
2. A frequency synthesizer according to claim 1 wherein the circuit for generating a voltage proportional to the difference in period between the reference frequency and the feedback signal frequency comprises a first charge pump charging a capacitor when receiving a first output from the detector, and a second charge pump discharging the capacitor when receiving a second output from the detector, a voltage generated across the capacitor being the voltage proportional to the difference in period between the reference frequency and the feedback signal frequency.
3. A frequency synthesizer according to claim 2 wherein the charge pumps remain inoperative until a synchronization input allows the charge pumps to operate.
4. A frequency synthesizer according to claim 3 wherein the synchronization input allows the charge pumps to operate within a gate period.
5. A frequency synthesizer according to claim 4 wherein duration of the gate period is duration of a single period of a lower of two frequencies, the reference frequency and the feedback frequency.
6. A frequency synthesizer according to claim 1 wherein an output of the amplifier is applied to the frequency control voltage input of the VCO via a base of a loop filter.
7. A frequency synthesizer according to claim 1 wherein the detector for detecting a difference in period between the reference frequency and the feedback signal frequency comprises a reference frequency input to a first flip-flop circuit, a feedback signal frequency input to a second flip-flop circuit, and an AND gate reset across outputs of the first and second flip-flops.
8. A frequency synthesizer according to claim 7 wherein the flip-flops are D-type flip-flops.
9. A frequency synthesizer according to claim 7 wherein the circuit for generating a voltage proportional to the difference in period between the reference frequency and the feedback signal frequency comprises a first charge pump charging a capacitor when receiving a first output from the detector, and a second charge pump discharging the capacitor when receiving a second output from the detector, a voltage generated across the capacitor being the voltage proportional to the difference in period between the reference frequency and the feedback signal frequency.
10. A frequency synthesizer according to claim 9 wherein the charge pumps remain inoperative until a synchronization input allows the charge pumps to operate.
11. A frequency synthesizer according to claim 10 wherein the synchronization input allows the charge pumps to operate within a gate period.
12. A frequency synthesizer according to claim 11 wherein duration of the gate period is duration of a single period of a lower of two frequencies, the reference frequency and the feedback frequency.
13. A frequency synthesizer according to claim 7 wherein an output of the amplifier is applied to the frequency control voltage input of the VCO via a base of a loop filter.
14. A frequency synthesizer according to claim 1 wherein the speed-up circuit is implemented on silicon as an integral part of the frequency synthesizer.
15. A frequency synthesizer according to claim 7 wherein the speed-up circuit is implemented on silicon as an integral part of the frequency synthesizer.
PCT/JP1999/004713 1998-09-02 1999-08-31 Frequency synthesizers WO2000014882A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU54463/99A AU5446399A (en) 1998-09-02 1999-08-31 Frequency synthesizers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9818982.2 1998-09-02
GB9818982A GB2341285B (en) 1998-09-02 1998-09-02 Frequency synthesisers

Publications (1)

Publication Number Publication Date
WO2000014882A1 true WO2000014882A1 (en) 2000-03-16

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PCT/JP1999/004713 WO2000014882A1 (en) 1998-09-02 1999-08-31 Frequency synthesizers

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GB (1) GB2341285B (en)
WO (1) WO2000014882A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1170869A2 (en) * 2000-06-30 2002-01-09 Nokia Mobile Phones Ltd. Method and arrangement for setting a frequency
WO2003067762A1 (en) * 2002-02-07 2003-08-14 Nokia Corporation Synthesiser
WO2006100617A1 (en) 2005-03-23 2006-09-28 Nokia Corporation Operating a phase locked loop

Citations (4)

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Publication number Priority date Publication date Assignee Title
US3611175A (en) * 1970-03-26 1971-10-05 Sylvania Electric Prod Search circuit for frequency synthesizer
EP0458269A1 (en) * 1990-05-21 1991-11-27 Nec Corporation Phase-locked loop circuit
EP0579978A1 (en) * 1992-06-29 1994-01-26 Nec Corporation Frequency synthesizer
GB2317279A (en) * 1996-09-11 1998-03-18 Nec Technologies Frequency synthesisers

Family Cites Families (1)

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Publication number Priority date Publication date Assignee Title
JP2841693B2 (en) * 1990-04-19 1998-12-24 日本電気株式会社 PLL frequency synthesizer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611175A (en) * 1970-03-26 1971-10-05 Sylvania Electric Prod Search circuit for frequency synthesizer
EP0458269A1 (en) * 1990-05-21 1991-11-27 Nec Corporation Phase-locked loop circuit
EP0579978A1 (en) * 1992-06-29 1994-01-26 Nec Corporation Frequency synthesizer
GB2317279A (en) * 1996-09-11 1998-03-18 Nec Technologies Frequency synthesisers

Non-Patent Citations (1)

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Title
SEVENHANS J ET AL: "AN ANALOG RADIO FRONT-END CHIP SET FOR A 1.9GHZ MOBILE RADIO TELEPHONE APPLICATION", IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE., vol. 37, February 1994 (1994-02-01), IEEE INC. NEW YORK., US, pages 44-45,307, XP000507055, ISSN: 0193-6530 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1170869A2 (en) * 2000-06-30 2002-01-09 Nokia Mobile Phones Ltd. Method and arrangement for setting a frequency
EP1170869A3 (en) * 2000-06-30 2003-08-13 Nokia Corporation Method and arrangement for setting a frequency
WO2003067762A1 (en) * 2002-02-07 2003-08-14 Nokia Corporation Synthesiser
US7567132B2 (en) 2002-02-07 2009-07-28 Nokia Corporation Synthesizer
WO2006100617A1 (en) 2005-03-23 2006-09-28 Nokia Corporation Operating a phase locked loop
US7321267B2 (en) 2005-03-23 2008-01-22 Nokia Corporation Compensating capacitive dielectric absorption induced frequency error in a phase locked loop
EP3468041A1 (en) * 2005-03-23 2019-04-10 Nokia Technologies Oy Method of operating a phase locked loop and phase locked loop
EP3468041B1 (en) * 2005-03-23 2022-06-22 Nokia Technologies Oy Method of operating a phase locked loop and phase locked loop

Also Published As

Publication number Publication date
GB9818982D0 (en) 1998-10-21
GB2341285A (en) 2000-03-08
GB2341285B (en) 2001-12-19
AU5446399A (en) 2000-03-27

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