WO2000007237A1

WO2000007237A1 - METHOD OF MAKING HIGH PERFORMANCE MOSFET USING Ti-LINER TECHNIQUE

Info

Publication number: WO2000007237A1
Application number: PCT/US1999/002449
Authority: WO
Inventors: Mark I. Gardner; Derick J. Wristers; Daniel Kadosh
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1998-07-28
Filing date: 1999-02-05
Publication date: 2000-02-10

Abstract

A transistor (10) and a method of making the same are provided. The transistor (10) includes a substrate (12) and an insulating layer (46) on the substrate (12) that has an opening therein (62) extending at least to the substrate (12). A gate electrode (16) is positioned in the opening (62). A first source/drain region (24) and a second source/drain region (26) are positioned in spaced-apart relation in the substrate (12). A metal oxide gate dielectric layer (14) in positioned between the gate electrode (16) and the substrate (12). The gate electrode (16) may be composed of a high temperature resistant material, such as tungsten. The gate dielectric layer (14) may be composed of a high K material with a thin equivalent thickness of oxide, such as TiO2.

Description

METHOD OF MAKING HIGH PERFORMANCE MOSFET USING Ti-LINER TECHNIQUE

1. Technical Field

This invention relates generally to semiconductor processing, and more particularly, to an integrated circuit transistor with an integrated metal gate electrode and high K. gate dielectric layer, and to a method of making the same.

2. Background Art

Insulated gate field effect transistors ("IGFE '), such as metal oxide semiconductor field effect transistors ("MOSFET"), are some of the most commonly used electronic components in modem integrated circuits. Embedded controllers, microprocessors, analog-to-digital converters, and many other types of devices now routinely include millions of field effect transistors. The dramatic proliferation of field effect transistors in integrated circuit design can be traced to their high switching speeds, potentially low power dissipation, and adaptability to semiconductor process scaling.

A typical field effect transistor implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.

In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. The first implant is performed self-aligned to the gate electrode to establish lightly doped drain ("LDD") structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode by depositing and anisotropically etching a dielectric material, such as silicon dioxide. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.

Early MOS integrated circuits were implemented as p-channel enhancement mode devices using aluminum as the gate electrode material. Aluminum had the advantages of relatively low resistivity and material cost. Furthermore, there was already a large body of manufacturing experience with aluminum in the chip industry developed from bipolar integrated circuit processing.

A later process innovation that is still widely used today, involves the use of heavily doped polysilicon as a gate electrode material in place of aluminum. The switch to polysilicon as a gate electrode material was the result of certain disadvantages associated with aluminum in early fabrication technologies. In conventional semiconductor fabrication processing, aluminum must be deposited following completion of all high temperature process steps (including drive-in of the source and drain regions). As a result, an aluminum gate electrode must ordinarily be separately aligned to the source and drain. This alignment procedure can adversely affect both packing density and parasitic overlap capacitances between the gate and source/drain regions. In contrast, polysilicon with its much higher melting point, can be deposited prior to source and drain formation and therefore provide for self-aligned gate processing. Furthermore, the high temperature capability of polysilicon is routinely exploited to enable interlevel dielectric layers to be applied to provide multiple metallization layers with improved planarity.

Despite the several advantages of polysilicon over aluminum as a gate electrode material, polysilicon has the disadvantage of a much higher resistivity as compared to aluminum. Higher resistivity translates into higher values of interconnect line resistance that can lead to undesirably long RC time constants and DC voltage variations within VLSI or ULSI circuits. The development of polycide films on top of polysilicon layers has alleviated some of the resistivity shortcomings of polysilicon gate electrodes. However, the resistivity of polysilicon gate electrodes in conventional MOS integrated circuit processing still presents a potential impediment to successful process scaling through reductions in the operating voltages of VLSI and ULSI devices.

Another disadvantage of polysilicon as a gate electrode material is polysilicon depletion. In p-channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion.

In addition to the drawbacks associated with conventional gate electrode manufacture, the gate dielectric formation aspects of conventional transistor fabrication present certain disadvantages. Silicon dioxide gate oxide layers are made as thin as possible to maximize drive current and to control short channel effects. The requirement for very thin gate oxide layers has become particularly important in sub-micron processing where process scaling has dramatically increased the potential for short channel effects. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. To begin with, very thin silicon dioxide layers have been historically difficult to fabricate with a consistent thickness across a given wafer, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot-carrier-injection degradation increases. Hot carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure. The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages. DISCLOSURE OF INVENTION

In accordance with one aspect of the present invention, a method of fabricating a transistor on a substrate is provided. The method includes the steps of forming a doped region in the substrate and forming a first insulating layer on the substrate. An opening is formed through the first insulating layer and the doped region that separates the doped region into first and second source/drain regions. A second insulating layer is formed in the opening and a gate electrode is formed in the opening. The gate electrode is insulated from the substrate by the second insulating layer.

In accordance with another aspect of the present invention, a method of fabricating a resistor on a substrate is provided. The method includes the steps of forming a first insulating layer on the substrate and forming a first opening and a second opening in the first insulating layer. The first and second openings extend at least to the substrate and respectively define first and second pluralities of sidewalls. A second insulating layer is formed on the first and second pluralities of sidewalls and a first ohmic contact is formed in the first opening and a second ohmic contact is formed in the second opening.

In accordance with another aspect of the present invention, an integrated circuit resistor is provided. The resistor includes a substrate, a first insulating layer on the substrate, and a first ohmic contact connected to the substrate. A second ohmic contact is connected to the substrate and a second insulating layer is positioned between each of the first and second ohmic contacts and the first insulating layer.

In accordance with another aspect of the present invention, a transistor is provided. The transistor includes a substrate and an insulating layer on the substrate and that has an opening therein extending at least to the substrate. A gate electrode is positioned in the opening. A first source/drain region and a second source/drain region are positioned in spaced-apart relation in the substrate and a metal oxide gate dielectric layer is positioned between the gate electrode and the substrate.

In accordance with another aspect of the present invention, an integrated circuit is provided. The integrated circuit includes a substrate and a first insulating layer on the substrate and that has an opening therein extending at least to the substrate. A first transistor is provided that has a first gate electrode positioned in the opening, first and second source/drain regions in the substrate in spaced-apart relation to define a first channel region, and a metal oxide gate dielectric layer positioned between the first gate electrode and the substrate. A second transistor is provided that has a gate dielectric layer on the substrate, a second gate electrode on the gate dielectric layer, and a third source/drain region in the substrate in spaced-apart relation to the first source/drain region to define a second channel region.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a cross-sectional view of an exemplary embodiment of first and second transistors in accordance with the present invention;

FIG. 2 is a cross-sectional view like FIG. 1 depicting formation of one of the two transistors in accordance with the present invention; FIG. 3 is a cross-sectional view like FIG. 1 following application of an interlevel dielectric layer and definition of an opening for the second transistor in accordance with the present invention;

FIG. 4 is a cross-sectional view like FIG. 3 depicting an etch of a doped region of the substrate in accordance with the present invention; FIG. 5 is a cross-sectional view like FIG. 4 depicting formation of a high K insulating layer in accordance with the present invention;

FIG. 6 is a cross-sectional view like FIG. 5 depicting formation of a gate electrode for the second transistor in accordance with the present invention;

FIG. 7 is a cross-sectional view like FIG. 3 depicting an alternate exemplary process flow excluding the first transistor in accordance with the present invention;

FIG. 8 is a cross-sectional view like FIG. 1 of an exemplary embodiment of an integrated circuit resistor in accordance with the present invention; and

FIG. 9 is a cross-sectional view depicting the initial formation of the resistor shown in FIG. 8 in accordance with the present invention. MODES FOR CARRYING OUT THE INVENTION

In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to FIG. 1, there is shown a cross-sectional view of an exemplary embodiment of an integrated circuit transistor 10 that is formed on a semiconductor substrate 12. The semiconductor substrate 12 may be composed of n-doped, or p-doped silicon, silicon-on-insulator, or other suitable substrate materials. The transistor 10 includes an insulating or gate dielectric layer 14 that is formed on the substrate 12 and a gate electrode 16 that is formed on the first insulating layer 14. The first insulating layer 14 is formed with a generally channel or U-shaped cross-section that establishes parallel, laterally spaced vertical sidewalls 18 and 20. The gate electrode 16 is positioned between the opposing sidewalls 18 and 20. An adhesion layer 22 that has the same general cross-sectional shape as the first insulating layer 14 is positioned between the gate electrode 16 and the first insulating layer 14. First and second source/drain regions 24 and 26 are formed in the substrate 12 and separated laterally by the first insulating layer 14 to define a channel region 28 in the substrate 12 beneath the gate electrode 16. The phrase

"source/drain region(s)" is used herein to describe a region that may serve as either a source or a drain. The skilled artisan will appreciate that a source/drain region may function as a source or a drain depending upon whether it is connected to V_ss or V_DD during metallization.

A second transistor 30 is formed on the substrate 12 in spaced-apart relation to the transistor 10. The second transistor 30 includes a gate dielectric layer 32 formed on the substrate 12 and a gate electrode 34 formed on the gate dielectric layer 32. The gate dielectric layer 32 and the gate electrode 34 are sandwiched between opposing dielectric sidewall spacers 36 and 38. The transistor 30 shares the source/drain region 24 with the transistor 10 and is provided with an additional source/drain region 40 that is separated laterally in the substrate 12 from the source/drain region 24 to define a channel region 42 in the substrate 12 beneath the gate dielectric layer 32. The exposed portions of the substrate 12 may be coated to facilitate enhanced ohmic contact with the source/drain regions 24, 26, and 40. In this regard, a suicide layer 44 is formed on the substrate 12 over the source/drain regions 24, 26, and 40.

The transistors 10 and 30 are covered by an interlevel dielectric layer 46. Vias are formed through the interlevel dielectric layer 46 and filled with contact plugs 48, 50, 52, 54, and 56 to establish ohmic contact, respectively, with the source/drain region 40, the gate electrode 34, the source/drain region 24, the gate electrode 16, and the source/drain region 26.

An exemplary process flow for forming the transistor 10 and the transistor 30 may be understood by referring now to FIGS. 2, 3, 4, 5, and 6, and initially to FIG. 2. The process will be described in the context of n-channel devices. However, the skilled artisan will appreciate that the transistors may be implemented as n- channel, p-channel or another type of device. The second insulating layer 32 and the gate electrode 34 are initially deposited as layers on the substrate 12 and subsequently masked and anisotropically etched to yield the layer 32 and gate electrode 34 shown in FIG. 2. The gate dielectric layer is advantageously composed of SiO,, or other suitable gate oxide material. The gate dielectric layer 32 may be 20 to 50 A thick and is advantageously about 30 A thick. If Si0₂ is selected, the gate dielectric layer 32 may be grown by exposing the substrate 12 to an oxygen containing ambient at approximately 800 to 1050°C for approximately 10 to 60 seconds in a rapid thermal anneal process ("RTA"), or for approximately 5 to 20 minutes in a diffusion tube process. A nitrogen bearing species, such as NO or N₂0, may be added to the ambient to infuse nitrogen into the layer 32 to inhibit polysilicon depletion and reduce hot carrier effects. The gate electrode 34 may be composed of a variety of conducting materials, such as, for example, amorphous silicon or polysilicon. In an exemplary embodiment, the gate electrode 34 is polysilicon. Well known techniques for applying polysilicon, such as CVD, may be used to deposit the gate electrode layer 34. In an exemplary embodiment, the polysilicon is deposited at or above about 625 °C to a thickness of 1000 to 2000 A, and advantageously to about 1300 A. Following definition of the second insulating layer 32 and the gate electrode 34, the upper regions of the substrate 12 are doped with a dopant specie to establish the source/drain region 40, and a doped region 58 that are generally self-aligned to the layer 32 and the gate electrode 34. The doped region 58 will be partitioned into the source/drain region 24 and the source/drain region 26 shown in FIG. 1 through later processing. The source/drain region 40 and the doped region 58 may be established in the substrate by ion implantation or diffusion as desired. In an exemplary embodiment, the source/drain region 40 and the doped region 58 are formed by implanting an n-type dopant, such as arsenic. The dosage may be about 5E13 to 8E14 ions/cm² and is advantageously about 4E14 ions/cm² The energy may be about 5 to 30 keV and is advantageously about 20 keV. The implant angle is advantageously 0°. If desired, a double implant may be used to establish lightly doped drain ("LDD") structures (not shown) adjacent the gate 34. The energy and dosage of the implant(s) will depend upon the dopant type.

Following establishment of the source/drain region 40 and the doped region 58, the dielectric sidewall spacers 36 and 38 may be formed. The spacers 36 and 38 may be composed of a suitable sidewall spacer material, such as, for example, Si0₂, Si₃N₄, or similar suitable sidewall spacer materials. The spacers 36 and 38 may be fabricated by forming a layer of the selected material by oxidation, CVD, or other technique, followed by anisotropic etching to leave the spacers 36 and 38. The spacers 36 and 38 are advantageously SiO_:, may be 200 to 800 A wide and are advantageously about 500 A wide.

The process of forming the spacers 36 and 38 will typically incorporate a high temperature (> 1000 °C) step that will serve to anneal and activate drive the source/drain region 40 and the doped region 58, and set the position of the junction 59 of the doped region 58 and the length of the channel 42. Subsequent heating will result in some shifting of the channel length and position of the junction 59.

The silicide layer 44 may be formed by depositing a silicide forming material, such as titanium, cobalt or like materials on the substrate 12, and heating the material to initiate a silicide forming reaction. The material may be annealed in an inert ambient at approximately 650 to 700 °C for approximately 30 to 60 seconds in a

RTA. The substrate 12 is then subjected to RCA cleaning to remove any unreacted metal and leave the layer 44. A final anneal is performed at approximately 700 to 800 °C for approximately 30 to 60 seconds to stabilize the silicide. The resulting silicide layer 44 may have a thickness of 250 to 500 A and advantageously about 375

A. Referring now to FIG. 3, the interlevel dielectric layer 46 is formed on the substrate 12. The layer 46 may be composed of silicon dioxide, tetra-ethyl-ortho-silicate ("TEOS"), or other suitable interlevel dielectric materials. If TEOS is selected, the layer 46 may be formed by CVD or like techniques. The interlevel dielectric layer 46 may be about 0.75 μm to 1.2 μm thick and is advantageously about 1.0 μm thick. Follow deposition, the layer 46 is planarized to the desired thickness by chemical-mechanical-polishing ("CMP") or other planarization techniques.

The interlevel dielectric layer 46 is masked with photoresist 60. The photoresist is patterned, i.e., exposed and developed to expose a portion of the interlevel dielectric layer 46 which is then etched back to the substrate 12 to form a via or opening 62. The formation of the opening 62 is advantageously by an anisotropic etch process, such as reactive ion etching, chemical plasma etching, or other like anisotropic etching techniques. Referring now to FIGS. 3 and 4, the upper region of the substrate 12 exposed by the opening 62 is anisotropically etched to slightly below the junction 59 of the doped region 58. The etch partitions the doped region 58 into the now established source/drain region 24 and the source/drain region 26. The etch of the substrate 12 may be accomplished by reactive ion etching, chemical plasma etching or other suitable anisotropic etching techniques. Referring now to FIGS. 4 and 5, the photoresist 60 is stripped and the first insulating layer 14 is formed in the opening 62. The first insulating layer 14 is advantageously composed of a high dielectric constant ("K") material that exhibits both a relatively thin equivalent thickness of oxide ("t_ox") and resistance to dielectric breakdown and hot-carrier degradation. Exemplary materials include TiO-, Ta₂0₅ or like materials. The layer 14 may be formed by depositing a layer of material that may form a high K metal oxide material. In an exemplary embodiment, the layer 14 is initially established by depositing titanium by chemical vapor deposition ("CVD") or other like techniques. The deposition process establishes a conformal layer of titanium on the interlevel dielectric layer 46 and establishes the layer 14 in the opening 62 including the vertical sidewalls 18 and 20. The layer 14 may be about 20 to 200 A thick and is advantageously about 120 A thick. The layer of oxide forming material is then converted to an oxide by annealing in an oxygen containing ambient. The anneal may be conducted under a variety of conditions. For example, a rapid thermal anneal

("RTA") may be conducted with an ambient of about 50 % O- and a like percentage of an inert gas, such as argon, at about 850 to 1050°C for about 15 to 30 seconds. The concentration of the inert gas, such as argon, may be varied to control the oxidation rate of the titanium to a desired level. Alternatively, the anneal may be accomplished in a diffusion tube furnace process at about 700 to 800°C for about 15 minutes. A nitrogen bearing specie, such as NO, N₂, N,0, or other specie may be mixed into the anneal ambient to establish a nitrogen dopant concentration in the layer 14. For example, the ambient may contain 0₂ at about 50% concentration, 10% to 40% argon, and a balance of a nitrogen bearing species in the aforementioned RTA process. Incorporation of nitrogen into the layer 14 enhances the resistance of the layer 14 to the diffusion of material therethrough into the substrate 12.

The conversion of the titanium to titanium dioxide yields an insulating layer 14 with an equivalent t_ox of approximately 5 to 25 A. The result is a gate dielectric layer that exhibits not only a very thin equivalent t_ox, but also better resistance to dielectric breakdown and hot-carrier degradation than conventional gate oxide. The mathematical relationship between the targeted equivalent t_ox for the layer 14 and the actual thickness of the

Ti0₂ layer 14 is given by the following equation:

Kτiθι • [Equivalent tox) = [Thickness ofTiOi Layer) _{E uation j}

KsiOi

where K_Ti02and _si02are the dielectric constants for Ti0₂ and SiO,. Note that the equation is expressed as an approximation since Ti0₂ and Si0₂ have a range of dielectric constants instead of a single value. For example, TiO, has a dielectric constant that may range from about 14 to 1 10.

If Ta^ is selected, the same general regimen may be used to achieve the same thin equivalent t_ox. The requisite thickness of the layer 14 of Ta ^ layer will be given by the above equation.

The application of the layer 14 has been described in the context of a metal deposition followed by oxidation. However, the skilled artisan will appreciate that other techniques may be used. For example, the layer 14 may be applied as an oxide, e.g., TiO, by CVD, sputter or like techniques.

It is anticipated that the high temperature anneal of the layer 14 will drive the depth of the junctions 59 of the source/drain regions 24 and 26 to below the interface between the substrate 12 and the first insulating layer 14. If desired, a second anneal step may be performed to drive the junctions of the source/drain regions 24 and 26 to a deeper depth. Referring now to FIG. 6, the adhesion layer 22 is formed on the first insulating layer 14. The adhesion layer 22 is deposited as a conformal layer that coats the vertical sidewalls 18 and 20 and the bottom of first insulating layer 14. The adhesion layer 22 is designed to facilitate adhesion of the later deposited gate electrode 16. In this regard, the adhesion layer is advantageously composed of titanium nitride. The layer 22 may be deposited by CVD or other suitable TiN deposition techniques. Alternatively, the layer 22 may be composed of titanium, a combination of titanium and tungsten, a combination of titanium and TiN, or other suitable adhesion layer materials. The skilled artisan will appreciate that the layer 22 may be unnecessary where the material selected for the gate electrode 16 exhibits good adhesion to the insulating layer 14.

Following formation of the adhesion layer 22, the gate electrode 16 is formed in the opening 62. The gate electrode 16 may be composed of a variety of conducting materials, such as tungsten, aluminum, polysilicon, or like materials. In an exemplary embodiment, the gate electrode 16 is composed of tungsten and may be deposited by CVD in a silane reduction process or other suitable tungsten CVD deposition process. The CVD formation of the adhesion layer 22 and the gate electrode 16 will conformally coat the interlevel dielectric layer 46. Accordingly, the layer 14, the layer 22, and the material used to form the gate electrode 16 are advantageously planarized by chemical mechanical polishing ("CMP"), by etchback planarization, or other suitable planarization techniques to remove the portions of the layer 14, the layer 22, and the material used to form the gate electrode 16 previously projecting above the upper surface of the interlevel dielectric layer 46. A tungsten gate electrode 16 has the advantages of resistance to high temperature degradation and the elimination of polysilicon depletion that is frequently associated with polysilicon gate electrodes in p-channel devices. Accordingly, a tungsten gate electrode 16 enables greater flexibility in the thermal budgeting of the overall process flow.

Referring now to FIGS. 1 and 6, the interlevel dielectric layer 46 may be thickened by thermal oxidation, CVD, or other techniques, and the contact plugs 48, 50, 52, 54, and 56 formed by etching openings through the interlevel dielectric layer 46 and forming the contact plugs 48, 50, 52, 54, and 56. The plugs 48, 50, 52, 54, and 56 may be composed of tungsten, polysilicon, aluminum, or other suitable conducting materials. In an exemplary embodiment, the plugs 48, 50, 52, 54, and 56, are advantageously composed of tungsten and may be deposited by CVD using the same or a similar type of silane reduction reaction used to deposit the gate electrode 16. Each of the plugs 48, 50, 52, 54, and 56, will normally be lined with an adhesion layer, like the layer 22, that is not shown in FIG. 1 for simplicity of illustration.

In an alternate exemplary process flow, the process of fabricating the transistor 10 may be divorced from the fabrication of the transistor 30. For example, as shown in FIG. 7, the doped region 58 may be established in the substrate 12 by ion implantation or diffusion as generally described above. The interlevel dielectric layer 46 may then be applied, masked with photoresist 60, and etched to establish the opening 62 all as generally described above. The substrate 12 may then be processed as described above and depicted in FIGS. 4, 5, and 6, albeit without the presence of the transistor 30. An alternate embodiment incorporating a high K layer into an integrated circuit resistor may be understood by referring now to FIGS. 8 and 9. FIG. 8 depicts a cross-sectional view of an exemplary embodiment of an integrated circuit resistor 64. The resistor 64 includes ohmic contacts 66 and 68 formed in spaced-apart openings 70 and 72. The openings 70 and 72 extend at least through the interlevel dielectric layer 46 at least to the substrate 12, and may extend down into the substrate 12 as shown. Each of the ohmic contacts 66 and 68 includes a conducting plug 74, the adhesion layer 22 and the insulating layer 14 configured generally like the gate electrode 16-insulating layer 14 combination shown in FIG. 1. However, note that the bottom of the layer 14 for each contact 66 and 68 is eliminated to enable ohmic contact between the adhesion layer 22 of each contact 66 and 68 and the substrate 12. An exemplary process flow for forming the resistor 64 may be understood by referring now also to FIG. 9. As shown in FIG. 9, the openings 70 and 72 may be formed in the interlevel dielectric layer 46 and filled with the insulating layer 14. The formation of the openings 70 and 72 will define respective pluralities of sidewalls 76 and 78. The number of given sidewalls will depend on the geometry of the openings 70 and 72. The bottom of the layer 14 in each opening 70 and 72 may be etched to expose the substrate 12. The adhesion layer 22 and the plugs 74 may then be fabricated as generally described above in conjunction with the gate electrode 16. If desired, the resistance of the resistor 64 may be manipulated by doping the region 80 of the substrate 12 between the contacts 66 and 68 via ion implantation as shown or via diffusion.

The resistor 64 may be integrated with a transistor or other component. For example, and as shown in FIG. 8, the resistor 64 is connected to the source/drain region 26 of the transistor 10. The electrical pathway is from the contact 66 through the substrate 12 to the source/drain region 26.

Reference herein has been made to forming various openings in the interlevel dielectric layer 46 by masking and etching the layer 46. However, it should be understood that an opening may be established in the layer 46 by first establishing a structure on the substrate 12 by appropriate masking and etching, such as the combined gate electrode 16, adhesion layer 22 and insulating layer 14, and subsequently forming the layer 46 on either side of the structure. In either case, the structure and the layer 46 are integrated.

The process in accordance with the present invention yields a transistor that integrates a high K gate dielectric and a high temperature capable gate electrode with good conductivity. A thin equivalent thickness of oxide is achieved with resistance to dielectric breakdown and hot-carrier degradation. While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.

Claims

CLAIMSWhat is claimed is:

1. A method of fabricating a transistor ( 10) on a substrate ( 12), comprising the steps of: forming a doped region (58) in the substrate (12); forming a first insulating layer (46) on the substrate (12); forming an opening (62) through the first insulating layer (46) and the doped region (58), the opening

(62) separating the doped region (58) into first and second source/drain regions (24), (26); forming a second insulating layer ( 14) in the opening (62); and forming a gate electrode ( 16) in the opening (62), the gate electrode ( 16) being insulated from the substrate (12) by the second insulating layer (14).

2. The method of claim 1 , wherein the step of forming the second insulating layer comprises applying a layer of Ta^.

3. The method of claim 1 , wherein the step of forming the gate electrode comprises depositing tungsten in the opening.

4. A method of fabricating a resistor on a substrate, characterized in that the method comprises: forming a first insulating layer (46) on the substrate (12); forming a first opening (70) and a second opening (72) in the first insulating layer 46, the first and second openings (70), (72) extending at least to the substrate (12) and respectively defining first and second pluralities of sidewalls (76), (78); forming a second insulating layer (14) on the first and second pluralities of sidewalls (76), (78); and forming a first ohmic contact (66) in the first opening (70) and a second ohmic contact (68) in the second opening (72).

5. The method of claim 4, wherein the step of forming the second insulating layer comprises applying a layer of Ta^.

6. The method of claims 2 or 5, wherein the step forming a layer of Ta₂0, comprises depositing tantalum and substantially converting the deposited tantalum to Ta₂O_s by thermal oxidation.

7. The method of claims 2 or 5, wherein the step of applying a layer of Ta- i comprises applying Ta^ by chemical vapor deposition.

8. The method of claim 4, wherein the step of forming the first and second ohmic contacts comprises depositing tungsten in the first and second openings.

9. The method of claims 1 or 4, wherein the step of forming the first insulating layer comprises forming a layer of TEOS.

10. The method of claim 4, comprising the step of doping the substrate between the first and second openings to manipulate the resistance of the substrate between the first and second ohmic contacts.

1 1. An integrated circuit resistor (64), comprising: a substrate (12); a first insulating layer (46) on the substrate (12); a first ohmic contact (66) connected to the substrate ( 12); a second ohmic contact (68) connected to the substrate; and a second insulating layer (14) positioned between each of the first and second ohmic contacts (66), (68) and the first insulating layer (46).

12. The integrated circuit resistor of claim 1 1 , wherein the second insulating layer comprises Ta₂0₅.

13. The integrated circuit resistor of claim 1 1, wherein the first and second ohmic contacts comprise tungsten plugs.

14. The integrated circuit resistor of claim 1 1 , comprising a transistor connected thereto and having first and second source/drain regions and a gate electrode.

15. A transistor (10), comprising: a substrate (12); an insulating layer (46) on the substrate (12) and having an opening (62) therein extending at least to the substrate (12); a gate electrode (16) positioned in the opening (62); a first source/drain region (24) and a second source/drain region (26) positioned in spaced-apart relation in the substrate (12); and a metal oxide gate dielectric layer (14) positioned between the gate electrode (16) and the substrate

(12).

16. The transistor of claim 15, wherein the metal oxide gate dielectric layer comprises Ta₂O_s.

17. The transistor of claim 15, wherein the gate electrode is composed of tungsten.

18. The transistor of claim 15, comprising a resistor connected thereto and having a first ohmic contact and a second ohmic contact connected to the substrate, the second insulating layer being positioned between each of the first and second ohmic contacts and the first insulating layer.

19. An integrated circuit, comprising: a substrate (12); a first insulating layer (46) on the substrate (12) and having an opening therein (62) extending at least to the substrate (12); a first transistor (10) having a first gate electrode ( 16) positioned in the opening (62), first and second source/drain regions (24), (26) in the substrate in spaced-apart relation to define a first channel region (28), and a metal oxide gate dielectric layer (14) positioned between the first gate electrode (16) and the substrate (12); and a second transistor (30) having a gate dielectric layer (32) on the substrate (12), a second gate electrode (34) on the gate dielectric layer (32), and a third source/drain region (40) in the substrate (12) in spaced-apart relation to the first source/drain region (24) to define a second channel region

(42).

20. The integrated circuit of claim 19, wherein the metal oxide gate dielectric layer comprises Ta^.

21. The integrated circuit of claim 19, wherein the gate electrode is composed of tungsten.