WO2000004502A1 - Traitement graphique pour une manipulation efficace d'un polygone - Google Patents

Traitement graphique pour une manipulation efficace d'un polygone Download PDF

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Publication number
WO2000004502A1
WO2000004502A1 PCT/US1999/016080 US9916080W WO0004502A1 WO 2000004502 A1 WO2000004502 A1 WO 2000004502A1 US 9916080 W US9916080 W US 9916080W WO 0004502 A1 WO0004502 A1 WO 0004502A1
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WO
WIPO (PCT)
Prior art keywords
vertex
vertices
locations
base
data
Prior art date
Application number
PCT/US1999/016080
Other languages
English (en)
Inventor
William Lazenby
Dale Kirkland
Original Assignee
Intergraph Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intergraph Corporation filed Critical Intergraph Corporation
Publication of WO2000004502A1 publication Critical patent/WO2000004502A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/50—Lighting effects
    • G06T15/80—Shading

Definitions

  • the invention generally relates to computer systems and, more particularly, the invention relates to processing graphics request data for display on a computer display device.
  • Three dimensional graphics request data commonly is processed in a computer system as a plurality of polygons having vertices.
  • Each of the vertices has associated attribute data (e.g., color, transparency, depth, etc.) that is utilized to rasterize pixels on a computer display device.
  • Items to be displayed commonly are in the form of a "T-fan.”
  • a T-fan is a polygon having more than three vertices such as, for example, five vertices.
  • Various techniques have been utilized to process T-fan shaped items.
  • a method and graphics accelerator that processes a polygon having N vertices utilizes a single vertex buffer location for storing data for a single base vertex of the polygon while the polygon is processed.
  • the method and graphics processor first designates one of the vertices of the polygon to be the base vertex, and then defines N-2 different triangles by each of the vertices of the polygon. Each of the N-2 triangles is defined by the base vertex and two of the N vertices other than the base vertex.
  • a buffer is provided for storing the vertex data while the polygon is being processed.
  • the buffer includes a selected number of vertex locations each for storing vertex data for one vertex. The selected number is less than N.
  • the base vertex data is stored in the first vertex location in the buffer.
  • the base vertex data preferably is retrieved from the first vertex location each time one of the N-2 triangles is processed.
  • the base vertex data is stored in the first vertex location until each of the N-2 triangles is processed.
  • the first vertex location then may be utilized for storing other data after each of the triangles is processed.
  • each of the N vertices except the base vertex defines a set of vertices
  • the buffer includes a set of vertex locations other than the first vertex location.
  • the graphics accelerator and method further process each of the vertices in the set of vertices in the set of vertex locations.
  • the set of vertices is processed in the set of vertex locations in a round robin manner.
  • the set of vertices includes N-1 vertices and the set of vertex locations includes fewer than N-1 vertex locations. In such embodiments, selected vertices in the set of vertex locations are overwritten when each of the other vertex locations in the set of vertex locations is filled with vertex data for other vertices.
  • a modulo counter is utilized to perform a round-robin method of processing and storing vertex data.
  • the polygon is a T-fan.
  • Figure 1 schematically shows a portion of an exemplary computer system on which preferred embodiments of the invention may be implemented.
  • Figure 2 schematically shows a preferred graphics accelerator that may be utilized in accordance with preferred embodiments of the invention.
  • Figure 3A schematically shows a preferred embodiment of a geometry accelerator stage shown in Figure 2.
  • Figure 3B schematically shows an alternate embodiment of a geometry accelerator stage shown in Figure 2.
  • Figure 4 shows a preferred header for sending data to the rasterization stage from the geometry accelerator stage in the graphics accelerator shown in Figure 2.
  • Figure 5 A shows an exemplary T-fan.
  • Figure 5B shows a processed exemplary T-fan that may be processed in accordance with preferred embodiments of the invention.
  • Figures 5C and 5D show exemplary primitives.
  • Figure 1 shows a portion of an exemplary computer system 100 on which preferred embodiments of the invention may be implemented.
  • the computer system 100 includes a host processor 104 (i.e., a central processing unit) for executing application level programs and system functions, volatile host memory 102 for short term data storage (i.e., random access memory), a graphics accelerator 106 for processing graphics request code in accord with preferred embodiments of the invention (see Figure 4), a display device 108 for displaying the graphics request code processed by the accelerator 106, and a bus 110 coupling all of the prior noted elements of the system 100.
  • a host processor 104 i.e., a central processing unit
  • volatile host memory 102 for short term data storage (i.e., random access memory)
  • graphics accelerator 106 for processing graphics request code in accord with preferred embodiments of the invention (see Figure 4)
  • a display device 108 for displaying the graphics request code processed by the accelerator 106
  • a bus 110 coupling all of the prior noted elements of the system 100.
  • the graphics accelerator 106 preferably utilizes any well known graphics processing application program interface such as, for example, the OPENGLTM application program interface (available from Silicon Graphics, Inc. of Mountain View, California) for processing three dimensional ("3D") and two dimensional ("2D") graphical request code.
  • the host processor 104 executes a graphical drawing application program such as, for example, the PLANT DESIGN SYSTEMTM drawing program, available from Intergraph Corporation of Huntsville, Alabama.
  • the graphics accelerator 106 includes a double buffered frame buffer 200 (i.e., having a back buffer and a front buffer) for storing the processed graphics request code in accordance with the OPENGLTM interface.
  • the graphics accelerator 106 also preferably includes a geometry accelerator 202 for performing geometry operations that commonly are executed in graphics processing, a rasterizer 204 for rasterizing pixels on the display device 108, and a resolver 206 for storing data in the frame buffer 200 and transmitting data from the frame buffer 200 to the display device
  • the graphics accelerator 106 preferably is adapted to process both 2D and 3D graphical data.
  • the graphics accelerator 106 see, for example, copending patent application entitled “Wide Instruction Word Graphics Processor”, filed on even date herewith and naming Vernon Brethour, Gary Shelton, William Lazenby, and Dale Kirkland as inventors, the disclosure of which is incorporated herein, in its entirety, by reference.
  • Figure 3 A schematically shows a preferred embodiment of the geometry accelerator stage 202 shown in Figure 2.
  • the geometry accelerator stage 202 processes graphics primitives, which are two-dimensional surfaces such as points, lines, and polygons that are combined in 2D and 3D space to create 2D and 3D objects.
  • Each endpoint (i.e., comer) of a primitive is called a vertex.
  • Figure 5C shows some exemplary primitives including a line, a triangle, and a quadrilateral.
  • a line has two vertices
  • a triangle has three vertices
  • a quadrilateral has four vertices.
  • More complex primitives such as strip primitives may be formed by using primitives as sub-elements, or sub- primitives.
  • Figure 5D shows exemplary strip primitives, including a line strip (Lstrip), a triangle strip (Tstrip), and a quadrilateral strip (Qstrip).
  • Lstrips are composed of sub- primitives that are Lines
  • Tstrips are composed of sub-primitives that are Triangles
  • Qstrips are composed of sub-primitives that are Quadrilaterals.
  • the geometry accelerator 202 processes these and other primitives. More particularly, selected elements of the geometry accelerator 202 are shown for processing a polygon having more than three vertices.
  • the geometry accelerator 202 includes an input buffer 320 for storing the input vertex data.
  • the input buffer 320 includes four vertex locations for storing all of the necessary vertex data for four vertices.
  • data is color data, transparency data, depth data, and other commonly known 2D or 3D graphical data.
  • such data may be represented by a plurality of numbers (e.g., thirty-two bit words) such as, for example, forty-eight numbers.
  • each of the vertex locations in the input buffer preferably includes an array of forty-eight thirty-two bit words.
  • the geometry accelerator 202 also includes a geometry accelerator processor 330 ("processor") for executing geometry and other known math functions on the vertex data.
  • the math functions may include multiplication operations, addition operations, and reciprocal operations.
  • the processor 330 produces processed vertex data that is stored in an output buffer 340 that also is a part of the geometry accelerator 202.
  • data in the output buffer 340 is retrieved by the processor for further processing such as, for example, clipping operations.
  • the output buffer 340 preferably includes four vertex locations for storing all of the necessary vertex data for the vertices being processed. Accordingly, the output buffer 340 may include four vertex locations for storing all of the necessary vertex data. For some graphics operations, additional vertex locations may be necessary. These may be called “reserved vertex locations.” In preferred embodiments, each of the vertex locations in the output buffer 340 includes an array of thirty-two separate thirty-two bit words.
  • the geometry accelerator also includes a vertex handler 350 for retrieving the vertex data from the output buffer and transmitting such data to the rasterizer stage 204.
  • the vertex handler 350 is controlled by the processor 330 to retrieve the output vertex data.
  • the processor 330 signals the vertex handler when vertex data for one or more vertices has been processed and placed in the output buffer 340.
  • vertex data is partially processed and is sent to the output buffer 340 temporarily.
  • the partially processed vertex data is then retrieved by the processor 330 for further processing before rasterization. In such cases, the processor 330 signals the vertex handler 350 not to retrieve vertex data from the output buffer 340 until the processing is completed.
  • the vertex handler 350 also signals the processor 330 when the vertex handler 350 cannot retrieve vertex data from the output buffer 340, for example, when the rasterizer 204 cannot handle additional rasterization requests
  • two bits of the address are required to select which of the four individual vertex locations to access within the input buffer 320 and the output buffer 340.
  • two separate pointers are maintained for addressing the input buffer 320 and the output buffer 340. The addressing (i.e., indexing) of the input and output buffers is the same so that an input buffer vertex location and corresponding output buffer vertex location correspond to the same vertex. Keeping the two buffers in sync in this manner simplifies buffer addressing.
  • a specialized arithmetic logic unit (“ALU") support is provided in the form of increment and decrement instructions to traverse the input and output vertex buffers using modulo arithmetic. If an increment operation (i.e., an operation that adds one to a given pointer) results in a value that is greater than a predetermined maximum, then a "0" value is returned. If a decrement operation (i.e., an operation that subtracts one from a given pointer) results in a value that is less than "0", then the maximum value is returned.
  • the modulo counter With four vertex locations V0, VI, V2, and V3 in each of the input and output buffers, the modulo counter is configured with a maximum value of 3. The counter counts 0, 1, 2, 3, 0, 1, 2, 3, etc. to address these locations.
  • Performance may be improved by dynamically configuring the buffer addressing. More particularly, the buffer addressing is configured by setting the maximum value on the modulo counter so that fewer than all of the vertex locations may be accessed depending on the processing required. The vertex locations which are accessed may be called "addressable vertex locations.” The maximum value on the modulo counter, therefore, may be adjusted according to the graphics primitive being processed. In some cases involving a graphics primitive composed of sub-primitives, processing may be simplified by not using all of the available vertex locations. By setting the maximum value on the modulo counter so that the number of addressable vertex locations is equal to the sub-primitive size, simplified buffer addressing can be achieved.
  • the buffer addressing can be dynamically configured based upon the sub-primitive size (e.g., 1, 2, 3, or 4). For example, consider the Lstrip in Figure 5D.
  • Lstrip can be used as an approximation of a smooth curve drawn by connecting a series of consecutive vertices with lines, where each Line is defined by two vertices. Each subsequent line shares a vertex with the previous line.
  • the sub-primitive size is two.
  • the buffer addressing could be configured to use only two of the vertex locations. Vertex data for A is stored in vertex location V0 and vertex data for B is stored in vertex location
  • vertex data for B is stored in vertex location V0
  • vertex data for C is stored in vertex location VI.
  • vertex data for C is stored in vertex location V0 and so on.
  • the vertex data for a first vertex of a line is always accessed from vertex location V0
  • the vertex data for a second vertex of the line is always accessed from vertex location VI.
  • the modulo counter thus uses a maximum value of one, and counts 0, 1, 0, 1, etc.
  • vertex data for each odd-numbered vertex in the line request is accessed from vertex location V0, and when the modulo counter counts 1 , vertex data for each even-numbered vertex in the line request is accessed from vertex location VI. This simplifies the processing code used to process the primitive, which should access vertex data for corresponding vertices of each sub-primitive from the same vertex locations each time.
  • performance is improved by utilizing all of the vertex locations.
  • performance may be improved by using a maximum value of three, so that all four vertex locations are used and the modulo counter would count 0, 1, 2, 3, 0, 1,
  • the performance may be improved by using all four vertex locations, in this case, because vertex data for vertex C is already stored in the input buffer when the first line (vertices A and B) is being processed.
  • the next line (vertices B and C) can then processed without the need for the processor 330 to wait for vertex data for vertex B and vertex C to be stored in input vertex locations.
  • strip primitives preferably are processed in this same way, except that sub- primitives may share up to two vertices.
  • Tstrip and Qstrip shown in Figure 5D In the case of a Tstrip, each new vertex in the request stream
  • every second vertex in the request stream (starting with the fourth vertex) forms a sub-quad with the previous three vertices: ABCD, CDEF, EFGH, etc.
  • This processing can be performed in the same manner as described above for consecutive vertices, but must be done every time a new sub-primitive is formed
  • the buffer addressing can be dynamically configured to one less than the number of vertices (i.e., N-1). This leaves one vertex location out of the modulo arithmetic (buffer N, or V3 in a preferred embodiments), which can be used to hold the base vertex data that is a part of each sub-primitive.
  • vertex location V3 is not an addressable vertex location, because the modulo counter cannot generate an integer that designates vertex location V3.
  • the processor can subsequently access the base vertex data as needed by directly addressing vertex location V3 without using the modulo counter. Otherwise, the two most recent vertices can be accessed by using the modulo arithmetic.
  • the output buffer includes additional reserved vertex locations necessary for certain graphics operations. These reserved vertex locations are not addressable by the modulo arithmetic. Instead, these reserved vertex locations may be addressed in a manner similar to the addressing of the vertex location holding the base vertex data.
  • FIG 3B schematically shows an alternate embodiment of the geometry accelerator stage 202 shown in Figure 2.
  • the geometry accelerator further includes a vertex assembler 310 which receives input vertex data and passes it to the input buffer.
  • the vertex assembler 310 communicates with the processor and receives an address which designates a vertex location in the input buffer 320 in which to store vertex data for a single vertex.
  • the vertex assembler 310 also signals the processor 330 when vertex data is ready to be passed to the input buffer.

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  • Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)

Abstract

L'invention concerne un procédé et un accélérateur graphique qui traitent un polygone à N sommets et qui utilisent un emplacement de tampon pour un seul sommet afin de stocker des données pour un seul sommet de base du polygone au moment où celui-ci est traité. A cet effet, la méthode et le processeur graphique désignent d'abord un des sommets du polygone comme sommet de base, puis ils définissent N-2 différents triangles par chacun des sommets du polygone. Chacun des N-2 triangles est défini par le sommet de base et par deux autres des N-1 sommets. Un tampon est prévu pour stocker les données de sommet au moment où elles sont traitées. Ce tampon comporte un nombre choisi d'emplacements de sommet afin de stocker des données de sommet pour un sommet. Le nombre choisi est inférieur à N. Dans des modes de réalisation préférés, on peut extraire le sommet de base du premier emplacement de sommet, chaque fois qu'un des N-2 triangles est traité.
PCT/US1999/016080 1998-07-17 1999-07-15 Traitement graphique pour une manipulation efficace d'un polygone WO2000004502A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9318398P 1998-07-17 1998-07-17
US60/093,183 1998-07-17

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8976188B1 (en) 2012-04-20 2015-03-10 Google Inc. Optimized data communication system and method for an image rendering system
US9721363B2 (en) 2014-05-19 2017-08-01 Google Inc. Encoding polygon data for fast retrieval and rendering

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0448286A2 (fr) * 1990-03-16 1991-09-25 Hewlett-Packard Company Méthode et appareil pour la génération de zones, adressées arbitrairement et de forme arbitraire, dans un système graphique à ordinateur
EP0627682A1 (fr) * 1993-06-04 1994-12-07 Sun Microsystems, Inc. Processeur à virgule flottante pour un accélérateur graphique tri-dimensionnel à haute performance

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0448286A2 (fr) * 1990-03-16 1991-09-25 Hewlett-Packard Company Méthode et appareil pour la génération de zones, adressées arbitrairement et de forme arbitraire, dans un système graphique à ordinateur
EP0627682A1 (fr) * 1993-06-04 1994-12-07 Sun Microsystems, Inc. Processeur à virgule flottante pour un accélérateur graphique tri-dimensionnel à haute performance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8976188B1 (en) 2012-04-20 2015-03-10 Google Inc. Optimized data communication system and method for an image rendering system
US9721363B2 (en) 2014-05-19 2017-08-01 Google Inc. Encoding polygon data for fast retrieval and rendering

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