WO1999057852A1 - Hub port with constant phase - Google Patents
Hub port with constant phase Download PDFInfo
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- WO1999057852A1 WO1999057852A1 PCT/US1999/009428 US9909428W WO9957852A1 WO 1999057852 A1 WO1999057852 A1 WO 1999057852A1 US 9909428 W US9909428 W US 9909428W WO 9957852 A1 WO9957852 A1 WO 9957852A1
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- WIPO (PCT)
- Prior art keywords
- hub
- port
- data
- node
- clock signal
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/44—Star or tree networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L2007/045—Fill bit or bits, idle words
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
Definitions
- the present invention relates to an electronic network switching device, and more specifically to a network hub port which synchronizes data received from an attached node port to an internal clock in order to provide internal phase control.
- Network communication systems are frequently interconnected using network communication systems.
- Area-wide networks and channels are two approaches that have been developed for computer network architectures.
- Traditional networks e.g. , LAN's and WAN's
- Channels such as the Enterprise System Connection (ESCON) and the Small Computer System Interface (SCSI), have been developed for high performance and reliability.
- ESCON Enterprise System Connection
- SCSI Small Computer System Interface
- Fibre Channel a new network standard known as "Fibre Channel”.
- Fibre Channel systems combine the speed and reliability of channels with the flexibility and connectivity of networks.
- Fibre Channel products currently can run at very high data rates, such as 266 Mbps or 1062 Mbps. These speeds are sufficient to handle quite demanding applications, such as uncompressed, full motion, high-quality video.
- ANSI specifications such as X3.230-1994, define the Fibre Channel network. This specification distributes Fibre Channel functions among five layers.
- FC-0 the physical media layer
- FC-1 the coding and encoding layer
- FC-2 the actual transport mechanism, including the framing protocol and flow control between nodes
- FC-3 the common services layer
- FC-4 the upper layer protocol.
- Fibre Channel networks There are generally three ways to deploy a Fibre Channel network: simple point-to-point connections; arbitrated loops; and switched fabrics.
- the simplest topology is the point-to-point configuration, which simply connects any two Fibre Channel systems directly.
- Arbitrated loops are Fibre Channel ring connections that provide shared access to bandwidth via arbitration.
- Switched Fibre Channel networks called “fabrics", are a form of cross-point switching.
- FC-AL Fibre Channel Arbitrated Loop
- Hub ports 102 - 112 are interconnected by internal hub links 114, 116, 118, 120, 122, 124.
- Four node ports 126, 128, 130, 132 are attached to hub ports 102, 106, 110, 112, respectively.
- a physical star topology is created by node ports 126 - 132 around hub 100.
- hub ports 102 - 112 by internal hub links 114 - 124 forms an internal loop within hub 100 and creates a loop topology among node ports 126 - 132.
- Each node port is connected to a hub port by a pair of data channels.
- node port 126 is connected to hub port 102 by data channels 134 and 136.
- Data channel 134 transmits data from hub port 102 to node port 126.
- Data channel 136 transmits data from node port 126 to hub port 102. In this way, a datapath is created around the loop including each of the hub ports and the node ports.
- data received by a hub port from a node port may have a bit boundary which is out of phase and synchronization relative to data received by other hub ports in the loop ofthe same hub.
- Each node port transmits data to its corresponding hub port using a clock internal to that node port.
- each datastream introduced to the hub loop is sent with a different clock.
- the bit boundaries ofthe signals are often out of phase relative to one another.
- the node port recovers the clock signal from the datastream and synchronizes the datastream to its own internal clock, such as with a phase lock loop.
- Synchronization is typically detrimentally affected by switching hub ports in and out of bypass mode, such as upon the insertion and removal of node ports from the loop.
- a hub port which is connected to a node port receives two datastreams: one from the preceding hub port and one from the attached node port.
- the two datastreams are not necessarily synchronized because each is typically from a different node port and so has a different clock. If this switch occurs at a time which does not coincide with a bit boundary in the datastream, bit synchronization at the point in the datastream ofthe switch from one input to another is lost. The bit boundary shifts from that ofthe old datastream to that ofthe new datastream. Consequently, word synchronization may also be lost.
- hub port 106 receives data from hub port 104 and from node port 128.
- hub port 106 switches to bypass mode, such as when node port 128 is disconnected, hub port 106 stops outputting data from node port 128 and switches to outputting data received from hub port 104. Because the two datastreams are not necessarily in phase this switch may cause a loss in bit synchronization. - 4 -
- node port 130 When node port 130 attempts to recover the clock signal from the datastream, the recovery may fail causing node port 130 to re-synchronize the datastream.
- loop initialization primitive (“LIP”) primitive sequences may be generated by one or more node ports to reinitialize the loop.
- LIP primitive sequences are formed from three consecutive identical LIP ordered sets. LIP ordered sets are known and defined in conventional FC-AL protocols.
- node ports When node ports receive a LIP primitive sequence, node ports typically end ordinary processing and may generate LIP primitive sequences of their own. Under conventional FC-AL protocols, the loop may not return to ordinary processing for as long as approximately 500 to 600 microseconds. This delay is an undesirable result of synchronization errors.
- a hub port ofthe preferred embodiment provides a local clock internal to the hub.
- the local clock provides the ability to connect or disconnect a node port or loop segment attached to the hub port without disturbing the phase or bit boundary of data received at a downstream hub port.
- the hub port includes a smoothing circuit to synchronize data received from the attached node port to a local clock that is internal to the hub and common to all hub ports in the hub. As a result, a constant phase or bit boundary is maintained in the datastream ofthe hub loop. A hub port is switched in and out of bypass mode only on a bit boundary. Because the data received at a downstream hub port has a constant phase or bit boundary when a node port attached to an upstream hub port is connected or disconnected, the node port attached to the downstream hub port does not lose synchronization as a result ofthe change at the upstream hub port.
- An additional advantage ofthe preferred embodiment is that the transmission of data to an attached node port using the local clock substantially eliminates the transfer of "jitter" (time based noise, i.e., loss of precision in the signal) in the signal transmitted to a node port. This reduction in jitter reduces synchronization errors, improves the bit-error rate, and improves hub cascadability.
- jitter time based noise, i.e., loss of precision in the signal
- FIG. 1 shows a prior art configuration of a loop including a hub.
- FIG. 2 is a block diagram of a first preferred implementation of a hub port.
- FIG. 3 is a block diagram of a second preferred implementation of a hub port.
- FC-AL Fibre Channel Arbitrated Loop
- a hub port maintains constant phase in the datastream ofthe hub loop.
- the phase shift problem of conven- tional hub ports is typically caused by the difference in phase ofthe clocks for the datastreams entering the hub port.
- This implementation synchronizes data received from a node port to a local clock before introducing that data to the hub loop.
- Each hub port may receive data from potentially two sources: an attached node port and an upstream hub port. While a hub port is not connected to a node port, the hub port is in bypass mode and passes data from the upstream hub port to a downstream hub port. When a node port is connected to a hub port and is transmit- ting valid data to the hub port, the hub port switches out of bypass mode and switches from outputting the datastream from the upstream hub port to outputting the datastream from the node port.
- the hub port monitors data received from the attached node port and synchronizes that data to the local clock signal using a smoothing circuit.
- the node port transmits data to the hub port using a clock internal to the node port.
- the hub port recovers the node port's clock signal from the data from the node port and uses that recovered clock signal to receive the data from the node port.
- the frequencies ofthe recovered clock signal and the local clock signal are typically similar but not necessarily the same and so the smoothing circuit inserts and deletes fill words from the datastream to compensate for lack of synchronization.
- the hub port ensures that data from the node port enters the datastream ofthe loop only upon bit and word boundaries. Because each hub port in the hub inserts data into the hub loop using a local clock, the datastream on the hub loop is synchronized to the local clock.
- the switch from one datastream to another does not affect the phase ofthe datastream on the hub loop.
- switching from the datastream from the node port to the datastream from the upstream hub port does not affect the phase ofthe hub loop datastream.
- a hub port 200 includes an incoming internal hub link 202 connected to a data input of a switching device such as a multiplexer 204 and to a transmit circuit 206.
- Transmit circuit 206 transmits data along data channel 208 to node port 210.
- Node port 210 transmits data to hub port 200 along data channel 212.
- Data channel 212 is connected to a receive circuit 214 - 7 - and a clock recovery circuit 216.
- Clock recovery circuit 216 recovers a clock signal from data received from node port 210 and supplies that clock signal to receive circuit 214.
- Receive circuit 214 outputs data using the recovered clock signal to smoothing circuit 218. Smoothing circuit 218 is connected to a hub clock line 220.
- Hub clock line 220 is connected to a clock (not shown) which is internal to the hub containing hub port 200.
- Hub clock line 220 is connected to each hub port in the hub containing hub port 200.
- Smoothing circuit 218 outputs data to a data input of multiplexer 204 using the hub clock signal. Smoothing circuit 218 also supplies control signals to a control input of multiplexer 204 to control the selection of inputs for multiplexer 204.
- Multiplexer 204 outputs data onto outgoing internal hub link 222 into the hub loop of the hub containing hub port 200.
- Hub port 200 synchronizes all data received from node port 210 to a local clock through smoothing circuit 218 and hub clock line 220. The data is then output onto outgoing internal hub link 222. All data entering the loop is synchronized to the same local clock because each hub port in the hub is connected to a common local clock.
- multiplexer 204 has two data inputs: one connected to smoothing circuit 218 and one connected to incoming internal hub link 202. Because all data on the internal hub links is synchronized to the same local clock as the local clock connected to smoothing circuit 218, the phases ofthe two datastreams are the same. Thus, when hub port 200 switches between the data inputs of multiplexer 204, the phase and bit boundaries ofthe datastreams received at downstream node ports are not disrupted.
- Hub clock line 220 also supplies a local clock signal to transmit circuit 206. Transmit circuit 206 transmits data to node port 210 using the local clock signal. By transmitting with a clean clock signal rather than a recovered clock signal, the transfer of jitter (i.e., noise in the data signal which may accumulate as the signal passes through logic circuits) from hub port 200 to node port 210 is reduced and preferably eliminated.
- jitter i.e., noise in the data signal which may accumulate as the signal passes through logic circuits
- FIG. 3 is a block diagram of a second preferred implementation of a hub port 300 showing the components in more detail.
- Hub port 300 includes components - 8 - for transmitting data to a node port 314, for receiving data from node port 314, and for bypassing or inserting node port 314 in and out ofthe hub loop.
- An incoming internal hub link 302 connects hub port 300 to an upstream hub port (not shown) in the loop ofthe hub containing hub port 300.
- Incoming internal hub link 302 is connected to a data input of a multiplexer 304 and to an encoder 306.
- Encoder 306 is preferably a conventional 8B/10B encoder.
- Encoder 306 is connected to a transmit circuit 308.
- Transmit circuit 308 is connected to a serializer/deserializer ("SERDES") circuit 310.
- SERDES circuit 310 serializes data and sends the data through a data channel 312 to node port 314.
- Each of encoder 306, transmit circuit 308, and SERDES circuit 310 is connected to hub clock line 336 and outputs data using that clock signal.
- a data channel 316 carries data from node port 314 to SERDES circuit
- SERDES circuit 310 deserializes serial data received from node port 314 and passes the data to a receive circuit 318.
- SERDES circuit 310 also recovers a clock signal from the deserialized data.
- SERDES circuit 310 sends the recovered clock signal via a recovered clock line 317 to receive circuit 318, a word synchronization detect circuit 322 and a "smoothing" first-in-first-out (“FIFO”) buffer 324.
- smoothing buffer 324 need not be a FIFO buffer.
- Receive circuit 318 passes the data to a decoder 320.
- Decoder 320 is preferably a conventional 10B/8B decoder. Decoder 320 passes the decoded data to word synchronization detect circuit 322 and smoothing FIFO buffer 324.
- Word synchronization detect circuit 322 is connected to a smoothing FIFO control circuit 326, which is also coupled to smoothing FIFO buffer 324.
- Smoothing FIFO buffer 324 is connected to a data input of multiplexer 304, a fill word detect circuit 330, and a current fill word generator 332.
- Current fill word generator 332 is connected to fill word detect circuit 330 and to a data input of multiplexer 304.
- Smoothing FIFO control circuit 326 is connected to a hub port output control circuit 328, which is - 9 - connected to a control input of multiplexer 304.
- Multiplexer 304 is connected to an output register 334.
- a hub clock line 336 is connected to a local clock (not shown).
- the local clock is preferably connected to each hub port in the hub and supplies a common local clock signal to each hub port in the hub.
- Hub clock line 336 supplies a local clock signal to encoder 306, transmit circuit 308, SERDES circuit 310, smoothing FIFO buffer 324, current fill word generator 332, and output register 334.
- Output register 334 outputs data from multiplexer 304 onto outgoing internal hub link 338 using the local clock. Output register 334 functions as a pipeline stage between connecting hub ports.
- smoothing FIFO buffer 324 In receiving data from an attached node port 314, an important part ofthe preferred hub port design is smoothing FIFO buffer 324 and smoothing FIFO control circuit 326. Smoothing FIFO buffer 324 in conjunction with smoothing FIFO control circuit 326 synchronizes data received from node port 314 to the internal clock ofthe hub port. Smoothing FIFO buffer 324 provides a smoothing function between the two potentially asynchronous clock domains ofthe clock signal recovered from the data and the local clock of hub port 300.
- SERDES circuit 310 deserializes an incoming serial datastream from node port 314, generating deserialized 1 OB-encoded data.
- SERDES circuit 310 also recovers a clock signal from the serial data.
- SERDES circuit 310 outputs the recovered clock signal to recovered clock line 317 to be received by receive circuit 318, word synchronization detect circuit 322 and smoothing FIFO buffer 324.
- Receive circuit 318 receives the 1 OB-encoded data and outputs the data to decoder 320, synchronized to the recovered clock signal. Decoder 320 then performs a 10B/8B decoding ofthe data. The decoded data is forwarded to word synchronization detect circuit 322 and smoothing FIFO buffer 324.
- Word synchronization detect circuit 322 preferably follows procedures defined in clause 12.1 of ANSI publication X3.230-1994 (FC-PH, Rev 4.3, June 1, 1994). In particular, when word synchronization detect circuit 322 detects three - 10 - consecutive valid Fibre Channel ordered sets emerging from decoder 320, hub port 300 has acquired word synchronization and word synchronization detect circuit 322 enters a synchronization-acquired state. Word synchronization detect circuit 322 enables smoothing FIFO control circuit 326, which in turn enables subsequent Fibre Channel words to be written into smoothing FIFO buffer 324.
- word synchronization detect circuit 322 enters a synchronization-lost state.
- Smoothing FIFO control circuit 326 disables words from being written into smoothing FIFO buffer 324 if word synchronization is lost.
- Smoothing FIFO buffer 324 includes a FIFO buffer and, in conjunction with smoothing FIFO control circuit 326, synchronizes the received Fibre Channel data to the local clock frequency on hub clock line 336.
- Data received from node port 314 is written into smoothing FIFO buffer 324 at a data rate determined by the recovered clock on recovered clock line 317.
- the data is synchronized to the local clock signal determined by a local oscillator (not shown in FIG. 3) within the hub.
- Data is output from smoothing FIFO buffer 324 into multiplexer 304 at a data rate determined by the local clock signal on hub clock line 336.
- Multiplexer 304 outputs data into output register 334. Switching of multiplexer 304 is controlled by hub output control circuit 328, which is connected to the control input of multiplexer 304.
- hub output control circuit 328 When data received from node port 314 is to be inserted into the loop, the data input corresponding to smoothing FIFO buffer 324 is selected.
- the data input corresponding to current fill word generator 330 When fill words are to be inserted into the loop (described below), the data input corresponding to current fill word generator 330 is selected.
- hub port 300 is in a bypass mode, the data input corresponding to incoming internal hub link 302 is selected. Each ofthe datastreams have the same phase and switching among the data inputs occurs on bit boundaries to preserve the constant phase.
- Output data register 334 outputs data onto outgoing internal hub link 338 using the local clock signal received on hub clock line 336. - 11 -
- the recovered clock frequency and the local clock frequency may vary by a small amount, such as ⁇ lOOppm.
- the difference in the recovered and local clock frequencies results in a difference between the data rates for writing data into (using the recovered clock signal) and removing data from (using the local clock signal) smoothing FIFO buffer 324.
- Smoothing FIFO control circuit 326 "smooths" out the differences in incoming and outgoing data rates for smoothing FIFO buffer 324 using fill words.
- Fill words are typically inserted into inter-frame gaps between data frames in Fibre Channel datastreams. Essentially every datastream includes some number of fill words.
- a current fill word is typically selected from a list formed according to FC-AL protocols.
- smoothing FIFO control circuit 326 By scheduling either insertions or deletions of current fill words when the amount of data in smoothing FIFO buffer 324 reaches various thresholds, smoothing FIFO control circuit 326 prevents smoothing FIFO buffer 324 from running dry or from overflowing.
- smoothing FIFO control circuit 326 determines that deleting a fill word is appropriate, smoothing FIFO control circuit 326 waits until a suitable fill word is found in an inter-frame gap before a delete is performed.
- smoothing FIFO control circuit 326 waits for an inter-frame gap and then causes multiplexer 304 to select the data input corresponding to current fill word generator 332 to be output to output register 334.
- smoothing FIFO control circuit 326 temporarily stalls data reads from smoothing FIFO buffer 324.
- fill word detect circuit 330 Connected to current fill word generator 332 is fill word detect circuit 330.
- Fill word detect circuit 330 keeps track ofthe latest suitable fill word by updating current fill word generator 332 with the fill word to be used if a fill word insert is appropriate.
- smoothing FIFO buffer 324 As data is removed from smoothing FIFO buffer 324 and output to multiplexer 304, if the local clock frequency is faster than the recovered clock frequency, the amount of data in smoothing FIFO buffer 324 diminishes. The amount of data in smoothing FIFO buffer 324 may also diminish when writing into smoothing FIFO buffer 324 is disabled due to loss of word synchronization. If the amount of data in smoothing FIFO buffer 324 falls below a minimum threshold, smoothing FIFO control circuit 326 causes hub port output control circuit 328 to bypass hub port - 12 -
- Hub port output control circuit 328 causes multiplexer 304 to select the data input corresponding to incoming internal hub link 302 to output data directly from the upstream hub port rather than the output of smoothing FIFO buffer 324.
- smoothing FIFO control circuit 326 causes hub port output control circuit 328 to end the bypass.
- Hub port output control circuit 328 causes multiplexer 304 to select data from smoothing FIFO buffer 324, returning node port 314 to the loop.
- different thresholds may be used for removing and inserting node ports into the loop. If the local clock frequency is slower than the recovered clock frequency, the amount of data in smoothing FIFO buffer 324 increases. If the amount of data in smoothing FIFO buffer 324 exceeds a maximum threshold, smoothing FIFO control circuit 326 deletes fill words as described above.
- hub port 300 In operation, when hub port 300 is not connected to a node port 314, hub port 300 is in bypass mode. Multiplexer 304 connects the data input corresponding to incoming internal hub link 302 to output register 334. When node port 314 is initially connected to hub port 300 and begins transmitting a datastream, a process similar to that described above occurs. The data is deserialized by SERDES circuit 310, decoded by decoder 320, and supplied to word synchronization detect circuit 322. If valid ordered sets are being received, word synchronization detect circuit 322 enters a synchronization-acquired state and the received data starts to be written into smoothing FIFO buffer 324.
- smoothing FIFO buffer 324 exceeds a minimum threshold.
- smoothing FIFO control circuit 326 causes hub port output control circuit 328 to end bypass mode for hub port 300.
- Hub port output control circuit 328 causes multiplexer 304 to select the data input corresponding to smoothing FIFO buffer 324 rather than data from the upstream hub port on incoming internal hub link 302. Because data received from node port 314 is inserted into the loop using a local clock signal to read data out of smoothing FIFO buffer 324, node port 314 is inserted into the loop without disrupting the synchronization ofthe datastream.
- word synchronization detect circuit 322 detects the loss of valid synchronized data and enters a synchronization-lost state. Subsequent data is not written into smoothing FIFO buffer 324. Data continues to be removed from smoothing FIFO buffer 324 and output by multiplexer 304 to output register 334 causing smoothing FIFO buffer 324 to approach empty.
- smoothing FIFO control circuit 326 when smoothing FIFO control circuit 326 detects that smoothing FIFO buffer 324 has fallen below a minimum threshold, smoothing FIFO control circuit 326 causes hub port output control circuit 328 to bypass hub port 300.
- Hub port output control circuit 328 causes multiplexer 304 to select the data input corresponding to incoming internal hub link 302 and data from the upstream hub port.
- hub port 300 while valid data is not received from node port 314, hub port 300 enters a bypass mode. Because the bypass occurs in synchronization with the local clock signal, the failure of node port 314 does not disrupt the datastream of the loop.
- encoder 306 In transmitting data from hub port 300 to node port 314, encoder 306 encodes the un-encoded Fibre Channel data, preferably using 8B/10B encoding, received along incoming internal hub link 302 from the upstream hub port. Encoder 306 does not incorporate a clock signal recovered by the SERDES circuit of an upstream hub port because that recovered clock signal is not sent by that upstream hub port. As described above, data is output onto outgoing internal hub link 338 of a hub port using the local clock signal on hub clock line 336, not the recovered clock signal. Encoder 306 preferably incorporates the local clock signal on hub clock line 336. The encoded data is forwarded to transmit circuit 308. Transmit circuit 308 ensures that only complete words are transmitted to node port 314.
- transmit circuit 308 automatically adjusts the running disparity (i.e., the difference between the number of 1 's and 0's in the data signal) ofthe data as necessary, such as by changing the disparity to positive or negative.
- the data is passed to SERDES circuit 310 to be serialized and transmitted to node port 314 using the local clock on hub clock line 336. As described above, by transmitting data to node port 314 using - 14 - the local clock signal, substantially no jitter which may have accumulated in the datastream is transferred to node port 314.
- a node port or a loop segment of multiple node ports may be seamlessly inserted into or removed from the loop by a hub port without causing a disruption in the phase of data transmitted to the downstream node port.
- jitter transfer between hub ports is substantially eliminated.
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- Signal Processing (AREA)
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- Synchronisation In Digital Transmission Systems (AREA)
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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CA002330743A CA2330743C (en) | 1998-05-01 | 1999-04-28 | Hub port with constant phase |
EP99918920A EP1074118A4 (en) | 1998-05-01 | 1999-04-28 | Hub port with constant phase |
JP2000547736A JP3734016B2 (en) | 1998-05-01 | 1999-04-28 | Hub port with constant phase |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/071,932 | 1998-05-01 | ||
US09/071,932 US6157652A (en) | 1998-05-01 | 1998-05-01 | Hub port with constant phase |
Publications (1)
Publication Number | Publication Date |
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WO1999057852A1 true WO1999057852A1 (en) | 1999-11-11 |
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PCT/US1999/009428 WO1999057852A1 (en) | 1998-05-01 | 1999-04-28 | Hub port with constant phase |
Country Status (6)
Country | Link |
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US (1) | US6157652A (en) |
EP (1) | EP1074118A4 (en) |
JP (1) | JP3734016B2 (en) |
KR (1) | KR100393927B1 (en) |
CA (1) | CA2330743C (en) |
WO (1) | WO1999057852A1 (en) |
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US6459701B1 (en) * | 1999-08-06 | 2002-10-01 | Emulex Corporation | Variable access fairness in a fibre channel arbitrated loop |
US7570724B1 (en) * | 1999-10-14 | 2009-08-04 | Pluris, Inc. | Method of link word synchronization |
WO2004002094A1 (en) * | 2002-06-25 | 2003-12-31 | Lockheed Martin Corporation | Method to increase the hamming distance between frame delimiter symbol and data symbols of a mbnb line code |
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-
1999
- 1999-04-28 WO PCT/US1999/009428 patent/WO1999057852A1/en not_active Application Discontinuation
- 1999-04-28 EP EP99918920A patent/EP1074118A4/en not_active Withdrawn
- 1999-04-28 CA CA002330743A patent/CA2330743C/en not_active Expired - Fee Related
- 1999-04-28 JP JP2000547736A patent/JP3734016B2/en not_active Expired - Fee Related
- 1999-04-28 KR KR10-2000-7012120A patent/KR100393927B1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
EP1074118A1 (en) | 2001-02-07 |
JP2002514845A (en) | 2002-05-21 |
US6157652A (en) | 2000-12-05 |
EP1074118A4 (en) | 2005-08-03 |
CA2330743C (en) | 2004-04-06 |
JP3734016B2 (en) | 2006-01-11 |
CA2330743A1 (en) | 1999-11-11 |
KR100393927B1 (en) | 2003-08-06 |
KR20010043195A (en) | 2001-05-25 |
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